include/configs/p3mx.h

   1 /*
   2  * (C) Copyright 2006
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * Based on original work by
   6  *      Roel Loeffen, (C) Copyright 2006 Prodrive B.V.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 /************************************************************************
  28  * p3mx.h - configuration for Prodrive P3M750 & P3M7448 boards
  29  *
  30  * The defines:
  31  * CONFIG_P3M750 or
  32  * CONFIG_P3M7448
  33  * are written into include/config.h by the "make xxx_config" command
  34  ***********************************************************************/
  35 #ifndef __CONFIG_H
  36 #define __CONFIG_H
  37
  38 /*-----------------------------------------------------------------------
  39  * High Level Configuration Options
  40  *----------------------------------------------------------------------*/
  41 #define CONFIG_P3Mx                     /* used for both board versions */
  42
  43 #define CONFIG_SYS_TEXT_BASE    0xfff00000
  44
  45 #if defined (CONFIG_P3M750)
  46 #define CONFIG_750FX                    /* 750GL/GX/FX                  */
  47 #define CONFIG_HIGH_BATS                /* High BATs supported          */
  48 #define CONFIG_SYS_BOARD_NAME           "P3M750"
  49 #define CONFIG_SYS_BUS_CLK              100000000
  50 #define CONFIG_SYS_TCLK         100000000
  51 #elif defined (CONFIG_P3M7448)
  52 #define CONFIG_74xx
  53 #define CONFIG_SYS_BOARD_NAME           "P3M7448"
  54 #define CONFIG_SYS_BUS_CLK              133333333
  55 #define CONFIG_SYS_TCLK         133333333
  56 #endif
  57 #define CONFIG_SYS_GT_DUAL_CPU                  /* also for JTAG even with one cpu */
  58
  59 /* which initialization functions to call for this board */
  60 #define CONFIG_SYS_BOARD_ASM_INIT       1
  61 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f      */
  62 #define CONFIG_MISC_INIT_R      1       /* Call misc_init_r()           */
  63
  64 /*-----------------------------------------------------------------------
  65  * Base addresses -- Note these are effective addresses where the
  66  * actual resources get mapped (not physical addresses)
  67  *----------------------------------------------------------------------*/
  68 #define CONFIG_SYS_SDRAM_BASE           0x00000000
  69 #ifdef CONFIG_P3M750
  70 #define CONFIG_SYS_SDRAM1_BASE          0x10000000      /* each 256 MByte       */
  71 #endif
  72
  73 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
  74 #if defined (CONFIG_P3M750)
  75 #define CONFIG_SYS_FLASH_BASE           0xff800000      /* start of flash banks */
  76 #define CONFIG_SYS_BOOT_SIZE            _8M             /* boot flash           */
  77 #elif defined (CONFIG_P3M7448)
  78 #define CONFIG_SYS_FLASH_BASE           0xff000000      /* start of flash banks */
  79 #define CONFIG_SYS_BOOT_SIZE            _16M            /* boot flash           */
  80 #endif
  81 #define CONFIG_SYS_BOOT_SPACE           CONFIG_SYS_FLASH_BASE   /* BOOT_CS0 flash 0    */
  82 #define CONFIG_SYS_MONITOR_BASE 0xfff00000
  83 #define CONFIG_SYS_RESET_ADDRESS        0xfff00100
  84 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)     /* Reserve 256 kB for malloc */
  85 #define CONFIG_SYS_MISC_REGION_BASE     0xf0000000
  86
  87 #define CONFIG_SYS_DFL_GT_REGS          0xf1000000      /* boot time GT_REGS */
  88 #define CONFIG_SYS_GT_REGS              0xf1000000      /* GT Registers are mapped here */
  89 #define CONFIG_SYS_INT_SRAM_BASE        0x42000000      /* GT offers 256k internal SRAM */
  90
  91 /*-----------------------------------------------------------------------
  92  * Initial RAM & stack pointer (placed in internal SRAM)
  93  *----------------------------------------------------------------------*/
  94  /*
  95  * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS
  96  * To an unused memory region. The stack will remain in cache until RAM
  97  * is initialized
  98 */
  99 #undef  CONFIG_SYS_INIT_RAM_LOCK
 100 #define CONFIG_SYS_INIT_RAM_ADDR        0x42000000
 101 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000
 102 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 103
 104
 105 /*-----------------------------------------------------------------------
 106  * Serial Port
 107  *----------------------------------------------------------------------*/
 108 #define CONFIG_MPSC                     /* MV64460 Serial               */
 109 #define CONFIG_MPSC_PORT        0
 110 #define CONFIG_BAUDRATE         115200  /* console baudrate             */
 111 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
 112 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 113 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 114
 115 /*-----------------------------------------------------------------------
 116  * Ethernet
 117  *----------------------------------------------------------------------*/
 118 /* Change the default ethernet port, use this define (options: 0, 1, 2) */
 119 #define CONFIG_SYS_ETH_PORT             ETH_0
 120 #define CONFIG_NET_MULTI
 121 #define MV_ETH_DEVS             2
 122 #define CONFIG_PHY_RESET        1       /* reset phy upon startup         */
 123 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 124
 125 /*-----------------------------------------------------------------------
 126  * FLASH related
 127  *----------------------------------------------------------------------*/
 128 #define CONFIG_SYS_FLASH_CFI                    /* The flash is CFI compatible          */
 129 #define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver                */
 130 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 131 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip    */
 132 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 133 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 134 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
 135 #define CONFIG_SYS_FLASH_PROTECTION     1       /* use hardware flash protection        */
 136 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 137
 138 #define CONFIG_ENV_IS_IN_FLASH     1    /* use FLASH for environment vars       */
 139 #if defined (CONFIG_P3M750)
 140 #define CONFIG_ENV_SECT_SIZE    0x20000 /* one sector (1 device)                */
 141 #elif defined (CONFIG_P3M7448)
 142 #define CONFIG_ENV_SECT_SIZE    0x40000 /* two sectors (2 devices parallel      */
 143 #endif
 144 #define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector     */
 145 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 146
 147 /*-----------------------------------------------------------------------
 148  * DDR SDRAM
 149  *----------------------------------------------------------------------*/
 150 #define CONFIG_MV64460_ECC
 151
 152 /*-----------------------------------------------------------------------
 153  * I2C
 154  *----------------------------------------------------------------------*/
 155 #define CONFIG_SYS_I2C_SPEED            100000          /* I2C speed default    */
 156
 157 /* I2C RTC */
 158 #define CONFIG_RTC_M41T11       1
 159 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 160 #define CONFIG_SYS_M41T11_BASE_YEAR     1900    /* play along with linux        */
 161
 162 /*-----------------------------------------------------------------------
 163  * PCI stuff
 164  *----------------------------------------------------------------------*/
 165 #define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
 166 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 167 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 168
 169 #undef CONFIG_PCI                       /* include pci support          */
 170 #ifdef CONFIG_PCI
 171 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
 172 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 173 #define CONFIG_PCI_SCAN_SHOW            /* show devices on bus          */
 174 #endif /* CONFIG_PCI */
 175
 176 /* PCI MEMORY MAP section */
 177 #define CONFIG_SYS_PCI0_MEM_BASE        0x80000000
 178 #define CONFIG_SYS_PCI0_MEM_SIZE        _128M
 179 #define CONFIG_SYS_PCI1_MEM_BASE        0x88000000
 180 #define CONFIG_SYS_PCI1_MEM_SIZE        _128M
 181
 182 #define CONFIG_SYS_PCI0_0_MEM_SPACE     (CONFIG_SYS_PCI0_MEM_BASE)
 183 #define CONFIG_SYS_PCI1_0_MEM_SPACE     (CONFIG_SYS_PCI1_MEM_BASE)
 184
 185 /* PCI I/O MAP section */
 186 #define CONFIG_SYS_PCI0_IO_BASE 0xfa000000
 187 #define CONFIG_SYS_PCI0_IO_SIZE _16M
 188 #define CONFIG_SYS_PCI1_IO_BASE 0xfb000000
 189 #define CONFIG_SYS_PCI1_IO_SIZE _16M
 190
 191 #define CONFIG_SYS_PCI0_IO_SPACE        (CONFIG_SYS_PCI0_IO_BASE)
 192 #define CONFIG_SYS_PCI0_IO_SPACE_PCI    0x00000000
 193 #define CONFIG_SYS_PCI1_IO_SPACE        (CONFIG_SYS_PCI1_IO_BASE)
 194 #define CONFIG_SYS_PCI1_IO_SPACE_PCI    0x00000000
 195
 196 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS (CONFIG_SYS_PCI0_IO_BASE)
 197 #define CONFIG_SYS_PCI_IDSEL 0x30
 198
 199 #undef  CONFIG_BOOTARGS
 200 #define CONFIG_EXTRA_ENV_SETTINGS_COMMON                                \
 201         "netdev=eth0\0"                                                 \
 202         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 203                 "nfsroot=${serverip}:${rootpath}\0"                     \
 204         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 205         "addip=setenv bootargs ${bootargs} "                            \
 206                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 207                 ":${hostname}:${netdev}:off panic=1\0"                  \
 208         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 209         "flash_nfs=run nfsargs addip addtty;"                           \
 210                 "bootm ${kernel_addr}\0"                                \
 211         "flash_self=run ramargs addip addtty;"                          \
 212                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 213         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 214                 "bootm\0"                                               \
 215         "rootpath=/opt/eldk/ppc_6xx\0"                                  \
 216         "u-boot=p3mx/u-boot/u-boot.bin\0"                               \
 217         "load=tftp 100000 ${u-boot}\0"                                  \
 218         "update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;"   \
 219                 "cp.b 100000 fff00000 40000;"                           \
 220                 "setenv filesize;saveenv\0"                             \
 221         "upd=run load update\0"                                         \
 222         "serverip=11.0.0.152\0"
 223
 224 #if defined (CONFIG_P3M750)
 225 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 226         CONFIG_EXTRA_ENV_SETTINGS_COMMON                                \
 227         "hostname=p3m750\0"                                             \
 228         "bootfile=/tftpboot/p3mx/vxWorks.st\0"                          \
 229         "kernel_addr=fc000000\0"                                        \
 230         "ramdisk_addr=fc180000\0"                                       \
 231         "vxfile=p3m750/vxWorks\0"                                       \
 232         "vxuser=ddg\0"                                                  \
 233         "vxpass=ddg\0"                                                  \
 234         "vxtarget=target\0"                                             \
 235         "vxflags=0x8\0"                                                 \
 236         "vxargs=setenv bootargs mgi(0,0)host:${vxfile} h=${serverip} "  \
 237                 "e=${ipaddr} u=${vxuser} pw=${vxpass} tn=${vxtarget} "  \
 238                 "f=${vxflags}\0"
 239 #elif defined (CONFIG_P3M7448)
 240 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 241         CONFIG_EXTRA_ENV_SETTINGS_COMMON                                \
 242         "hostname=p3m7448\0"
 243 #endif
 244
 245 #if defined (CONFIG_P3M750)
 246 #define CONFIG_BOOTCOMMAND      "tftp;run vxargs;bootvx"
 247 #elif defined (CONFIG_P3M7448)
 248 #define CONFIG_BOOTCOMMAND      " "
 249 #endif
 250
 251 #define CONFIG_BOOTDELAY        3       /* autoboot after 5 seconds */
 252
 253 /*
 254  * BOOTP options
 255  */
 256 #define CONFIG_BOOTP_SUBNETMASK
 257 #define CONFIG_BOOTP_GATEWAY
 258 #define CONFIG_BOOTP_HOSTNAME
 259 #define CONFIG_BOOTP_BOOTPATH
 260 #define CONFIG_BOOTP_BOOTFILESIZE
 261
 262 /*
 263  * Command line configuration.
 264  */
 265 #include <config_cmd_default.h>
 266
 267 #define CONFIG_CMD_ASKENV
 268 #define CONFIG_CMD_DATE
 269 #define CONFIG_CMD_DIAG
 270 #define CONFIG_CMD_ELF
 271 #define CONFIG_CMD_I2C
 272 #define CONFIG_CMD_IRQ
 273 #define CONFIG_CMD_MII
 274 #define CONFIG_CMD_NET
 275 #define CONFIG_CMD_NFS
 276 #define CONFIG_CMD_PING
 277 #define CONFIG_CMD_REGINFO
 278 #define CONFIG_CMD_PCI
 279 #define CONFIG_CMD_CACHE
 280 #define CONFIG_CMD_SDRAM
 281
 282
 283 /*-----------------------------------------------------------------------
 284  * Miscellaneous configurable options
 285  *----------------------------------------------------------------------*/
 286 #define CONFIG_SYS_HUSH_PARSER
 287 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 288
 289 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 290 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt       */
 291 #if defined(CONFIG_CMD_KGDB)
 292 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 293 #else
 294 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 295 #endif
 296 #define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 297 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 298 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size  */
 299
 300 #define CONFIG_SYS_MEMTEST_START        0x0400000 /* memtest works on           */
 301 #define CONFIG_SYS_MEMTEST_END          0x0C00000 /* 4 ... 12 MB in DRAM        */
 302
 303 #define CONFIG_SYS_LOAD_ADDR            0x08000000      /* default load address */
 304
 305 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 306
 307 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 308 #define CONFIG_LOOPW            1       /* enable loopw command         */
 309 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 310 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 311 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 312
 313 /*-----------------------------------------------------------------------
 314  * Marvell MV64460 config settings
 315  *----------------------------------------------------------------------*/
 316 /* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected device width */
 317 #if defined (CONFIG_P3M750)
 318 #define CONFIG_SYS_BOOT_PAR             0x8FDFF87F      /* 16 bit flash, disable burst*/
 319 #elif defined (CONFIG_P3M7448)
 320 #define CONFIG_SYS_BOOT_PAR             0x8FEFFFFF      /* 32 bit flash, burst enabled */
 321 #endif
 322
 323 /*
 324  * MPP[0]       Serial Port 0 TxD       TxD     OUT     Connected to P14 (buffered)
 325  * MPP[1]       Serial Port 0 RxD       RxD     IN      Connected to P14 (buffered)
 326  * MPP[2]       NC
 327  * MPP[3]       Serial Port 1 TxD       TxD     OUT     Connected to P14 (buffered)
 328  * MPP[4]       PCI Monarch#            GPIO    IN      Connected to P12
 329  * MPP[5]       Serial Port 1 RxD       RxD     IN      Connected to P14 (buffered)
 330  * MPP[6]       PMC Carrier Interrupt 0 Int     IN      Connected to P14
 331  * MPP[7]       PMC Carrier Interrupt 1 Int     IN      Connected to P14
 332  * MPP[8]       Reserved                                Do not use
 333  * MPP[9]       Reserved                                Do not use
 334  * MPP[10]      Reserved                                Do not use
 335  * MPP[11]      Reserved                                Do not use
 336  * MPP[12]      Phy 0 Interrupt         Int     IN
 337  * MPP[13]      Phy 1 Interrupt         Int     IN
 338  * MPP[14]      NC
 339  * MPP[15]      NC
 340  * MPP[16]      PCI Interrupt C         Int     IN      Connected to P11
 341  * MPP[17]      PCI Interrupt D         Int     IN      Connected to P11
 342  * MPP[18]      Watchdog NMI#           GPIO    IN      Connected to MPP[24]
 343  * MPP[19]      Watchdog Expired#       WDE     OUT     Connected to rst logic
 344  * MPP[20]      Watchdog Status         WD_STS  IN      Read back of rst by watchdog
 345  * MPP[21]      NC
 346  * MPP[22]      GP LED Green            GPIO    OUT
 347  * MPP[23]      GP LED Red              GPIO    OUT
 348  * MPP[24]      Watchdog NMI#           Int     OUT
 349  * MPP[25]      NC
 350  * MPP[26]      NC
 351  * MPP[27]      PCI Interrupt A         Int     IN      Connected to P11
 352  * MPP[28]      NC
 353  * MPP[29]      PCI Interrupt B         Int     IN      Connected to P11
 354  * MPP[30]      Module reset            GPIO    OUT     Board reset
 355  * MPP[31]      PCI EReady              GPIO    IN      Connected to P12
 356  */
 357 #define CONFIG_SYS_MPP_CONTROL_0        0x00303022
 358 #define CONFIG_SYS_MPP_CONTROL_1        0x00000000
 359 #define CONFIG_SYS_MPP_CONTROL_2        0x00004000
 360 #define CONFIG_SYS_MPP_CONTROL_3        0x00000004
 361 #define CONFIG_SYS_GPP_LEVEL_CONTROL    0x280730D0
 362
 363 /*----------------------------------------------------------------------
 364  * Initial BAT mappings
 365  */
 366
 367 /* NOTES:
 368  * 1) GUARDED and WRITE_THRU not allowed in IBATS
 369  * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
 370  */
 371 /* SDRAM */
 372 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 373 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 374 #define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT)
 375 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
 376
 377 /* init ram */
 378 #define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
 379 #define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
 380 #define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
 381 #define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
 382
 383 /* PCI0, PCI1 in one BAT */
 384 #define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
 385 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
 386 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
 387 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 388
 389 /* GT regs, bootrom, all the devices, PCI I/O */
 390 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
 391 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
 392 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
 393 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
 394
 395 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 396 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 397 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 398 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
 399
 400 /* set rest out of range for Linux !!!!!!!!!!! */
 401
 402 /* IBAT5 and DBAT5 */
 403 #define CONFIG_SYS_IBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
 404 #define CONFIG_SYS_IBAT5U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 405 #define CONFIG_SYS_DBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 406 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
 407
 408 /* IBAT6 and DBAT6 */
 409 #define CONFIG_SYS_IBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
 410 #define CONFIG_SYS_IBAT6U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 411 #define CONFIG_SYS_DBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 412 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
 413
 414 /* IBAT7 and DBAT7 */
 415 #define CONFIG_SYS_IBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
 416 #define CONFIG_SYS_IBAT7U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 417 #define CONFIG_SYS_DBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 418 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
 419
 420 /*
 421  * For booting Linux, the board info and command line data
 422  * have to be in the first 8 MB of memory, since this is
 423  * the maximum mapped by the Linux kernel during initialization.
 424  */
 425 #define CONFIG_SYS_BOOTMAPSZ            (8<<20) /* Initial Memory map for Linux */
 426 #define CONFIG_SYS_VXWORKS_MAC_PTR      0x42010000 /* use some memory in SRAM that's not used!!! */
 427
 428 /*-----------------------------------------------------------------------
 429  * Cache Configuration
 430  */
 431 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For all MPC74xx CPUs          */
 432 #if defined(CONFIG_CMD_KGDB)
 433 #define CONFIG_SYS_CACHELINE_SHIFT      5       /* log base 2 of the above value */
 434 #endif
 435
 436 /*-----------------------------------------------------------------------
 437  * L2CR setup -- make sure this is right for your board!
 438  * look in include/mpc74xx.h for the defines used here
 439  */
 440 #define CONFIG_SYS_L2
 441
 442 #if defined (CONFIG_750CX) || defined (CONFIG_750FX)
 443 #define L2_INIT 0
 444 #else
 445 #define L2_INIT         (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
 446                         L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
 447 #endif
 448
 449 #define L2_ENABLE       (L2_INIT | L2CR_L2E)
 450
 451 #endif  /* __CONFIG_H */