]>
git.ipfire.org Git - people/ms/u-boot.git/blob - include/configs/rsdproto.h
3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
9 * Configuation settings for the R&S Protocol Board board.
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 * High Level Configuration Options
38 #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
39 #define CONFIG_RSD_PROTO 1 /* on a R&S Protocol Board */
40 #define CONFIG_CPM2 1 /* Has a CPM2 */
42 #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
45 * select serial console configuration
47 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
48 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
51 * if CONFIG_CONS_NONE is defined, then the serial console routines must
54 #undef CONFIG_CONS_ON_SMC /* define if console on SMC */
55 #define CONFIG_CONS_ON_SCC /* define if console on SCC */
56 #undef CONFIG_CONS_NONE /* define if console on neither */
57 #define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
60 * select ethernet configuration
62 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
63 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
66 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
67 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
69 #undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
70 #define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
71 #undef CONFIG_ETHER_NONE /* define if ethernet on neither */
72 #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
74 #if (CONFIG_ETHER_INDEX == 2)
79 * - Select bus for bd/buffers (see 28-13)
80 * - Enable Full Duplex in FSMR
82 # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
83 # define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
84 # define CONFIG_SYS_CPMFCR_RAMTYPE (0)
85 # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
87 #endif /* CONFIG_ETHER_INDEX */
90 /* allow to overwrite serial and ethaddr */
91 #define CONFIG_ENV_OVERWRITE
94 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
95 #define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */
96 #define CONFIG_SYS_I2C_SLAVE 0x30
99 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
100 #define CONFIG_8260_CLKIN 50000000 /* in Hz */
102 #define CONFIG_BAUDRATE 115200
108 #define CONFIG_BOOTP_BOOTFILESIZE
109 #define CONFIG_BOOTP_BOOTPATH
110 #define CONFIG_BOOTP_GATEWAY
111 #define CONFIG_BOOTP_HOSTNAME
115 * Command line configuration.
117 #include <config_cmd_default.h>
119 #undef CONFIG_CMD_KGDB
122 /* Define this if you want to boot from 0x00000100. If you don't define
123 * this, you will need to program the bootloader to 0xfff00000, and
124 * get the hardware reset config words at 0xfe000000. The simplest
125 * way to do that is to program the bootloader at both addresses.
126 * It is suggested that you just let U-Boot live at 0x00000000.
128 #define CONFIG_SYS_RSD_BOOT_LOW 1
130 #define CONFIG_BOOTDELAY 5
131 #define CONFIG_BOOTARGS "devfs=mount root=ramfs"
132 #define CONFIG_ETHADDR 08:00:3e:26:0a:5a
133 #define CONFIG_NETMASK 255.255.0.0
135 #if defined(CONFIG_CMD_KGDB)
136 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
137 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
141 * Miscellaneous configurable options
143 #define CONFIG_SYS_LONGHELP /* undef to save memory */
144 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
145 #if defined(CONFIG_CMD_KGDB)
146 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
148 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
150 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
151 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
152 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
154 #define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
155 #define CONFIG_SYS_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */
157 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
159 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
161 /* valid baudrates */
162 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
165 * Low Level Configuration Settings
166 * (address mappings, register initial values, etc.)
167 * You should know what you are doing if you make changes here.
170 /*-----------------------------------------------------------------------
171 * Physical Memory Map
173 #define PHYS_SDRAM_60X 0x00000000 /* SDRAM (60x Bus) */
174 #define PHYS_SDRAM_60X_SIZE 0x08000000 /* 128 MB */
176 #define PHYS_SDRAM_LOCAL 0x40000000 /* SDRAM (Local Bus) */
177 #define PHYS_SDRAM_LOCAL_SIZE 0x04000000 /* 64 MB */
179 #define PHYS_DPRAM_PCI 0xE8000000 /* DPRAM PPC/PCI */
180 #define PHYS_DPRAM_PCI_SIZE 0x00020000 /* 128 KB */
182 /*#define PHYS_DPRAM_PCI_SEM 0x04020000 / * DPRAM PPC/PCI Semaphore */
183 /*#define PHYS_DPRAM_PCI_SEM_SIZE 0x00000001 / * 1 Byte */
185 #define PHYS_DPRAM_SHARC 0xE8100000 /* DPRAM PPC/Sharc */
186 #define PHYS_DPRAM_SHARC_SIZE 0x00040000 /* 256 KB */
188 /*#define PHYS_DPRAM_SHARC_SEM 0x04140000 / * DPRAM PPC/Sharc Semaphore */
189 /*#define PHYS_DPRAM_SHARC_SEM_SIZE 0x00000001 / * 1 Byte */
191 #define PHYS_VIRTEX_REGISTER 0xE8300000 /* FPGA implemented register */
192 #define PHYS_VIRTEX_REGISTER_SIZE 0x00000100
194 #define PHYS_USB 0x04200000 /* USB Controller (60x Bus) */
195 #define PHYS_USB_SIZE 0x00000002 /* 2 Bytes */
197 #define PHYS_IMMR 0xF0000000 /* Internal Memory Mapped Reg. */
199 #define PHYS_FLASH 0xFF000000 /* Flash (60x Bus) */
200 #define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
202 #define CONFIG_SYS_IMMR PHYS_IMMR
204 /*-----------------------------------------------------------------------
207 * In order to reset the CPU, U-Boot jumps to a special address which
208 * causes a machine check exception. The default address for this is
209 * CONFIG_SYS_MONITOR_BASE - sizeof (ulong), which might not always work, eg. when
210 * testing the monitor in RAM using a JTAG debugger.
212 * Just set CONFIG_SYS_RESET_ADDRESS to an address that you know is sure to
213 * cause a bus error on your hardware.
215 #define CONFIG_SYS_RESET_ADDRESS 0x20000000
217 /*-----------------------------------------------------------------------
218 * Hard Reset Configuration Words
221 #if defined(CONFIG_SYS_RSD_BOOT_LOW)
222 # define CONFIG_SYS_RSD_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
224 # define CONFIG_SYS_RSD_HRCW_BOOT_FLAGS (0)
225 #endif /* defined(CONFIG_SYS_RSD_BOOT_LOW) */
227 /* get the HRCW ISB field from CONFIG_SYS_IMMR */
228 #define CONFIG_SYS_RSD_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) |\
229 ((CONFIG_SYS_IMMR & 0x01000000) >> 7) |\
230 ((CONFIG_SYS_IMMR & 0x00100000) >> 4) )
232 #define CONFIG_SYS_HRCW_MASTER (HRCW_L2CPC10 | \
234 CONFIG_SYS_RSD_HRCW_IMMR |\
239 CONFIG_SYS_RSD_HRCW_BOOT_FLAGS)
242 #define CONFIG_SYS_HRCW_SLAVE1 0
243 #define CONFIG_SYS_HRCW_SLAVE2 0
244 #define CONFIG_SYS_HRCW_SLAVE3 0
245 #define CONFIG_SYS_HRCW_SLAVE4 0
246 #define CONFIG_SYS_HRCW_SLAVE5 0
247 #define CONFIG_SYS_HRCW_SLAVE6 0
248 #define CONFIG_SYS_HRCW_SLAVE7 0
250 /*-----------------------------------------------------------------------
251 * Definitions for initial stack pointer and data area (in DPRAM)
253 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
254 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
255 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
256 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
257 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
259 /*-----------------------------------------------------------------------
260 * Start addresses for the final memory configuration
261 * (Set up by the startup code)
262 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
263 * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependend.
265 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_60X
266 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH
267 /*#define CONFIG_SYS_MONITOR_BASE 0x200000 */
268 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
269 #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE
270 #define CONFIG_SYS_RAMBOOT
272 #define CONFIG_SYS_MONITOR_LEN (160 << 10) /* Reserve 160 kB for Monitor */
273 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
276 * For booting Linux, the board info and command line data
277 * have to be in the first 8 MB of memory, since this is
278 * the maximum mapped by the Linux kernel during initialization.
280 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
282 /*-----------------------------------------------------------------------
283 * FLASH and environment organization
285 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
286 #define CONFIG_SYS_MAX_FLASH_SECT 63 /* max number of sectors on one chip */
288 #define CONFIG_SYS_FLASH_ERASE_TOUT 12000 /* Timeout for Flash Erase (in ms) */
289 #define CONFIG_SYS_FLASH_WRITE_TOUT 3000 /* Timeout for Flash Write (in ms) */
291 /* turn off NVRAM env feature */
292 #undef CONFIG_NVRAM_ENV
294 #define CONFIG_ENV_IS_IN_FLASH 1
295 #define CONFIG_ENV_ADDR (PHYS_FLASH + 0x28000) /* Addr of Environment Sector */
296 #define CONFIG_ENV_SECT_SIZE 0x8000 /* Total Size of Environment Sector */
298 /*-----------------------------------------------------------------------
299 * Cache Configuration
301 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
302 #if defined(CONFIG_CMD_KGDB)
303 #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
306 /*-----------------------------------------------------------------------
307 * HIDx - Hardware Implementation-dependent Registers 2-11
308 *-----------------------------------------------------------------------
309 * HID0 also contains cache control - initially enable both caches and
310 * invalidate contents, then the final state leaves only the instruction
311 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
312 * but Soft reset does not.
314 * HID1 has only read-only information - nothing to set.
316 #define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|HID0_IFEM|HID0_ABE)
317 #define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE|HID0_EMCP)
318 #define CONFIG_SYS_HID2 0
320 /*-----------------------------------------------------------------------
321 * RMR - Reset Mode Register
322 *-----------------------------------------------------------------------
324 #define CONFIG_SYS_RMR 0
326 /*-----------------------------------------------------------------------
327 * BCR - Bus Configuration 4-25
328 *-----------------------------------------------------------------------
330 #define CONFIG_SYS_BCR 0x100c0000
332 /*-----------------------------------------------------------------------
333 * SIUMCR - SIU Module Configuration 4-31
334 *-----------------------------------------------------------------------
337 #define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11 | SIUMCR_L2CPC10 | SIUMCR_APPC10 | \
338 SIUMCR_CS10PC01 | SIUMCR_BCTLC01)
340 /*-----------------------------------------------------------------------
341 * SYPCR - System Protection Control 11-9
342 * SYPCR can only be written once after reset!
343 *-----------------------------------------------------------------------
344 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
346 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_PBME | SYPCR_LBME | \
347 SYPCR_SWRI | SYPCR_SWP)
349 /*-----------------------------------------------------------------------
350 * TMCNTSC - Time Counter Status and Control 4-40
351 *-----------------------------------------------------------------------
352 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
353 * and enable Time Counter
355 #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC | TMCNTSC_ALR | TMCNTSC_TCF | TMCNTSC_TCE)
357 /*-----------------------------------------------------------------------
358 * PISCR - Periodic Interrupt Status and Control 4-42
359 *-----------------------------------------------------------------------
360 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
363 #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
365 /*-----------------------------------------------------------------------
366 * SCCR - System Clock Control 9-8
367 *-----------------------------------------------------------------------
369 #define CONFIG_SYS_SCCR 0x00000000
371 /*-----------------------------------------------------------------------
372 * RCCR - RISC Controller Configuration 13-7
373 *-----------------------------------------------------------------------
375 #define CONFIG_SYS_RCCR 0
378 * Init Memory Controller:
381 #define CONFIG_SYS_PSDMR 0x494D2452
382 #define CONFIG_SYS_LSDMR 0x49492552
385 #define CONFIG_SYS_BR0_PRELIM (PHYS_FLASH | BRx_V)
386 #define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(PHYS_FLASH_SIZE) | \
390 /* DPRAM to the PCI BUS on the protocol board */
391 #define CONFIG_SYS_BR1_PRELIM (PHYS_DPRAM_PCI | BRx_V)
392 #define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(PHYS_DPRAM_PCI_SIZE) | \
396 #define CONFIG_SYS_BR2_PRELIM (PHYS_SDRAM_60X | BRx_MS_SDRAM_P | BRx_V)
397 #define CONFIG_SYS_OR2_PRELIM (ORxS_SIZE_TO_AM(PHYS_SDRAM_60X_SIZE) | \
399 ORxS_ROWST_PBI1_A2 | \
403 /* Virtex-FPGA - Register */
404 #define CONFIG_SYS_BR3_PRELIM (PHYS_VIRTEX_REGISTER | BRx_V)
405 #define CONFIG_SYS_OR3_PRELIM (ORxS_SIZE_TO_AM(PHYS_VIRTEX_REGISTER_SIZE) | \
410 /* local bus SDRAM */
411 #define CONFIG_SYS_BR4_PRELIM (PHYS_SDRAM_LOCAL | BRx_PS_32 | BRx_MS_SDRAM_L | BRx_V)
412 #define CONFIG_SYS_OR4_PRELIM (ORxS_SIZE_TO_AM(PHYS_SDRAM_LOCAL_SIZE) | \
414 ORxS_ROWST_PBI1_A4 | \
417 /* DPRAM to the Sharc-Bus on the protocol board */
418 #define CONFIG_SYS_BR5_PRELIM (PHYS_DPRAM_SHARC | BRx_V)
419 #define CONFIG_SYS_OR5_PRELIM (P2SZ_TO_AM(PHYS_DPRAM_SHARC_SIZE) | \
423 * Internal Definitions
427 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
428 #define BOOTFLAG_WARM 0x02 /* Software reboot */
430 #endif /* __CONFIG_H */