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1 /*
2 * Configuration file for the SAMA5D2 PTC EK Board.
3 *
4 * Copyright (C) 2017 Microchip Technology Inc.
5 * Wenyou Yang <wenyou.yang@microchip.com>
6 * Ludovic Desroches <ludovic.desroches@microchip.com>
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13
14 #include "at91-sama5_common.h"
15
16 #undef CONFIG_SYS_AT91_MAIN_CLOCK
17 #define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */
18
19 #define CONFIG_MISC_INIT_R
20
21 /* SDRAM */
22 #define CONFIG_NR_DRAM_BANKS 1
23 #define CONFIG_SYS_SDRAM_BASE 0x20000000
24 #define CONFIG_SYS_SDRAM_SIZE 0x20000000
25
26 #define CONFIG_SYS_INIT_SP_ADDR \
27 (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
28
29 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
30
31 /* NAND Flash */
32 #ifdef CONFIG_CMD_NAND
33 #define CONFIG_NAND_ATMEL
34 #define CONFIG_SYS_MAX_NAND_DEVICE 1
35 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
36 /* our ALE is AD21 */
37 #define CONFIG_SYS_NAND_MASK_ALE BIT(21)
38 /* our CLE is AD22 */
39 #define CONFIG_SYS_NAND_MASK_CLE BIT(22)
40 #define CONFIG_SYS_NAND_ONFI_DETECTION
41 /* PMECC & PMERRLOC */
42 #define CONFIG_ATMEL_NAND_HWECC
43 #define CONFIG_ATMEL_NAND_HW_PMECC
44 #endif
45
46 #endif /* __CONFIG_H */