include/configs/sh7785lcr.h

   1 /*
   2  * Configuation settings for the Renesas Technology R0P7785LC0011RL board
   3  *
   4  * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __SH7785LCR_H
  10 #define __SH7785LCR_H
  11
  12 #define CONFIG_CPU_SH7785       1
  13 #define CONFIG_SH7785LCR        1
  14
  15 #define CONFIG_CMD_SDRAM
  16 #define CONFIG_CMD_SH_ZIMAGEBOOT
  17
  18 #define CONFIG_BOOTARGS         "console=ttySC1,115200 root=/dev/nfs ip=dhcp"
  19
  20 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  21         "bootdevice=0:1\0"                                              \
  22         "usbload=usb reset;usbboot;usb stop;bootm\0"
  23
  24 #define CONFIG_DISPLAY_BOARDINFO
  25 #undef  CONFIG_SHOW_BOOT_PROGRESS
  26
  27 /* MEMORY */
  28 #if defined(CONFIG_SH_32BIT)
  29 #define CONFIG_SYS_TEXT_BASE            0x8FF80000
  30 /* 0x40000000 - 0x47FFFFFF does not use */
  31 #define CONFIG_SH_SDRAM_OFFSET          (0x8000000)
  32 #define SH7785LCR_SDRAM_PHYS_BASE       (0x40000000 + CONFIG_SH_SDRAM_OFFSET)
  33 #define SH7785LCR_SDRAM_BASE            (0x80000000 + CONFIG_SH_SDRAM_OFFSET)
  34 #define SH7785LCR_SDRAM_SIZE            (384 * 1024 * 1024)
  35 #define SH7785LCR_FLASH_BASE_1          (0xa0000000)
  36 #define SH7785LCR_FLASH_BANK_SIZE       (64 * 1024 * 1024)
  37 #define SH7785LCR_USB_BASE              (0xa6000000)
  38 #else
  39 #define CONFIG_SYS_TEXT_BASE            0x0FF80000
  40 #define SH7785LCR_SDRAM_BASE            (0x08000000)
  41 #define SH7785LCR_SDRAM_SIZE            (128 * 1024 * 1024)
  42 #define SH7785LCR_FLASH_BASE_1          (0xa0000000)
  43 #define SH7785LCR_FLASH_BANK_SIZE       (64 * 1024 * 1024)
  44 #define SH7785LCR_USB_BASE              (0xb4000000)
  45 #endif
  46
  47 #define CONFIG_SYS_LONGHELP
  48 #define CONFIG_SYS_CBSIZE               256
  49 #define CONFIG_SYS_PBSIZE               256
  50 #define CONFIG_SYS_MAXARGS              16
  51 #define CONFIG_SYS_BARGSIZE             512
  52 #define CONFIG_SYS_BAUDRATE_TABLE       { 115200 }
  53
  54 /* SCIF */
  55 #define CONFIG_CONS_SCIF1       1
  56 #define CONFIG_SCIF_EXT_CLOCK   1
  57
  58 #define CONFIG_SYS_MEMTEST_START        (SH7785LCR_SDRAM_BASE)
  59 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START + \
  60                                         (SH7785LCR_SDRAM_SIZE) - \
  61                                          4 * 1024 * 1024)
  62 #undef  CONFIG_SYS_ALT_MEMTEST
  63 #undef  CONFIG_SYS_MEMTEST_SCRATCH
  64 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE
  65
  66 #define CONFIG_SYS_SDRAM_BASE   (SH7785LCR_SDRAM_BASE)
  67 #define CONFIG_SYS_SDRAM_SIZE   (SH7785LCR_SDRAM_SIZE)
  68 #define CONFIG_SYS_LOAD_ADDR    (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
  69
  70 #define CONFIG_SYS_MONITOR_BASE (SH7785LCR_FLASH_BASE_1)
  71 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
  72 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024)
  73 #define CONFIG_SYS_BOOTMAPSZ            (8 * 1024 * 1024)
  74
  75 /* FLASH */
  76 #define CONFIG_FLASH_CFI_DRIVER
  77 #define CONFIG_SYS_FLASH_CFI
  78 #undef  CONFIG_SYS_FLASH_QUIET_TEST
  79 #define CONFIG_SYS_FLASH_EMPTY_INFO
  80 #define CONFIG_SYS_FLASH_BASE           (SH7785LCR_FLASH_BASE_1)
  81 #define CONFIG_SYS_MAX_FLASH_SECT       512
  82
  83 #define CONFIG_SYS_MAX_FLASH_BANKS      1
  84 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE + \
  85                                  (0 * SH7785LCR_FLASH_BANK_SIZE) }
  86
  87 #define CONFIG_SYS_FLASH_ERASE_TOUT     (3 * 1000)
  88 #define CONFIG_SYS_FLASH_WRITE_TOUT     (3 * 1000)
  89 #define CONFIG_SYS_FLASH_LOCK_TOUT      (3 * 1000)
  90 #define CONFIG_SYS_FLASH_UNLOCK_TOUT    (3 * 1000)
  91
  92 #undef  CONFIG_SYS_FLASH_PROTECTION
  93 #undef  CONFIG_SYS_DIRECT_FLASH_TFTP
  94
  95 /* R8A66597 */
  96 #define CONFIG_USB_R8A66597_HCD
  97 #define CONFIG_R8A66597_BASE_ADDR       SH7785LCR_USB_BASE
  98 #define CONFIG_R8A66597_XTAL            0x0000  /* 12MHz */
  99 #define CONFIG_R8A66597_LDRV            0x8000  /* 3.3V */
 100 #define CONFIG_R8A66597_ENDIAN          0x0000  /* little */
 101
 102 /* PCI Controller */
 103 #define CONFIG_SH4_PCI
 104 #define CONFIG_SH7780_PCI
 105 #if defined(CONFIG_SH_32BIT)
 106 #define CONFIG_SH7780_PCI_LSR   0x1ff00001
 107 #define CONFIG_SH7780_PCI_LAR   0x5f000000
 108 #define CONFIG_SH7780_PCI_BAR   0x5f000000
 109 #else
 110 #define CONFIG_SH7780_PCI_LSR   0x07f00001
 111 #define CONFIG_SH7780_PCI_LAR   CONFIG_SYS_SDRAM_SIZE
 112 #define CONFIG_SH7780_PCI_BAR   CONFIG_SYS_SDRAM_SIZE
 113 #endif
 114 #define CONFIG_PCI_SCAN_SHOW    1
 115
 116 #define CONFIG_PCI_MEM_BUS      0xFD000000      /* Memory space base addr */
 117 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
 118 #define CONFIG_PCI_MEM_SIZE     0x01000000      /* Size of Memory window */
 119
 120 #define CONFIG_PCI_IO_BUS       0xFE200000      /* IO space base address */
 121 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
 122 #define CONFIG_PCI_IO_SIZE      0x00200000      /* Size of IO window */
 123
 124 #if defined(CONFIG_SH_32BIT)
 125 #define CONFIG_PCI_SYS_PHYS     SH7785LCR_SDRAM_PHYS_BASE
 126 #else
 127 #define CONFIG_PCI_SYS_PHYS     CONFIG_SYS_SDRAM_BASE
 128 #endif
 129 #define CONFIG_PCI_SYS_BUS      CONFIG_SYS_SDRAM_BASE
 130 #define CONFIG_PCI_SYS_SIZE     CONFIG_SYS_SDRAM_SIZE
 131
 132 /* ENV setting */
 133 #define CONFIG_ENV_OVERWRITE    1
 134 #define CONFIG_ENV_SECT_SIZE    (256 * 1024)
 135 #define CONFIG_ENV_SIZE         (CONFIG_ENV_SECT_SIZE)
 136 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
 137 #define CONFIG_ENV_OFFSET               (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
 138 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SECT_SIZE)
 139
 140 /* Board Clock */
 141 /* The SCIF used external clock. system clock only used timer. */
 142 #define CONFIG_SYS_CLK_FREQ     50000000
 143 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
 144 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 145 #define CONFIG_SYS_TMU_CLK_DIV          4
 146
 147 #endif  /* __SH7785LCR_H */