include/configs/spc1920.h

   1 /*
   2  * (C) Copyright 2006
   3  * Markus Klotzbuecher, DENX Software Engineering, mk@denx.de
   4  *
   5  * Configuation settings for the SPC1920 board.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #ifndef __H
  24 #define __CONFIG_H
  25
  26 #define CONFIG_SPC1920                  1       /* SPC1920 board */
  27 #define CONFIG_MPC885                   1       /* MPC885 CPU */
  28
  29 #define CONFIG_8xx_CONS_SMC1            /* Console is on SMC1 */
  30 #undef  CONFIG_8xx_CONS_SMC2
  31 #undef  CONFIG_8xx_CONS_NONE
  32
  33 #define CONFIG_MII
  34 #define CONFIG_MII_INIT         1
  35 #undef CONFIG_ETHER_ON_FEC1
  36 #define CONFIG_ETHER_ON_FEC2
  37 #define FEC_ENET
  38 #define CONFIG_FEC2_PHY         1
  39
  40 #define CONFIG_BAUDRATE         19200
  41
  42 /* use PLD CLK4 instead of brg */
  43 #define CFG_SPC1920_SMC1_CLK4
  44
  45 #define CONFIG_8xx_OSCLK                10000000 /* 10 MHz oscillator on EXTCLK  */
  46 #define CONFIG_8xx_CPUCLK_DEFAULT       50000000
  47 #define CFG_8xx_CPUCLK_MIN              40000000
  48 #define CFG_8xx_CPUCLK_MAX              133000000
  49
  50 #define CFG_RESET_ADDRESS               0xC0000000
  51
  52 #define CONFIG_BOARD_EARLY_INIT_F
  53 #define CONFIG_LAST_STAGE_INIT
  54
  55 #if 0
  56 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  57 #else
  58 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  59 #endif
  60
  61 #define CONFIG_ENV_OVERWRITE
  62
  63 #define CONFIG_NFSBOOTCOMMAND                                                   \
  64     "dhcp;"                                                                     \
  65     "setenv bootargs root=/dev/nfs rw nfsroot=$rootpath "                       \
  66     "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;"              \
  67     "bootm"
  68
  69 #define CONFIG_BOOTCOMMAND                                                      \
  70     "setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\
  71     "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;"              \
  72     "bootm fe080000"
  73
  74 #undef CONFIG_BOOTARGS
  75
  76 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  77 #define CONFIG_BZIP2     /* include support for bzip2 compressed images */
  78
  79
  80 /*
  81  * BOOTP options
  82  */
  83 #define CONFIG_BOOTP_BOOTFILESIZE
  84 #define CONFIG_BOOTP_BOOTPATH
  85 #define CONFIG_BOOTP_GATEWAY
  86 #define CONFIG_BOOTP_HOSTNAME
  87
  88
  89 /*
  90  * Command line configuration.
  91  */
  92 #include <config_cmd_default.h>
  93
  94 #define CONFIG_CMD_ASKENV
  95 #define CONFIG_CMD_DATE
  96 #define CONFIG_CMD_ECHO
  97 #define CONFIG_CMD_IMMAP
  98 #define CONFIG_CMD_JFFS2
  99 #define CONFIG_CMD_NET
 100 #define CONFIG_CMD_PING
 101 #define CONFIG_CMD_DHCP
 102 #define CONFIG_CMD_I2C
 103 #define CONFIG_CMD_MII
 104
 105 /*
 106  * Miscellaneous configurable options
 107  */
 108 #define CFG_LONGHELP                            /* undef to save memory         */
 109 #define CFG_PROMPT              "=>"            /* Monitor Command Prompt       */
 110 #define CFG_HUSH_PARSER
 111 #define CFG_PROMPT_HUSH_PS2     "> "
 112
 113 #if defined(CONFIG_CMD_KGDB)
 114 #define CFG_CBSIZE              1024            /* Console I/O Buffer Size      */
 115 #else
 116 #define CFG_CBSIZE              256             /* Console I/O Buffer Size      */
 117 #endif
 118
 119 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size  */
 120 #define CFG_MAXARGS             16              /* max number of command args   */
 121 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 122
 123 #define CFG_LOAD_ADDR           0x00100000
 124
 125 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 126
 127 #define CFG_BAUDRATE_TABLE      { 2400, 4800, 9600, 19200 }
 128
 129 /*
 130  * Low Level Configuration Settings
 131  * (address mappings, register initial values, etc.)
 132  * You should know what you are doing if you make changes here.
 133  */
 134
 135 /*-----------------------------------------------------------------------
 136  * Internal Memory Mapped Register
 137  */
 138 #define CFG_IMMR                0xF0000000
 139
 140 /*-----------------------------------------------------------------------
 141  * Definitions for initial stack pointer and data area (in DPRAM)
 142  */
 143 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 144 #define CFG_INIT_RAM_END        0x2F00  /* End of used area in DPRAM    */
 145 #define CFG_GBL_DATA_SIZE       64  /* size in bytes reserved for initial data */
 146 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 147 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 148
 149 /*-----------------------------------------------------------------------
 150  * Start addresses for the final memory configuration
 151  * (Set up by the startup code)
 152  * Please note that CFG_SDRAM_BASE _must_ start at 0
 153  */
 154 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 155 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 156
 157 /*
 158  * For booting Linux, the board info and command line data
 159  * have to be in the first 8 MB of memory, since this is
 160  * the maximum mapped by the Linux kernel during initialization.
 161  */
 162 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 163
 164 #define CFG_MONITOR_BASE        TEXT_BASE
 165 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 KB for monitor   */
 166
 167 #ifdef CONFIG_BZIP2
 168 #define CFG_MALLOC_LEN          (2500 << 10)    /* Reserve ~2.5 MB for malloc() */
 169 #else
 170 #define CFG_MALLOC_LEN          (384 << 10)     /* Reserve 384 kB for malloc()  */
 171 #endif /* CONFIG_BZIP2 */
 172
 173 #define CFG_ALLOC_DPRAM         1       /* use allocation routines      */
 174
 175 /*
 176  * Flash
 177  */
 178 /*-----------------------------------------------------------------------
 179  * Flash organisation
 180  */
 181 #define CFG_FLASH_BASE          0xFE000000
 182 #define CFG_FLASH_CFI                           /* The flash is CFI compatible  */
 183 #define CONFIG_FLASH_CFI_DRIVER                    /* Use common CFI driver        */
 184 #define CFG_MAX_FLASH_BANKS     1               /* Max number of flash banks    */
 185 #define CFG_MAX_FLASH_SECT      128             /* Max num of sects on one chip */
 186
 187 /* Environment is in flash */
 188 #define CONFIG_ENV_IS_IN_FLASH
 189 #define CONFIG_ENV_SECT_SIZE       0x40000         /* We use one complete sector   */
 190 #define CONFIG_ENV_ADDR         (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
 191
 192 #define CONFIG_ENV_OVERWRITE
 193
 194 /*-----------------------------------------------------------------------
 195  * Cache Configuration
 196  */
 197 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
 198 #define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
 199
 200 #ifdef CONFIG_CMD_DATE
 201 # define CONFIG_RTC_DS3231
 202 # define CFG_I2C_RTC_ADDR      0x68
 203 #endif
 204
 205 /*-----------------------------------------------------------------------
 206  * I2C configuration
 207  */
 208 #if defined(CONFIG_CMD_I2C)
 209 /* enable I2C and select the hardware/software driver */
 210 #undef CONFIG_HARD_I2C                 /* I2C with hardware support    */
 211 #define CONFIG_SOFT_I2C                1       /* I2C bit-banged               */
 212
 213 #define CFG_I2C_SPEED          93000   /* 93 kHz is supposed to work   */
 214 #define CFG_I2C_SLAVE          0xFE
 215
 216 #ifdef CONFIG_SOFT_I2C
 217 /*
 218  * Software (bit-bang) I2C driver configuration
 219  */
 220 #define PB_SCL         0x00000020      /* PB 26 */
 221 #define PB_SDA         0x00000010      /* PB 27 */
 222
 223 #define I2C_INIT       (immr->im_cpm.cp_pbdir |=  PB_SCL)
 224 #define I2C_ACTIVE     (immr->im_cpm.cp_pbdir |=  PB_SDA)
 225 #define I2C_TRISTATE   (immr->im_cpm.cp_pbdir &= ~PB_SDA)
 226 #define I2C_READ       ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 227 #define I2C_SDA(bit)   if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
 228                        else    immr->im_cpm.cp_pbdat &= ~PB_SDA
 229 #define I2C_SCL(bit)   if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
 230                        else    immr->im_cpm.cp_pbdat &= ~PB_SCL
 231 #define I2C_DELAY      udelay(2)       /* 1/4 I2C clock duration */
 232 #endif /* CONFIG_SOFT_I2C */
 233 #endif
 234
 235 /*-----------------------------------------------------------------------
 236  * SYPCR - System Protection Control                            11-9
 237  * SYPCR can only be written once after reset!
 238  *-----------------------------------------------------------------------
 239  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 240  */
 241 #if defined(CONFIG_WATCHDOG)
 242 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 243                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 244 #else
 245 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 246 #endif
 247
 248 /*-----------------------------------------------------------------------
 249  * SIUMCR - SIU Module Configuration                            11-6
 250  *-----------------------------------------------------------------------
 251  * PCMCIA config., multi-function pin tri-state
 252  */
 253 #define CFG_SIUMCR      (SIUMCR_FRC)
 254
 255 /*-----------------------------------------------------------------------
 256  * TBSCR - Time Base Status and Control                         11-26
 257  *-----------------------------------------------------------------------
 258  * Clear Reference Interrupt Status, Timebase freezing enabled
 259  */
 260 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
 261
 262 /*-----------------------------------------------------------------------
 263  * PISCR - Periodic Interrupt Status and Control                11-31
 264  *-----------------------------------------------------------------------
 265  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 266  */
 267 #define CFG_PISCR       (PISCR_PS | PISCR_PITF)
 268
 269 /*-----------------------------------------------------------------------
 270  * SCCR - System Clock and reset Control Register               15-27
 271  *-----------------------------------------------------------------------
 272  * Set clock output, timebase and RTC source and divider,
 273  * power management and some other internal clocks
 274  */
 275 #define SCCR_MASK       SCCR_EBDF11
 276 /* #define CFG_SCCR     SCCR_TBS */
 277 #define CFG_SCCR        (SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 278                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 279                          SCCR_DFALCD00)
 280
 281 /*-----------------------------------------------------------------------
 282  * DER - Debug Enable Register
 283  *-----------------------------------------------------------------------
 284  * Set to zero to prevent the processor from entering debug mode
 285  */
 286 #define CFG_DER          0
 287
 288
 289 /* Because of the way the 860 starts up and assigns CS0 the entire
 290  * address space, we have to set the memory controller differently.
 291  * Normally, you write the option register first, and then enable the
 292  * chip select by writing the base register.  For CS0, you must write
 293  * the base register first, followed by the option register.
 294  */
 295
 296
 297 /*
 298  * Init Memory Controller:
 299  */
 300
 301 /* BR0 and OR0 (FLASH) */
 302 #define FLASH_BASE0_PRELIM      CFG_FLASH_BASE  /* FLASH bank #0 */
 303
 304
 305 /* used to re-map FLASH both when starting from SRAM or FLASH:
 306  * restrict access enough to keep SRAM working (if any)
 307  * but not too much to meddle with FLASH accesses
 308  */
 309 #define CFG_REMAP_OR_AM         0x80000000      /* OR addr mask */
 310 #define CFG_PRELIM_OR_AM        0xE0000000      /* OR addr mask */
 311
 312 /*
 313  * FLASH timing:
 314  */
 315 #define CFG_OR_TIMING_FLASH     (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 316                                  OR_SCY_6_CLK | OR_EHTR | OR_BI)
 317
 318 #define CFG_OR0_REMAP   (CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 319 #define CFG_OR0_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
 320 #define CFG_BR0_PRELIM  ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 321
 322
 323 /*
 324  * SDRAM CS1 UPMB
 325  */
 326 #define CFG_SDRAM_BASE  0x00000000
 327 #define CFG_SDRAM_BASE_PRELIM CFG_SDRAM_BASE
 328 #define SDRAM_MAX_SIZE  0x4000000 /* max 64 MB */
 329
 330 #define CFG_PRELIM_OR1_AM       0xF0000000
 331 /* #define CFG_OR1_TIMING  OR_CSNT_SAM/\*  | OR_G5LS /\\* *\\/ *\/ */
 332 #define SDRAM_TIMING    OR_SCY_0_CLK    /* SDRAM-Timing */
 333
 334 #define CFG_OR1_PRELIM  (CFG_PRELIM_OR1_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING)
 335 #define CFG_BR1_PRELIM  ((CFG_SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V)
 336
 337 /* #define CFG_OR1_FINAL   ((CFG_OR1_AM & OR_AM_MSK) | CFG_OR1_TIMING) */
 338 /* #define CFG_BR1_FINAL   ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) */
 339
 340 #define CFG_PTB_PER_CLK ((4096 * 16 * 1000) / (4 * 64))
 341 #define CFG_PTA_PER_CLK 195
 342 #define CFG_MBMR_PTB    195
 343 #define CFG_MPTPR       MPTPR_PTP_DIV16
 344 #define CFG_MAR         0x88
 345
 346 #define CFG_MBMR_8COL  ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \
 347                         MBMR_AMB_TYPE_0 | \
 348                         MBMR_G0CLB_A10 | \
 349                         MBMR_DSB_1_CYCL | \
 350                         MBMR_RLFB_1X | \
 351                         MBMR_WLFB_1X | \
 352                         MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */
 353
 354 #define CFG_MBMR_9COL  ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \
 355                         MBMR_AMB_TYPE_1 | \
 356                         MBMR_G0CLB_A10 | \
 357                         MBMR_DSB_1_CYCL | \
 358                         MBMR_RLFB_1X | \
 359                         MBMR_WLFB_1X | \
 360                         MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */
 361
 362
 363 /*
 364  * DSP Host Port Interface CS3
 365  */
 366 #define CFG_SPC1920_HPI_BASE   0x90000000
 367 #define CFG_PRELIM_OR3_AM      0xF8000000
 368
 369 #define CFG_OR3         (CFG_PRELIM_OR3_AM | \
 370                                        OR_G5LS | \
 371                                        OR_SCY_0_CLK | \
 372                                        OR_BI)
 373
 374 #define CFG_BR3 ((CFG_SPC1920_HPI_BASE & BR_BA_MSK) | \
 375                                                BR_MS_UPMA | \
 376                                                BR_PS_16 | \
 377                                                BR_V);
 378
 379 #define CFG_MAMR (MAMR_GPL_A4DIS | \
 380                 MAMR_RLFA_5X | \
 381                 MAMR_WLFA_5X)
 382
 383 #define CONFIG_SPC1920_HPI_TEST
 384
 385 #ifdef CONFIG_SPC1920_HPI_TEST
 386 #define HPI_REG(x)             (*((volatile u16 *) (CFG_SPC1920_HPI_BASE + x)))
 387 #define HPI_HPIC_1             HPI_REG(0)
 388 #define HPI_HPIC_2             HPI_REG(2)
 389 #define HPI_HPIA_1             HPI_REG(0x2000008)
 390 #define HPI_HPIA_2             HPI_REG(0x2000008 + 2)
 391 #define HPI_HPID_INC_1         HPI_REG(0x1000004)
 392 #define HPI_HPID_INC_2         HPI_REG(0x1000004 + 2)
 393 #define HPI_HPID_NOINC_1       HPI_REG(0x300000c)
 394 #define HPI_HPID_NOINC_2       HPI_REG(0x300000c + 2)
 395 #endif /* CONFIG_SPC1920_HPI_TEST */
 396
 397 /*
 398  * Ramtron FM18L08 FRAM 32KB on CS4
 399  */
 400 #define CFG_SPC1920_FRAM_BASE   0x80100000
 401 #define CFG_PRELIM_OR4_AM       0xffff8000
 402 #define CFG_OR4         (CFG_PRELIM_OR4_AM | \
 403                                         OR_ACS_DIV2 | \
 404                                         OR_BI | \
 405                                         OR_SCY_4_CLK | \
 406                                         OR_TRLX)
 407
 408 #define CFG_BR4 ((CFG_SPC1920_FRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
 409
 410 /*
 411  * PLD CS5
 412  */
 413 #define CFG_SPC1920_PLD_BASE    0x80000000
 414 #define CFG_PRELIM_OR5_AM       0xffff8000
 415
 416 #define CFG_OR5_PRELIM          (CFG_PRELIM_OR5_AM | \
 417                                         OR_CSNT_SAM | \
 418                                         OR_ACS_DIV1 | \
 419                                         OR_BI | \
 420                                         OR_SCY_0_CLK | \
 421                                         OR_TRLX)
 422
 423 #define CFG_BR5_PRELIM ((CFG_SPC1920_PLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
 424
 425 /*
 426  * Internal Definitions
 427  *
 428  * Boot Flags
 429  */
 430 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 431 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 432
 433 #endif  /* __CONFIG_H */