include/configs/spieval.h

   1 /*
   2  * (C) Copyright 2003-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2004-2005
   6  * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 /*
  31  * High Level Configuration Options
  32  * (easy to change)
  33  */
  34
  35 #define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU */
  36 #define CONFIG_MPC5200          1       /* (more precisely an MPC5200 CPU) */
  37 #define CONFIG_TQM5200          1       /* ... on TQM5200 module */
  38 #undef CONFIG_TQM5200_REV100            /*  define for revision 100 modules */
  39 #define CONFIG_STK52XX          1       /* ... on a STK52XX base board */
  40 #define CONFIG_STK52XX_REV100   1       /*  define for revision 100 baseboards */
  41
  42 #define CFG_MPC5XXX_CLKIN       33000000 /* ... running at 33.000000MHz */
  43
  44 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH  */
  45 #define BOOTFLAG_WARM           0x02    /* Software reboot           */
  46
  47 /*
  48  * Serial console configuration
  49  */
  50 #define CONFIG_PSC_CONSOLE      6       /* console is on PSC6 */
  51 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps */
  52 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
  53
  54 #ifdef CONFIG_STK52XX
  55 #undef CONFIG_PS2KBD                    /* AT-PS/2 Keyboard             */
  56 #define CONFIG_PS2MULT                  /* .. on PS/2 Multiplexer       */
  57 #define CONFIG_PS2SERIAL        6       /* .. on PSC6                   */
  58 #define CONFIG_PS2MULT_DELAY    (CFG_HZ/2)      /* Initial delay        */
  59 #define CONFIG_BOARD_EARLY_INIT_R
  60 #endif /* CONFIG_STK52XX */
  61
  62 /*
  63  * PCI Mapping:
  64  * 0x40000000 - 0x4fffffff - PCI Memory
  65  * 0x50000000 - 0x50ffffff - PCI IO Space
  66  */
  67 #ifdef CONFIG_STK52XX
  68 #define CONFIG_PCI              1
  69 #define CONFIG_PCI_PNP          1
  70 /* #define CONFIG_PCI_SCAN_SHOW 1 */
  71
  72 #define CONFIG_PCI_MEM_BUS      0x40000000
  73 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  74 #define CONFIG_PCI_MEM_SIZE     0x10000000
  75
  76 #define CONFIG_PCI_IO_BUS       0x50000000
  77 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  78 #define CONFIG_PCI_IO_SIZE      0x01000000
  79
  80 #define CONFIG_NET_MULTI        1
  81 #define CONFIG_EEPRO100         1
  82 #define CFG_RX_ETH_BUFFER       8  /* use 8 rx buffer on eepro100  */
  83 #define CONFIG_NS8382X          1
  84 #endif  /* CONFIG_STK52XX */
  85
  86 /*
  87  * Video console
  88  */
  89 #if 1
  90 #define CONFIG_VIDEO
  91 #define CONFIG_VIDEO_SM501
  92 #define CONFIG_VIDEO_SM501_32BPP
  93 #define CONFIG_CFB_CONSOLE
  94 #define CONFIG_VIDEO_LOGO
  95 #define CONFIG_VGA_AS_SINGLE_DEVICE
  96 #define CONFIG_CONSOLE_EXTRA_INFO
  97 #define CONFIG_VIDEO_SW_CURSOR
  98 #define CONFIG_SPLASH_SCREEN
  99 #define CFG_CONSOLE_IS_IN_ENV
 100 #endif
 101
 102 /* Partitions */
 103 #define CONFIG_MAC_PARTITION
 104 #define CONFIG_DOS_PARTITION
 105 #define CONFIG_ISO_PARTITION
 106
 107 /* USB */
 108 #ifdef CONFIG_STK52XX
 109 #define CONFIG_USB_OHCI
 110 #define CONFIG_USB_STORAGE
 111 #endif
 112
 113 /* POST support */
 114 #define CONFIG_POST             (CFG_POST_MEMORY   | \
 115                                  CFG_POST_CPU      | \
 116                                  CFG_POST_I2C)
 117
 118 #ifdef CONFIG_POST
 119 #define CFG_CMD_POST_DIAG CFG_CMD_DIAG
 120 /* preserve space for the post_word at end of on-chip SRAM */
 121 #define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
 122 #else
 123 #define CFG_CMD_POST_DIAG 0
 124 #endif
 125
 126
 127 /*
 128  * Command line configuration.
 129  */
 130 #include <config_cmd_default.h>
 131
 132 #if defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX)
 133     #define CONFIG_CMD_IDE
 134     #define CONFIG_CMD_FAT
 135     #define CONFIG_CMD_EXT2
 136 #endif
 137
 138 #ifdef CONFIG_STK52XX
 139     #define CONFIG_CMD_USB
 140     #define CONFIG_CMD_FAT
 141 #endif
 142
 143 #ifdef CONFIG_VIDEO
 144     #define CONFIG_CMD_BMP
 145 #endif
 146
 147 #ifdef CONFIG_PCI
 148     #define CONFIG_CMD_PCI
 149 #endif
 150
 151 #define CONFIG_CMD_ASKENV
 152 #define CONFIG_CMD_DATE
 153 #define CONFIG_CMD_DHCP
 154 #define CONFIG_CMD_ECHO
 155 #define CONFIG_CMD_EEPROM
 156 #define CONFIG_CMD_I2C
 157 #define CONFIG_CMD_MII
 158 #define CONFIG_CMD_NFS
 159 #define CONFIG_CMD_PING
 160 #define CONFIG_CMD_POST
 161 #define CONFIG_CMD_REGINFO
 162 #define CONFIG_CMD_SNTP
 163
 164
 165 #define CONFIG_TIMESTAMP                /* display image timestamps */
 166
 167 #if (TEXT_BASE == 0xFC000000)           /* Boot low */
 168 #   define CFG_LOWBOOT          1
 169 #endif
 170
 171 /*
 172  * Autobooting
 173  */
 174 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 175
 176 #define CONFIG_PREBOOT  "echo;" \
 177         "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
 178         "echo"
 179
 180 #undef  CONFIG_BOOTARGS
 181
 182 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 183         "netdev=eth0\0"                                                 \
 184         "rootpath=/opt/eldk/ppc_6xx\0"                                  \
 185         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 186         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 187                 "nfsroot=${serverip}:${rootpath}\0"                     \
 188         "addip=setenv bootargs ${bootargs} "                            \
 189                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 190                 ":${hostname}:${netdev}:off panic=1\0"                  \
 191         "flash_self=run ramargs addip;"                                 \
 192                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 193         "flash_nfs=run nfsargs addip;"                                  \
 194                 "bootm ${kernel_addr}\0"                                \
 195         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
 196         "bootfile=/tftpboot/tqm5200/uImage\0"                           \
 197         "load=tftp 200000 ${u-boot}\0"                                  \
 198         "u-boot=/tftpboot/tqm5200/u-boot.bin\0"                         \
 199         "update=protect off FC000000 FC05FFFF;"                         \
 200                 "erase FC000000 FC05FFFF;"                              \
 201                 "cp.b 200000 FC000000 ${filesize};"                     \
 202                 "protect on FC000000 FC05FFFF\0"                        \
 203         ""
 204
 205 #define CONFIG_BOOTCOMMAND      "run net_nfs"
 206
 207 /*
 208  * IPB Bus clocking configuration.
 209  */
 210 #define CFG_IPBCLK_EQUALS_XLBCLK                /* define for 133MHz speed */
 211
 212 #if defined(CFG_IPBCLK_EQUALS_XLBCLK)
 213 /*
 214  * PCI Bus clocking configuration
 215  *
 216  * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
 217  * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
 218  * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
 219  */
 220 #define CFG_PCICLK_EQUALS_IPBCLK_DIV2   /* define for 66MHz speed */
 221 #endif
 222
 223 /*
 224  * I2C configuration
 225  */
 226 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 227 #ifdef CONFIG_TQM5200_REV100
 228 #define CFG_I2C_MODULE          1       /* Select I2C module #1 for rev. 100 board */
 229 #else
 230 #define CFG_I2C_MODULE          2       /* Select I2C module #2 for all other revs */
 231 #endif
 232
 233 /*
 234  * I2C clock frequency
 235  *
 236  * Please notice, that the resulting clock frequency could differ from the
 237  * configured value. This is because the I2C clock is derived from system
 238  * clock over a frequency divider with only a few divider values. U-boot
 239  * calculates the best approximation for CFG_I2C_SPEED. However the calculated
 240  * approximation allways lies below the configured value, never above.
 241  */
 242 #define CFG_I2C_SPEED           100000 /* 100 kHz */
 243 #define CFG_I2C_SLAVE           0x7F
 244
 245 /*
 246  * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
 247  * also). For other EEPROMs configuration should be verified. On Mini-FAP the
 248  * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
 249  * same configuration could be used.
 250  */
 251 #define CFG_I2C_EEPROM_ADDR             0x50    /* 1010000x */
 252 #define CFG_I2C_EEPROM_ADDR_LEN         2
 253 #define CFG_EEPROM_PAGE_WRITE_BITS      5       /* =32 Bytes per write */
 254 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  20
 255
 256 /*
 257  * HW-Monitor configuration on Mini-FAP
 258  */
 259 #if defined (CONFIG_MINIFAP)
 260 #define CFG_I2C_HWMON_ADDR              0x2C
 261 #endif
 262
 263 /* List of I2C addresses to be verified by POST */
 264 #if defined (CONFIG_MINIFAP)
 265 #undef I2C_ADDR_LIST
 266 #define I2C_ADDR_LIST   {       CFG_I2C_EEPROM_ADDR,    \
 267                                 CFG_I2C_HWMON_ADDR,     \
 268                                 CFG_I2C_SLAVE }
 269 #endif
 270
 271 /*
 272  * Flash configuration
 273  */
 274 #define CFG_FLASH_BASE          TEXT_BASE /* 0xFC000000 */
 275
 276 /* use CFI flash driver if no module variant is spezified */
 277 #define CFG_FLASH_CFI           1       /* Flash is CFI conformant */
 278 #define CFG_FLASH_CFI_DRIVER    1       /* Use the common driver */
 279 #define CFG_FLASH_BANKS_LIST    { CFG_BOOTCS_START }
 280 #define CFG_FLASH_EMPTY_INFO
 281 #define CFG_FLASH_SIZE          0x04000000 /* 64 MByte */
 282 #define CFG_MAX_FLASH_SECT      512     /* max num of sects on one chip */
 283 #undef CFG_FLASH_USE_BUFFER_WRITE       /* not supported yet for AMD */
 284
 285 #if !defined(CFG_LOWBOOT)
 286 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + 0x00760000 + 0x00800000)
 287 #else   /* CFG_LOWBOOT */
 288 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + 0x00060000)
 289 #endif  /* CFG_LOWBOOT */
 290 #define CFG_MAX_FLASH_BANKS     1       /* max num of flash banks
 291                                            (= chip selects) */
 292 #define CFG_FLASH_ERASE_TOUT    240000  /* Flash Erase Timeout (in ms)  */
 293 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (in ms)  */
 294
 295
 296 /*
 297  * Environment settings
 298  */
 299 #define CFG_ENV_IS_IN_FLASH     1
 300 #define CFG_ENV_SIZE            0x10000
 301 #define CFG_ENV_SECT_SIZE       0x20000
 302 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
 303 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 304
 305 /*
 306  * Memory map
 307  */
 308 #define CFG_MBAR                0xF0000000
 309 #define CFG_SDRAM_BASE          0x00000000
 310 #define CFG_DEFAULT_MBAR        0x80000000
 311
 312 /* Use ON-Chip SRAM until RAM will be available */
 313 #define CFG_INIT_RAM_ADDR       MPC5XXX_SRAM
 314 #ifdef CONFIG_POST
 315 /* preserve space for the post_word at end of on-chip SRAM */
 316 #define CFG_INIT_RAM_END        MPC5XXX_SRAM_POST_SIZE
 317 #else
 318 #define CFG_INIT_RAM_END        MPC5XXX_SRAM_SIZE
 319 #endif
 320
 321
 322 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
 323 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 324 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 325
 326 #define CFG_MONITOR_BASE        TEXT_BASE
 327 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 328 #   define CFG_RAMBOOT          1
 329 #endif
 330
 331 #define CFG_MONITOR_LEN         (384 << 10)     /* Reserve 384 kB for Monitor   */
 332 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 333 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 334
 335 /*
 336  * Ethernet configuration
 337  */
 338 #define CONFIG_MPC5xxx_FEC      1
 339 /*
 340  * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
 341  */
 342 /* #define CONFIG_FEC_10MBIT 1 */
 343 #define CONFIG_PHY_ADDR         0x00
 344
 345 /*
 346  * GPIO configuration
 347  *
 348  * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
 349  *      Bit 0 (mask: 0x80000000): 1
 350  * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
 351  *      00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
 352  *      01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
 353  *            Use for REV200 STK52XX boards. Do not use with REV100 modules
 354  *            (because, there I2C1 is used as I2C bus)
 355  * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
 356  * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
 357  *      000 -> All PSC2 pins are GIOPs
 358  *      001 -> CAN1/2 on PSC2 pins
 359  *             Use for REV100 STK52xx boards
 360  * use PSC6:
 361  *   on STK52xx:
 362  *      use as UART. Pins PSC6_0 to PSC6_3 are used.
 363  *      Bits 9:11 (mask: 0x00700000):
 364  *         101 -> PSC6 : Extended POST test is not available
 365  *   on MINI-FAP and TQM5200_IB:
 366  *      use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
 367  *         000 -> PSC6 could not be used as UART, CODEC or IrDA
 368  *   GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
 369  *   tests.
 370  */
 371 #if defined (CONFIG_MINIFAP)
 372 # define CFG_GPS_PORT_CONFIG    0x91000004
 373 #elif defined (CONFIG_STK52XX)
 374 # if defined (CONFIG_STK52XX_REV100)
 375 #  define CFG_GPS_PORT_CONFIG   0x81500014
 376 # else /* STK52xx REV200 and above */
 377 #  if defined (CONFIG_TQM5200_REV100)
 378 #   error TQM5200 REV100 not supported on STK52XX REV200 or above
 379 #  else/* TQM5200 REV200 and above */
 380 #   define CFG_GPS_PORT_CONFIG  0x91500004
 381 #  endif
 382 # endif
 383 #else  /* TMQ5200 Inbetriebnahme-Board */
 384 # define CFG_GPS_PORT_CONFIG    0x81000004
 385 #endif
 386
 387 /*
 388  * RTC configuration
 389  */
 390 #define CONFIG_RTC_MPC5200      1       /* use internal MPC5200 RTC */
 391
 392 /*
 393  * Miscellaneous configurable options
 394  */
 395 #define CFG_LONGHELP                    /* undef to save memory     */
 396 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt   */
 397 #if defined(CONFIG_CMD_KGDB)
 398 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size  */
 399 #else
 400 #define CFG_CBSIZE              256     /* Console I/O Buffer Size  */
 401 #endif
 402 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 403 #define CFG_MAXARGS             16      /* max number of command args   */
 404 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 405
 406 /* Enable an alternate, more extensive memory test */
 407 #define CFG_ALT_MEMTEST
 408
 409 #define CFG_MEMTEST_START       0x00100000      /* memtest works on */
 410 #define CFG_MEMTEST_END         0x00f00000      /* 1 ... 15 MB in DRAM  */
 411
 412 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 413
 414 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 415
 416 #define CFG_CACHELINE_SIZE      32      /* For MPC5xxx CPUs */
 417 #if defined(CONFIG_CMD_KGDB)
 418 #  define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value */
 419 #endif
 420
 421 /*
 422  * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
 423  * which is normally part of the default commands (CFV_CMD_DFL)
 424  */
 425 #define CONFIG_LOOPW
 426
 427 /*
 428  * Various low-level settings
 429  */
 430 #if defined(CONFIG_MPC5200)
 431 #define CFG_HID0_INIT           HID0_ICE | HID0_ICFI
 432 #define CFG_HID0_FINAL          HID0_ICE
 433 #else
 434 #define CFG_HID0_INIT           0
 435 #define CFG_HID0_FINAL          0
 436 #endif
 437
 438 #define CFG_BOOTCS_START        CFG_FLASH_BASE
 439 #define CFG_BOOTCS_SIZE         CFG_FLASH_SIZE
 440 #ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
 441 #define CFG_BOOTCS_CFG          0x0008DF30 /* for pci_clk  = 66 MHz */
 442 #else
 443 #define CFG_BOOTCS_CFG          0x0004DF30 /* for pci_clk = 33 MHz */
 444 #endif
 445 #define CFG_CS0_START           CFG_FLASH_BASE
 446 #define CFG_CS0_SIZE            CFG_FLASH_SIZE
 447
 448 #define CONFIG_LAST_STAGE_INIT
 449
 450 /*
 451  * SRAM - Do not map below 2 GB in address space, because this area is used
 452  * for SDRAM autosizing.
 453  */
 454 #define CFG_CS2_START           0xE5000000
 455 #define CFG_CS2_SIZE            0x100000        /* 1 MByte */
 456 #define CFG_CS2_CFG             0x0004D930
 457
 458 /*
 459  * Grafic controller - Do not map below 2 GB in address space, because this
 460  * area is used for SDRAM autosizing.
 461  */
 462 #define SM501_FB_BASE           0xE0000000
 463 #define CFG_CS1_START           (SM501_FB_BASE)
 464 #define CFG_CS1_SIZE            0x4000000       /* 64 MByte */
 465 #define CFG_CS1_CFG             0x8F48FF70
 466 #define SM501_MMIO_BASE         CFG_CS1_START + 0x03E00000
 467
 468 #define CFG_CS_BURST            0x00000000
 469 #define CFG_CS_DEADCYCLE        0x33333311      /* 1 dead cycle for flash and SM501 */
 470
 471 #define CFG_RESET_ADDRESS       0xff000000
 472
 473 /*-----------------------------------------------------------------------
 474  * USB stuff
 475  *-----------------------------------------------------------------------
 476  */
 477 #define CONFIG_USB_CLOCK        0x0001BBBB
 478 #define CONFIG_USB_CONFIG       0x00001000
 479
 480 /*-----------------------------------------------------------------------
 481  * IDE/ATA stuff Supports IDE harddisk
 482  *-----------------------------------------------------------------------
 483  */
 484
 485 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 486
 487 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 488 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 489
 490 #define CONFIG_IDE_RESET                /* reset for ide supported      */
 491 #define CONFIG_IDE_PREINIT
 492
 493 #define CFG_IDE_MAXBUS          1       /* max. 1 IDE bus               */
 494 #define CFG_IDE_MAXDEVICE       2       /* max. 2 drives per IDE bus    */
 495
 496 #define CFG_ATA_IDE0_OFFSET     0x0000
 497
 498 #define CFG_ATA_BASE_ADDR       MPC5XXX_ATA
 499
 500 /* Offset for data I/O                  */
 501 #define CFG_ATA_DATA_OFFSET     (0x0060)
 502
 503 /* Offset for normal register accesses  */
 504 #define CFG_ATA_REG_OFFSET      (CFG_ATA_DATA_OFFSET)
 505
 506 /* Offset for alternate registers       */
 507 #define CFG_ATA_ALT_OFFSET      (0x005C)
 508
 509 /* Interval between registers                                                */
 510 #define CFG_ATA_STRIDE          4
 511
 512 #endif /* __CONFIG_H */