include/configs/spieval.h

   1 /*
   2  * (C) Copyright 2003-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2004-2005
   6  * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 /*
  31  * High Level Configuration Options
  32  * (easy to change)
  33  */
  34
  35 #define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU */
  36 #define CONFIG_MPC5200          1       /* (more precisely an MPC5200 CPU) */
  37 #define CONFIG_TQM5200          1       /* ... on TQM5200 module */
  38 #undef CONFIG_TQM5200_REV100            /*  define for revision 100 modules */
  39 #define CONFIG_STK52XX          1       /* ... on a STK52XX base board */
  40 #define CONFIG_STK52XX_REV100   1       /*  define for revision 100 baseboards */
  41
  42 #define CFG_MPC5XXX_CLKIN       33000000 /* ... running at 33.000000MHz */
  43
  44 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH  */
  45 #define BOOTFLAG_WARM           0x02    /* Software reboot           */
  46
  47 #define CFG_CACHELINE_SIZE      32      /* For MPC5xxx CPUs */
  48 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  49 #  define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value */
  50 #endif
  51
  52 /*
  53  * Serial console configuration
  54  */
  55 #define CONFIG_PSC_CONSOLE      6       /* console is on PSC6 */
  56 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps */
  57 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
  58
  59 #ifdef CONFIG_STK52XX
  60 #undef CONFIG_PS2KBD                    /* AT-PS/2 Keyboard             */
  61 #define CONFIG_PS2MULT                  /* .. on PS/2 Multiplexer       */
  62 #define CONFIG_PS2SERIAL        6       /* .. on PSC6                   */
  63 #define CONFIG_PS2MULT_DELAY    (CFG_HZ/2)      /* Initial delay        */
  64 #define CONFIG_BOARD_EARLY_INIT_R
  65 #endif /* CONFIG_STK52XX */
  66
  67 /*
  68  * PCI Mapping:
  69  * 0x40000000 - 0x4fffffff - PCI Memory
  70  * 0x50000000 - 0x50ffffff - PCI IO Space
  71  */
  72 #ifdef CONFIG_STK52XX
  73 #define CONFIG_PCI              1
  74 #define CONFIG_PCI_PNP          1
  75 /* #define CONFIG_PCI_SCAN_SHOW 1 */
  76
  77 #define CONFIG_PCI_MEM_BUS      0x40000000
  78 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  79 #define CONFIG_PCI_MEM_SIZE     0x10000000
  80
  81 #define CONFIG_PCI_IO_BUS       0x50000000
  82 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  83 #define CONFIG_PCI_IO_SIZE      0x01000000
  84
  85 #define CONFIG_NET_MULTI        1
  86 #define CONFIG_EEPRO100         1
  87 #define CFG_RX_ETH_BUFFER       8  /* use 8 rx buffer on eepro100  */
  88 #define CONFIG_NS8382X          1
  89 #endif  /* CONFIG_STK52XX */
  90
  91 #ifdef CONFIG_PCI
  92 #define ADD_PCI_CMD             CFG_CMD_PCI
  93 #else
  94 #define ADD_PCI_CMD             0
  95 #endif
  96
  97 /*
  98  * Video console
  99  */
 100 #if 1
 101 #define CONFIG_VIDEO
 102 #define CONFIG_VIDEO_SM501
 103 #define CONFIG_VIDEO_SM501_32BPP
 104 #define CONFIG_CFB_CONSOLE
 105 #define CONFIG_VIDEO_LOGO
 106 #define CONFIG_VGA_AS_SINGLE_DEVICE
 107 #define CONFIG_CONSOLE_EXTRA_INFO
 108 #define CONFIG_VIDEO_SW_CURSOR
 109 #define CONFIG_SPLASH_SCREEN
 110 #define CFG_CONSOLE_IS_IN_ENV
 111 #endif
 112
 113 #ifdef CONFIG_VIDEO
 114 #define ADD_BMP_CMD             CFG_CMD_BMP
 115 #else
 116 #define ADD_BMP_CMD             0
 117 #endif
 118
 119 /* Partitions */
 120 #define CONFIG_MAC_PARTITION
 121 #define CONFIG_DOS_PARTITION
 122 #define CONFIG_ISO_PARTITION
 123
 124 /* USB */
 125 #ifdef CONFIG_STK52XX
 126 #define CONFIG_USB_OHCI
 127 #define ADD_USB_CMD             CFG_CMD_USB | CFG_CMD_FAT
 128 #define CONFIG_USB_STORAGE
 129 #else
 130 #define ADD_USB_CMD             0
 131 #endif
 132
 133 /* POST support */
 134 #define CONFIG_POST             (CFG_POST_MEMORY   | \
 135                                  CFG_POST_CPU      | \
 136                                  CFG_POST_I2C)
 137
 138 #ifdef CONFIG_POST
 139 #define CFG_CMD_POST_DIAG CFG_CMD_DIAG
 140 /* preserve space for the post_word at end of on-chip SRAM */
 141 #define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
 142 #else
 143 #define CFG_CMD_POST_DIAG 0
 144 #endif
 145
 146 /* IDE */
 147 #if defined (CONFIG_MINIFAP) || defined (CONFIG_STK52XX)
 148 #define ADD_IDE_CMD             (CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2)
 149 #else
 150 #define ADD_IDE_CMD             0
 151 #endif
 152
 153 /*
 154  * Supported commands
 155  */
 156 #define CONFIG_COMMANDS        (CONFIG_CMD_DFL  | \
 157                                 ADD_BMP_CMD     | \
 158                                 ADD_IDE_CMD     | \
 159                                 ADD_PCI_CMD     | \
 160                                 ADD_USB_CMD     | \
 161                                 CFG_CMD_ASKENV  | \
 162                                 CFG_CMD_DATE    | \
 163                                 CFG_CMD_DHCP    | \
 164                                 CFG_CMD_ECHO    | \
 165                                 CFG_CMD_EEPROM  | \
 166                                 CFG_CMD_I2C     | \
 167                                 CFG_CMD_MII     | \
 168                                 CFG_CMD_NFS     | \
 169                                 CFG_CMD_PING    | \
 170                                 CFG_CMD_POST_DIAG | \
 171                                 CFG_CMD_REGINFO | \
 172                                 CFG_CMD_SNTP    )
 173
 174 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 175 #include <cmd_confdefs.h>
 176
 177 #define CONFIG_TIMESTAMP                /* display image timestamps */
 178
 179 #if (TEXT_BASE == 0xFC000000)           /* Boot low */
 180 #   define CFG_LOWBOOT          1
 181 #endif
 182
 183 /*
 184  * Autobooting
 185  */
 186 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 187
 188 #define CONFIG_PREBOOT  "echo;" \
 189         "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
 190         "echo"
 191
 192 #undef  CONFIG_BOOTARGS
 193
 194 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 195         "netdev=eth0\0"                                                 \
 196         "rootpath=/opt/eldk/ppc_6xx\0"                                  \
 197         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 198         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 199                 "nfsroot=${serverip}:${rootpath}\0"                     \
 200         "addip=setenv bootargs ${bootargs} "                            \
 201                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 202                 ":${hostname}:${netdev}:off panic=1\0"                  \
 203         "flash_self=run ramargs addip;"                                 \
 204                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 205         "flash_nfs=run nfsargs addip;"                                  \
 206                 "bootm ${kernel_addr}\0"                                \
 207         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
 208         "bootfile=/tftpboot/tqm5200/uImage\0"                           \
 209         "load=tftp 200000 ${u-boot}\0"                                  \
 210         "u-boot=/tftpboot/tqm5200/u-boot.bin\0"                         \
 211         "update=protect off FC000000 FC05FFFF;"                         \
 212                 "erase FC000000 FC05FFFF;"                              \
 213                 "cp.b 200000 FC000000 ${filesize};"                     \
 214                 "protect on FC000000 FC05FFFF\0"                        \
 215         ""
 216
 217 #define CONFIG_BOOTCOMMAND      "run net_nfs"
 218
 219 /*
 220  * IPB Bus clocking configuration.
 221  */
 222 #define CFG_IPBSPEED_133                /* define for 133MHz speed */
 223
 224 #if defined(CFG_IPBSPEED_133)
 225 /*
 226  * PCI Bus clocking configuration
 227  *
 228  * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
 229  * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
 230  * been tested with a IPB Bus Clock of 66 MHz.
 231  */
 232 #define CFG_PCISPEED_66                 /* define for 66MHz speed */
 233 #endif
 234
 235 /*
 236  * I2C configuration
 237  */
 238 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 239 #ifdef CONFIG_TQM5200_REV100
 240 #define CFG_I2C_MODULE          1       /* Select I2C module #1 for rev. 100 board */
 241 #else
 242 #define CFG_I2C_MODULE          2       /* Select I2C module #2 for all other revs */
 243 #endif
 244
 245 /*
 246  * I2C clock frequency
 247  *
 248  * Please notice, that the resulting clock frequency could differ from the
 249  * configured value. This is because the I2C clock is derived from system
 250  * clock over a frequency divider with only a few divider values. U-boot
 251  * calculates the best approximation for CFG_I2C_SPEED. However the calculated
 252  * approximation allways lies below the configured value, never above.
 253  */
 254 #define CFG_I2C_SPEED           100000 /* 100 kHz */
 255 #define CFG_I2C_SLAVE           0x7F
 256
 257 /*
 258  * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
 259  * also). For other EEPROMs configuration should be verified. On Mini-FAP the
 260  * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
 261  * same configuration could be used.
 262  */
 263 #define CFG_I2C_EEPROM_ADDR             0x50    /* 1010000x */
 264 #define CFG_I2C_EEPROM_ADDR_LEN         2
 265 #define CFG_EEPROM_PAGE_WRITE_BITS      5       /* =32 Bytes per write */
 266 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  20
 267
 268 /*
 269  * HW-Monitor configuration on Mini-FAP
 270  */
 271 #if defined (CONFIG_MINIFAP)
 272 #define CFG_I2C_HWMON_ADDR              0x2C
 273 #endif
 274
 275 /* List of I2C addresses to be verified by POST */
 276 #if defined (CONFIG_MINIFAP)
 277 #undef I2C_ADDR_LIST
 278 #define I2C_ADDR_LIST   {       CFG_I2C_EEPROM_ADDR,    \
 279                                 CFG_I2C_HWMON_ADDR,     \
 280                                 CFG_I2C_SLAVE }
 281 #endif
 282
 283 /*
 284  * Flash configuration
 285  */
 286 #define CFG_FLASH_BASE          TEXT_BASE /* 0xFC000000 */
 287
 288 /* use CFI flash driver if no module variant is spezified */
 289 #define CFG_FLASH_CFI           1       /* Flash is CFI conformant */
 290 #define CFG_FLASH_CFI_DRIVER    1       /* Use the common driver */
 291 #define CFG_FLASH_BANKS_LIST    { CFG_BOOTCS_START }
 292 #define CFG_FLASH_EMPTY_INFO
 293 #define CFG_FLASH_SIZE          0x04000000 /* 64 MByte */
 294 #define CFG_MAX_FLASH_SECT      512     /* max num of sects on one chip */
 295 #undef CFG_FLASH_USE_BUFFER_WRITE       /* not supported yet for AMD */
 296
 297 #if !defined(CFG_LOWBOOT)
 298 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + 0x00760000 + 0x00800000)
 299 #else   /* CFG_LOWBOOT */
 300 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + 0x00060000)
 301 #endif  /* CFG_LOWBOOT */
 302 #define CFG_MAX_FLASH_BANKS     1       /* max num of flash banks
 303                                            (= chip selects) */
 304 #define CFG_FLASH_ERASE_TOUT    240000  /* Flash Erase Timeout (in ms)  */
 305 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (in ms)  */
 306
 307
 308 /*
 309  * Environment settings
 310  */
 311 #define CFG_ENV_IS_IN_FLASH     1
 312 #define CFG_ENV_SIZE            0x10000
 313 #define CFG_ENV_SECT_SIZE       0x20000
 314 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
 315 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 316
 317 /*
 318  * Memory map
 319  */
 320 #define CFG_MBAR                0xF0000000
 321 #define CFG_SDRAM_BASE          0x00000000
 322 #define CFG_DEFAULT_MBAR        0x80000000
 323
 324 /* Use ON-Chip SRAM until RAM will be available */
 325 #define CFG_INIT_RAM_ADDR       MPC5XXX_SRAM
 326 #ifdef CONFIG_POST
 327 /* preserve space for the post_word at end of on-chip SRAM */
 328 #define CFG_INIT_RAM_END        MPC5XXX_SRAM_POST_SIZE
 329 #else
 330 #define CFG_INIT_RAM_END        MPC5XXX_SRAM_SIZE
 331 #endif
 332
 333
 334 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
 335 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 336 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 337
 338 #define CFG_MONITOR_BASE        TEXT_BASE
 339 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 340 #   define CFG_RAMBOOT          1
 341 #endif
 342
 343 #define CFG_MONITOR_LEN         (384 << 10)     /* Reserve 384 kB for Monitor   */
 344 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 345 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 346
 347 /*
 348  * Ethernet configuration
 349  */
 350 #define CONFIG_MPC5xxx_FEC      1
 351 /*
 352  * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
 353  */
 354 /* #define CONFIG_FEC_10MBIT 1 */
 355 #define CONFIG_PHY_ADDR         0x00
 356
 357 /*
 358  * GPIO configuration
 359  *
 360  * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
 361  *      Bit 0 (mask: 0x80000000): 1
 362  * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
 363  *      00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
 364  *      01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
 365  *            Use for REV200 STK52XX boards. Do not use with REV100 modules
 366  *            (because, there I2C1 is used as I2C bus)
 367  * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
 368  * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
 369  *      000 -> All PSC2 pins are GIOPs
 370  *      001 -> CAN1/2 on PSC2 pins
 371  *             Use for REV100 STK52xx boards
 372  * use PSC6:
 373  *   on STK52xx:
 374  *      use as UART. Pins PSC6_0 to PSC6_3 are used.
 375  *      Bits 9:11 (mask: 0x00700000):
 376  *         101 -> PSC6 : Extended POST test is not available
 377  *   on MINI-FAP and TQM5200_IB:
 378  *      use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
 379  *         000 -> PSC6 could not be used as UART, CODEC or IrDA
 380  *   GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
 381  *   tests.
 382  */
 383 #if defined (CONFIG_MINIFAP)
 384 # define CFG_GPS_PORT_CONFIG    0x91000004
 385 #elif defined (CONFIG_STK52XX)
 386 # if defined (CONFIG_STK52XX_REV100)
 387 #  define CFG_GPS_PORT_CONFIG   0x81500014
 388 # else /* STK52xx REV200 and above */
 389 #  if defined (CONFIG_TQM5200_REV100)
 390 #   error TQM5200 REV100 not supported on STK52XX REV200 or above
 391 #  else/* TQM5200 REV200 and above */
 392 #   define CFG_GPS_PORT_CONFIG  0x91500004
 393 #  endif
 394 # endif
 395 #else  /* TMQ5200 Inbetriebnahme-Board */
 396 # define CFG_GPS_PORT_CONFIG    0x81000004
 397 #endif
 398
 399 /*
 400  * RTC configuration
 401  */
 402 #define CONFIG_RTC_MPC5200      1       /* use internal MPC5200 RTC */
 403
 404 /*
 405  * Miscellaneous configurable options
 406  */
 407 #define CFG_LONGHELP                    /* undef to save memory     */
 408 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt   */
 409 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 410 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size  */
 411 #else
 412 #define CFG_CBSIZE              256     /* Console I/O Buffer Size  */
 413 #endif
 414 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 415 #define CFG_MAXARGS             16      /* max number of command args   */
 416 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 417
 418 /* Enable an alternate, more extensive memory test */
 419 #define CFG_ALT_MEMTEST
 420
 421 #define CFG_MEMTEST_START       0x00100000      /* memtest works on */
 422 #define CFG_MEMTEST_END         0x00f00000      /* 1 ... 15 MB in DRAM  */
 423
 424 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 425
 426 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 427
 428 /*
 429  * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
 430  * which is normally part of the default commands (CFV_CMD_DFL)
 431  */
 432 #define CONFIG_LOOPW
 433
 434 /*
 435  * Various low-level settings
 436  */
 437 #if defined(CONFIG_MPC5200)
 438 #define CFG_HID0_INIT           HID0_ICE | HID0_ICFI
 439 #define CFG_HID0_FINAL          HID0_ICE
 440 #else
 441 #define CFG_HID0_INIT           0
 442 #define CFG_HID0_FINAL          0
 443 #endif
 444
 445 #define CFG_BOOTCS_START        CFG_FLASH_BASE
 446 #define CFG_BOOTCS_SIZE         CFG_FLASH_SIZE
 447 #ifdef CFG_PCISPEED_66
 448 #define CFG_BOOTCS_CFG          0x0008DF30 /* for pci_clk  = 66 MHz */
 449 #else
 450 #define CFG_BOOTCS_CFG          0x0004DF30 /* for pci_clk = 33 MHz */
 451 #endif
 452 #define CFG_CS0_START           CFG_FLASH_BASE
 453 #define CFG_CS0_SIZE            CFG_FLASH_SIZE
 454
 455 #define CONFIG_LAST_STAGE_INIT
 456
 457 /*
 458  * SRAM - Do not map below 2 GB in address space, because this area is used
 459  * for SDRAM autosizing.
 460  */
 461 #define CFG_CS2_START           0xE5000000
 462 #define CFG_CS2_SIZE            0x100000        /* 1 MByte */
 463 #define CFG_CS2_CFG             0x0004D930
 464
 465 /*
 466  * Grafic controller - Do not map below 2 GB in address space, because this
 467  * area is used for SDRAM autosizing.
 468  */
 469 #define SM501_FB_BASE           0xE0000000
 470 #define CFG_CS1_START           (SM501_FB_BASE)
 471 #define CFG_CS1_SIZE            0x4000000       /* 64 MByte */
 472 #define CFG_CS1_CFG             0x8F48FF70
 473 #define SM501_MMIO_BASE         CFG_CS1_START + 0x03E00000
 474
 475 #define CFG_CS_BURST            0x00000000
 476 #define CFG_CS_DEADCYCLE        0x33333311      /* 1 dead cycle for flash and SM501 */
 477
 478 #define CFG_RESET_ADDRESS       0xff000000
 479
 480 /*-----------------------------------------------------------------------
 481  * USB stuff
 482  *-----------------------------------------------------------------------
 483  */
 484 #define CONFIG_USB_CLOCK        0x0001BBBB
 485 #define CONFIG_USB_CONFIG       0x00001000
 486
 487 /*-----------------------------------------------------------------------
 488  * IDE/ATA stuff Supports IDE harddisk
 489  *-----------------------------------------------------------------------
 490  */
 491
 492 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 493
 494 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 495 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 496
 497 #define CONFIG_IDE_RESET                /* reset for ide supported      */
 498 #define CONFIG_IDE_PREINIT
 499
 500 #define CFG_IDE_MAXBUS          1       /* max. 1 IDE bus               */
 501 #define CFG_IDE_MAXDEVICE       2       /* max. 2 drives per IDE bus    */
 502
 503 #define CFG_ATA_IDE0_OFFSET     0x0000
 504
 505 #define CFG_ATA_BASE_ADDR       MPC5XXX_ATA
 506
 507 /* Offset for data I/O                  */
 508 #define CFG_ATA_DATA_OFFSET     (0x0060)
 509
 510 /* Offset for normal register accesses  */
 511 #define CFG_ATA_REG_OFFSET      (CFG_ATA_DATA_OFFSET)
 512
 513 /* Offset for alternate registers       */
 514 #define CFG_ATA_ALT_OFFSET      (0x005C)
 515
 516 /* Interval between registers                                                */
 517 #define CFG_ATA_STRIDE          4
 518
 519 #endif /* __CONFIG_H */