include/configs/stxssa.h

   1 /*
   2  * (C) Copyright 2005 Embedded Alley Solutions, Inc.
   3  * Dan Malek <dan@embeddedalley.com>
   4  * Copied from STx GP3.
   5  * Updates for Silicon Tx GP3 SSA board.
   6  *
   7  * (C) Copyright 2002,2003 Motorola,Inc.
   8  * Xianghua Xiao <X.Xiao@motorola.com>
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 /* mpc8560ads board configuration file */
  30 /* please refer to doc/README.mpc85xx for more info */
  31 /* make sure you change the MAC address and other network params first,
  32  * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
  33  */
  34
  35 #ifndef __CONFIG_H
  36 #define __CONFIG_H
  37
  38 /* High Level Configuration Options */
  39 #define CONFIG_BOOKE            1       /* BOOKE                */
  40 #define CONFIG_E500             1       /* BOOKE e500 family    */
  41 #define CONFIG_MPC85xx          1       /* MPC8540/MPC8560      */
  42 #define CONFIG_CPM2             1       /* has CPM2 */
  43 #define CONFIG_STXSSA           1       /* Silicon Tx GPPP SSA board specific*/
  44
  45 #define CONFIG_PCI                      /* PCI ethernet support */
  46 #define CONFIG_TSEC_ENET                /* tsec ethernet support*/
  47 #undef CONFIG_ETHER_ON_FCC              /* cpm FCC ethernet support */
  48 #define CONFIG_ENV_OVERWRITE
  49 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
  50 #undef  CONFIG_DDR_ECC                  /* only for ECC DDR module */
  51 #undef CONFIG_DDR_DLL                   /* possible DLL fix needed */
  52 #define CONFIG_DDR_2T_TIMING            /* Sets the 2T timing bit */
  53
  54
  55 /* sysclk for MPC85xx
  56  */
  57
  58 #define CONFIG_SYS_CLK_FREQ     33000000 /* most pci cards are 33Mhz */
  59
  60 /* Blinkin' LEDs for Robert :-)
  61 */
  62 #define CONFIG_SHOW_ACTIVITY 1
  63
  64 /*
  65  * These can be toggled for performance analysis, otherwise use default.
  66  */
  67 #define CONFIG_L2_CACHE                         /* toggle L2 cache             */
  68 #define  CONFIG_BTB                             /* toggle branch predition */
  69 #define  CONFIG_ADDR_STREAMING                  /* toggle addr streaming        */
  70
  71 #define CONFIG_BOARD_EARLY_INIT_F   1           /* Call board_pre_init   */
  72
  73 #undef  CFG_DRAM_TEST                           /* memory test, takes time      */
  74 #define CFG_MEMTEST_START       0x00200000      /* memtest region */
  75 #define CFG_MEMTEST_END         0x00400000
  76
  77
  78 /* Localbus connector.  There are many options that can be
  79  * connected here, including sdram or lots of flash.
  80  * This address, however, is used to configure a 256M local bus
  81  * window that includes the Config latch below.
  82  */
  83 #define CFG_LBC_OPTION_BASE     0xF0000000      /* Localbus Extension */
  84 #define CFG_LBC_OPTION_SIZE     256             /* 256MB */
  85
  86 /* There are various flash options used, we configure for the largest,
  87  * which is 64Mbytes.  The CFI works fine and will discover the proper
  88  * sizes.
  89  */
  90 #ifdef CONFIG_STXSSA_4M
  91 #define CFG_FLASH_BASE          0xFFC00000      /* start of  4 MiB flash */
  92 #else
  93 #define CFG_FLASH_BASE          0xFC000000      /* start of 64 MiB flash */
  94 #endif
  95 #define CFG_BR0_PRELIM  (CFG_FLASH_BASE | 0x1801) /* port size 32bit     */
  96 #define CFG_OR0_PRELIM  (CFG_FLASH_BASE | 0x0FF7)
  97
  98 #define CFG_FLASH_CFI           1
  99 #define CFG_FLASH_CFI_DRIVER    1
 100 #undef CFG_FLASH_USE_BUFFER_WRITE       /* use buffered writes (20x faster) */
 101 #define CFG_MAX_FLASH_SECT      256     /* max number of sectors on one chip */
 102 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks   */
 103
 104 #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
 105
 106 #define CFG_FLASH_PROTECTION
 107
 108 /* The configuration latch is Chip Select 1.
 109  * It's an 8-bit latch in the lower 8 bits of the word.
 110  */
 111 #define CFG_LBC_CFGLATCH_BASE   0xFB000000      /* Base of config latch */
 112 #define CFG_BR1_PRELIM          0xFB001801      /* 32-bit port */
 113 #define CFG_OR1_PRELIM          0xFFFF0FF7      /* 64K is enough */
 114
 115 #define CFG_MONITOR_BASE        TEXT_BASE       /* start of monitor     */
 116
 117 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 118 #define CFG_RAMBOOT
 119 #else
 120 #undef  CFG_RAMBOOT
 121 #endif
 122
 123 #ifdef CFG_RAMBOOT
 124 #define CFG_CCSRBAR_DEFAULT     0x40000000      /* CCSRBAR by BDI cfg   */
 125 #else
 126 #define CFG_CCSRBAR_DEFAULT     0xff700000      /* CCSRBAR Default      */
 127 #endif
 128 #define CFG_CCSRBAR             0xe0000000      /* relocated CCSRBAR    */
 129 #define CFG_IMMR                CFG_CCSRBAR     /* PQII uses CFG_IMMR   */
 130
 131
 132 /*
 133  * DDR Setup
 134  */
 135
 136 /*
 137  * Base addresses -- Note these are effective addresses where the
 138  * actual resources get mapped (not physical addresses)
 139  */
 140 #define CFG_DDR_SDRAM_BASE      0x00000000      /* DDR is system memory  */
 141 #define CFG_SDRAM_BASE          CFG_DDR_SDRAM_BASE
 142
 143 #define SPD_EEPROM_ADDRESS      0x54            /*  DDR DIMM */
 144
 145 #undef CONFIG_CLOCKS_IN_MHZ
 146
 147 /* local bus definitions */
 148 #define CFG_BR2_PRELIM          0xf8001861      /* 64MB localbus SDRAM  */
 149 #define CFG_OR2_PRELIM          0xfc006901
 150 #define CFG_LBC_LCRR            0x00030004      /* local bus freq       */
 151 #define CFG_LBC_LBCR            0x00000000
 152 #define CFG_LBC_LSRT            0x20000000
 153 #define CFG_LBC_MRTPR           0x20000000
 154 #define CFG_LBC_LSDMR_1         0x2861b723
 155 #define CFG_LBC_LSDMR_2         0x0861b723
 156 #define CFG_LBC_LSDMR_3         0x0861b723
 157 #define CFG_LBC_LSDMR_4         0x1861b723
 158 #define CFG_LBC_LSDMR_5         0x4061b723
 159
 160 #define CONFIG_L1_INIT_RAM
 161 #define CFG_INIT_RAM_LOCK       1
 162 #define CFG_INIT_RAM_ADDR       0x60000000      /* Initial RAM address  */
 163 #define CFG_INIT_RAM_END        0x4000          /* End of used area in RAM */
 164
 165 #define CFG_GBL_DATA_SIZE       128             /* num bytes initial data */
 166 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 167 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 168
 169 #define CFG_MONITOR_LEN         (256 * 1024)    /* Reserve 256 kB for Mon */
 170 #define CFG_MALLOC_LEN          (512 * 1024)    /* Reserved for malloc */
 171
 172 /* Serial Port */
 173 #define CONFIG_CONS_INDEX     2
 174 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 175 #define CFG_NS16550
 176 #define CFG_NS16550_SERIAL
 177 #define CFG_NS16550_REG_SIZE    1
 178 #define CFG_NS16550_CLK         get_bus_freq(0)
 179
 180 #define CFG_BAUDRATE_TABLE  \
 181         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 182
 183 #define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
 184 #define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
 185
 186 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 187 #define CFG_HUSH_PARSER         1       /* Use the HUSH parser          */
 188 #ifdef  CFG_HUSH_PARSER
 189 #define CFG_PROMPT_HUSH_PS2 "> "
 190 #endif
 191
 192 /* I2C */
 193 #define CONFIG_FSL_I2C                  /* Use FSL common I2C driver */
 194 #define  CONFIG_HARD_I2C                /* I2C with hardware support*/
 195 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged */
 196 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
 197 #define CFG_I2C_SLAVE           0x7F
 198 #if 0
 199 #define CFG_I2C_NOPROBES        {0x00}  /* Don't probe these addrs */
 200 #else
 201 /* I did the 'if 0' so we could keep the syntax above if ever needed. */
 202 #undef CFG_I2C_NOPROBES
 203 #endif
 204 #define CFG_I2C_OFFSET          0x3000
 205
 206 /* I2C EEPROM.  AT24C32, we keep our environment in here.
 207 */
 208 #define CFG_I2C_EEPROM_ADDR             0x51    /* 1010001x             */
 209 #define CFG_I2C_EEPROM_ADDR_LEN         2
 210 #define CFG_EEPROM_PAGE_WRITE_BITS      5       /* =32 Bytes per write  */
 211 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 212 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  20
 213
 214 /*
 215  * Standard 8555 PCI mapping.
 216  * Addresses are mapped 1-1.
 217  */
 218 #define CFG_PCI1_MEM_BASE       0x80000000
 219 #define CFG_PCI1_MEM_PHYS       CFG_PCI1_MEM_BASE
 220 #define CFG_PCI1_MEM_SIZE       0x20000000      /* 512M */
 221 #define CFG_PCI1_IO_BASE        0x00000000
 222 #define CFG_PCI1_IO_PHYS        0xe2000000
 223 #define CFG_PCI1_IO_SIZE        0x01000000      /* 16M */
 224
 225 #define CFG_PCI2_MEM_BASE       0xa0000000
 226 #define CFG_PCI2_MEM_PHYS       CFG_PCI2_MEM_BASE
 227 #define CFG_PCI2_MEM_SIZE       0x20000000      /* 512M */
 228 #define CFG_PCI2_IO_BASE        0x00000000
 229 #define CFG_PCI2_IO_PHYS        0xe3000000
 230 #define CFG_PCI2_IO_SIZE        0x01000000      /* 16M */
 231
 232 #if defined(CONFIG_PCI)                 /* PCI Ethernet card */
 233
 234 #define CONFIG_NET_MULTI
 235 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 236
 237 #define CONFIG_EEPRO100
 238 #define CONFIG_TULIP
 239
 240 #if !defined(CONFIG_PCI_PNP)
 241   #define PCI_ENET0_IOADDR      0xe0000000
 242   #define PCI_ENET0_MEMADDR     0xe0000000
 243   #define PCI_IDSEL_NUMBER      0x0c    /* slot0->3(IDSEL)=12->15 */
 244 #endif
 245
 246 #define CONFIG_PCI_SCAN_SHOW
 247 #define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 248
 249 #endif /* CONFIG_PCI */
 250
 251 #if defined(CONFIG_TSEC_ENET)
 252
 253 #ifndef CONFIG_NET_MULTI
 254 #define CONFIG_NET_MULTI        1
 255 #endif
 256
 257 #define CONFIG_MII              1       /* MII PHY management           */
 258
 259 #define CONFIG_TSEC1    1
 260 #define CONFIG_TSEC1_NAME       "TSEC0"
 261 #define CONFIG_TSEC2    1
 262 #define CONFIG_TSEC2_NAME       "TSEC1"
 263 #define CONFIG_MPS85XX_FEC
 264
 265 #define TSEC1_PHY_ADDR          2
 266 #define TSEC2_PHY_ADDR          4
 267 #define TSEC1_PHYIDX            0
 268 #define TSEC2_PHYIDX            0
 269 #define CONFIG_ETHPRIME         "TSEC0"
 270
 271 #elif defined(CONFIG_ETHER_ON_FCC)      /* CPM FCC Ethernet */
 272
 273 #define CONFIG_ETHER_ON_FCC2            /* define if ether on FCC   */
 274 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 275 #define CONFIG_ETHER_INDEX      2       /* which channel for ether  */
 276
 277 #if (CONFIG_ETHER_INDEX == 2)
 278   /*
 279    * - Rx-CLK is CLK13
 280    * - Tx-CLK is CLK14
 281    * - Select bus for bd/buffers
 282    * - Full duplex
 283    */
 284   #define CFG_CMXFCR_MASK       (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
 285   #define CFG_CMXFCR_VALUE      (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
 286   #define CFG_CPMFCR_RAMTYPE    0
 287 #if 0
 288   #define CFG_FCC_PSMR          (FCC_PSMR_FDE)
 289 #else
 290   #define CFG_FCC_PSMR          0
 291 #endif
 292   #define FETH2_RST             0x01
 293 #elif (CONFIG_ETHER_INDEX == 3)
 294   /* need more definitions here for FE3 */
 295   #define FETH3_RST             0x80
 296 #endif                                  /* CONFIG_ETHER_INDEX */
 297
 298 /* MDIO is done through the TSEC0 control.
 299 */
 300 #define CONFIG_MII                      /* MII PHY management */
 301 #undef CONFIG_BITBANGMII                /* bit-bang MII PHY management  */
 302
 303 #endif
 304
 305 /* Environment - default config is in flash, see below */
 306 #if 0   /* in EEPROM */
 307 # define CFG_ENV_IS_IN_EEPROM   1
 308 # define CFG_ENV_OFFSET         0
 309 # define CFG_ENV_SIZE           2048
 310 #else   /* in flash */
 311 # define CFG_ENV_IS_IN_FLASH    1
 312 # ifdef CONFIG_STXSSA_4M
 313 #  define CFG_ENV_SECT_SIZE     0x20000
 314 # else  /* default configuration - 64 MiB flash */
 315 #  define CFG_ENV_SECT_SIZE     0x40000
 316 # endif
 317 # define CFG_ENV_ADDR           (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
 318 # define CFG_ENV_SIZE           0x4000
 319 # define CFG_ENV_ADDR_REDUND    (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE)
 320 # define CFG_ENV_SIZE_REDUND    (CFG_ENV_SIZE)
 321 #endif
 322
 323 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 324 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
 325
 326 #define CONFIG_TIMESTAMP                /* Print image info with ts     */
 327
 328 #if defined(CFG_RAMBOOT)
 329   #if defined(CONFIG_PCI)
 330   #define  CONFIG_COMMANDS      ((CONFIG_CMD_DFL | CFG_CMD_PCI | \
 331                                 CFG_CMD_PING | CFG_CMD_I2C) & \
 332                                  ~(CFG_CMD_ENV | \
 333                                   CFG_CMD_LOADS ))
 334   #elif defined(CONFIG_TSEC_ENET)
 335   #define  CONFIG_COMMANDS      ((CONFIG_CMD_DFL | CFG_CMD_PING | \
 336                                 CFG_CMD_MII | CFG_CMD_I2C ) & \
 337                                 ~(CFG_CMD_ENV))
 338   #elif defined(CONFIG_ETHER_ON_FCC)
 339   #define  CONFIG_COMMANDS      ((CONFIG_CMD_DFL | CFG_CMD_MII | \
 340                                 CFG_CMD_PING | CFG_CMD_I2C) & \
 341                                 ~(CFG_CMD_ENV))
 342   #endif
 343 #else
 344   #if defined(CONFIG_PCI)
 345   #define  CONFIG_COMMANDS      (CONFIG_CMD_DFL | CFG_CMD_PCI | \
 346                                 CFG_CMD_ELF | CFG_CMD_PING | CFG_CMD_I2C)
 347   #elif defined(CONFIG_TSEC_ENET)
 348   #define  CONFIG_COMMANDS      (CONFIG_CMD_DFL | CFG_CMD_PING | \
 349                                 CFG_CMD_ELF | CFG_CMD_MII | CFG_CMD_I2C)
 350   #elif defined(CONFIG_ETHER_ON_FCC)
 351   #define  CONFIG_COMMANDS      (CONFIG_CMD_DFL | CFG_CMD_MII | \
 352                                 CFG_CMD_ELF | CFG_CMD_PING | CFG_CMD_I2C)
 353   #endif
 354 #endif
 355 #include <cmd_confdefs.h>
 356
 357 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 358
 359 /*
 360  * Miscellaneous configurable options
 361  */
 362 #define CFG_LONGHELP                    /* undef to save memory         */
 363 #define CFG_PROMPT      "SSA=> "        /* Monitor Command Prompt       */
 364 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 365 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 366 #else
 367 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 368 #endif
 369 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 370 #define CFG_MAXARGS     16              /* max number of command args   */
 371 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 372 #define CFG_LOAD_ADDR   0x1000000       /* default load address */
 373 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 374
 375 /*
 376  * For booting Linux, the board info and command line data
 377  * have to be in the first 8 MB of memory, since this is
 378  * the maximum mapped by the Linux kernel during initialization.
 379  */
 380 #define CFG_BOOTMAPSZ           (8 << 20) /* Initial Memory map for Linux */
 381
 382 /* Cache Configuration */
 383 #define CFG_DCACHE_SIZE         32768
 384 #define CFG_CACHELINE_SIZE      32
 385 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 386 #define CFG_CACHELINE_SHIFT     5       /* log base 2 of the above value */
 387 #endif
 388
 389 /*
 390  * Internal Definitions
 391  *
 392  * Boot Flags
 393  */
 394 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 395 #define BOOTFLAG_WARM   0x02            /* Software reboot              */
 396
 397 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 398 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 399 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 400 #endif
 401
 402 /*Note: change below for your network setting!!! */
 403 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
 404 #define CONFIG_ETHADDR   00:e0:0c:07:9b:8a
 405 #define CONFIG_HAS_ETH1
 406 #define CONFIG_ETH1ADDR  00:e0:0c:07:9b:8b
 407 #define CONFIG_HAS_ETH2
 408 #define CONFIG_ETH2ADDR  00:e0:0c:07:9b:8c
 409 #endif
 410
 411 /*
 412  * Environment in EEPROM is compatible with different flash sector sizes,
 413  * but only little space is available, so we use a very simple setup.
 414  * With environment in flash, we use a more powerful default configuration.
 415  */
 416 #ifdef CFG_ENV_IS_IN_EEPROM             /* use restricted "standard" environment */
 417
 418 #define CONFIG_BAUDRATE         38400
 419
 420 #define CONFIG_BOOTDELAY        3       /* -1 disable autoboot */
 421 #define CONFIG_BOOTCOMMAND      "bootm 0xffc00000 0xffd00000"
 422 #define CONFIG_BOOTARGS         "root=/dev/nfs rw ip=any console=ttyS1,$baudrate"
 423 #define CONFIG_SERVERIP         192.168.85.1
 424 #define CONFIG_IPADDR           192.168.85.60
 425 #define CONFIG_GATEWAYIP        192.168.85.1
 426 #define CONFIG_NETMASK          255.255.255.0
 427 #define CONFIG_HOSTNAME         STX_SSA
 428 #define CONFIG_ROOTPATH         /gppproot
 429 #define CONFIG_BOOTFILE         uImage
 430 #define CONFIG_LOADADDR         0x1000000
 431
 432 #else /* ENV IS IN FLASH                -- use a full-blown envionment */
 433
 434 #define CONFIG_BAUDRATE         115200
 435
 436 #define CONFIG_BOOTDELAY        5       /* -1 disable autoboot */
 437
 438 #define CONFIG_PREBOOT  "echo;" \
 439         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 440         "echo"
 441
 442 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs   */
 443
 444 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 445         "hostname=gp3ssa\0"                                             \
 446         "bootfile=/tftpboot/gp3ssa/uImage\0"                            \
 447         "loadaddr=400000\0"                                             \
 448         "netdev=eth0\0"                                                 \
 449         "consdev=ttyS1\0"                                               \
 450         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 451                 "nfsroot=$serverip:$rootpath\0"                         \
 452         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 453         "addip=setenv bootargs $bootargs "                              \
 454                 "ip=$ipaddr:$serverip:$gatewayip:$netmask"              \
 455                 ":$hostname:$netdev:off panic=1\0"                      \
 456         "addcons=setenv bootargs $bootargs "                            \
 457                 "console=$consdev,$baudrate\0"                          \
 458         "flash_nfs=run nfsargs addip addcons;"                          \
 459                 "bootm $kernel_addr\0"                                  \
 460         "flash_self=run ramargs addip addcons;"                         \
 461                 "bootm $kernel_addr $ramdisk_addr\0"                    \
 462         "net_nfs=tftp $loadaddr $bootfile;"                             \
 463                 "run nfsargs addip addcons;bootm\0"                     \
 464         "rootpath=/opt/eldk/ppc_85xx\0"                                 \
 465         "kernel_addr=FC000000\0"                                        \
 466         "ramdisk_addr=FC200000\0"                                       \
 467         ""
 468 #define CONFIG_BOOTCOMMAND      "run flash_self"
 469
 470 #endif  /* CFG_ENV_IS_IN_EEPROM */
 471
 472 #endif  /* __CONFIG_H */