include/configs/tao3530.h

   1 /*
   2  * Configuration settings for the TechNexion TAO-3530 SOM
   3  * equipped on Thunder baseboard.
   4  *
   5  * Edward Lin <linuxfae@technexion.com>
   6  * Tapani Utriainen <linuxfae@technexion.com>
   7  *
   8  * Copyright (C) 2013 Stefan Roese <sr@denx.de>
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #ifndef __CONFIG_H
  14 #define __CONFIG_H
  15
  16 /*
  17  * High Level Configuration Options
  18  */
  19 #define CONFIG_OMAP                     /* in a TI OMAP core */
  20
  21 #define CONFIG_OMAP_GPIO
  22
  23 #define CONFIG_SDRC                     /* Has an SDRC controller */
  24
  25 #include <asm/arch/cpu.h>               /* get chip and board defs */
  26 #include <asm/arch/omap.h>
  27
  28 /* Clock Defines */
  29 #define V_OSCK                  26000000        /* Clock output from T2 */
  30 #define V_SCLK                  (V_OSCK >> 1)
  31
  32 #define CONFIG_MISC_INIT_R
  33
  34 #define CONFIG_CMDLINE_TAG
  35 #define CONFIG_SETUP_MEMORY_TAGS
  36 #define CONFIG_INITRD_TAG
  37 #define CONFIG_REVISION_TAG
  38
  39 /*
  40  * Size of malloc() pool
  41  */
  42 #define CONFIG_SYS_MALLOC_LEN           (4 << 20)
  43 #define CONFIG_ENV_SIZE                 (128 << 10)     /* 128 KiB sector */
  44
  45 /*
  46  * Hardware drivers
  47  */
  48
  49 /*
  50  * NS16550 Configuration
  51  */
  52 #define V_NS16550_CLK                   48000000        /* 48MHz (APLL96/2) */
  53
  54 #define CONFIG_SYS_NS16550_SERIAL
  55 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  56 #define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
  57
  58 /*
  59  * select serial console configuration
  60  */
  61 #define CONFIG_CONS_INDEX               3
  62 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
  63
  64 /* allow to overwrite serial and ethaddr */
  65 #define CONFIG_ENV_OVERWRITE
  66
  67 /* GPIO banks */
  68 #define CONFIG_OMAP3_GPIO_2             /* GPIO32 ..63  is in GPIO bank 2 */
  69 #define CONFIG_OMAP3_GPIO_3             /* GPIO64 ..95  is in GPIO bank 3 */
  70 #define CONFIG_OMAP3_GPIO_4             /* GPIO96 ..127 is in GPIO bank 4 */
  71 #define CONFIG_OMAP3_GPIO_5             /* GPIO128..159 is in GPIO bank 5 */
  72 #define CONFIG_OMAP3_GPIO_6             /* GPIO160..191 is in GPIO bank 6 */
  73
  74 /* commands to include */
  75 #define CONFIG_CMD_MTDPARTS     /* Enable MTD parts commands */
  76 #define CONFIG_MTD_DEVICE       /* needed for mtdparts commands */
  77 #define MTDIDS_DEFAULT                  "nand0=nand"
  78 #define MTDPARTS_DEFAULT                "mtdparts=nand:512k(x-loader),"\
  79                                         "1920k(u-boot),128k(u-boot-env),"\
  80                                         "4m(kernel),-(fs)"
  81
  82 #define CONFIG_CMD_NAND         /* NAND support                 */
  83
  84 #define CONFIG_SYS_I2C
  85 #define CONFIG_SYS_I2C_OMAP34XX
  86 #define CONFIG_SYS_OMAP24_I2C_SPEED     100000
  87 #define CONFIG_SYS_OMAP24_I2C_SLAVE     1
  88 #define CONFIG_I2C_MULTI_BUS
  89
  90 /*
  91  * TWL4030
  92  */
  93 #define CONFIG_TWL4030_POWER
  94 #define CONFIG_TWL4030_LED
  95
  96 /*
  97  * Board NAND Info.
  98  */
  99 #define CONFIG_NAND_OMAP_GPMC
 100 #define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
 101                                                         /* to access nand */
 102 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
 103                                                         /* to access nand at */
 104                                                         /* CS0 */
 105
 106 #define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of NAND */
 107                                                         /* devices */
 108 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
 109 /* Environment information */
 110
 111 #define CONFIG_EXTRA_ENV_SETTINGS \
 112         "loadaddr=0x82000000\0" \
 113         "console=ttyO2,115200n8\0" \
 114         "mpurate=600\0" \
 115         "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \
 116         "tv_mode=omapfb.mode=tv:ntsc\0" \
 117         "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \
 118         "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \
 119         "extra_options= \0" \
 120         "mmcdev=0\0" \
 121         "mmcroot=/dev/mmcblk0p2 rw\0" \
 122         "mmcrootfstype=ext3 rootwait\0" \
 123         "nandroot=ubi0:rootfs ubi.mtd=4\0" \
 124         "nandrootfstype=ubifs\0" \
 125         "mmcargs=setenv bootargs console=${console} " \
 126                 "mpurate=${mpurate} " \
 127                 "${video_mode} " \
 128                 "root=${mmcroot} " \
 129                 "rootfstype=${mmcrootfstype} " \
 130                 "${extra_options}\0" \
 131         "nandargs=setenv bootargs console=${console} " \
 132                 "mpurate=${mpurate} " \
 133                 "${video_mode} " \
 134                 "${network_setting} " \
 135                 "root=${nandroot} " \
 136                 "rootfstype=${nandrootfstype} "\
 137                 "${extra_options}\0" \
 138         "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 139         "bootscript=echo Running bootscript from mmc ...; " \
 140                 "source ${loadaddr}\0" \
 141         "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 142         "mmcboot=echo Booting from mmc ...; " \
 143                 "run mmcargs; " \
 144                 "bootm ${loadaddr}\0" \
 145         "nandboot=echo Booting from nand ...; " \
 146                 "run nandargs; " \
 147                 "nand read ${loadaddr} 280000 400000; " \
 148                 "bootm ${loadaddr}\0" \
 149
 150 #define CONFIG_BOOTCOMMAND \
 151         "if mmc rescan ${mmcdev}; then " \
 152                 "if run loadbootscript; then " \
 153                         "run bootscript; " \
 154                 "else " \
 155                         "if run loaduimage; then " \
 156                                 "run mmcboot; " \
 157                         "else run nandboot; " \
 158                         "fi; " \
 159                 "fi; " \
 160         "else run nandboot; fi"
 161
 162 /*
 163  * Miscellaneous configurable options
 164  */
 165 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 166 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 167
 168 /* turn on command-line edit/hist/auto */
 169 #define CONFIG_CMDLINE_EDITING
 170 #define CONFIG_AUTO_COMPLETE
 171
 172 /* Print Buffer Size */
 173 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 174                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 175 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 176 /* Boot Argument Buffer Size */
 177 #define CONFIG_SYS_BARGSIZE             (CONFIG_SYS_CBSIZE)
 178
 179 #define CONFIG_SYS_ALT_MEMTEST          1
 180 #define CONFIG_SYS_MEMTEST_START        (0x82000000)            /* memtest */
 181                                                                 /* defaults */
 182 #define CONFIG_SYS_MEMTEST_END          (0x83FFFFFF)            /* 64MB */
 183 #define CONFIG_SYS_MEMTEST_SCRATCH      (0x81000000)    /* dummy address */
 184
 185 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0)     /* default */
 186                                                         /* load address */
 187 #define CONFIG_SYS_TEXT_BASE            0x80008000
 188
 189 /*
 190  * OMAP3 has 12 GP timers, they can be driven by the system clock
 191  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 192  * This rate is divided by a local divisor.
 193  */
 194 #define CONFIG_SYS_TIMERBASE            (OMAP34XX_GPT2)
 195 #define CONFIG_SYS_PTV                  2       /* Divisor: 2^(PTV+1) => 8 */
 196
 197 /*
 198  * Physical Memory Map
 199  */
 200 #define CONFIG_NR_DRAM_BANKS    2       /* CS1 may or may not be populated */
 201 #define PHYS_SDRAM_1            OMAP34XX_SDRC_CS0
 202 #define PHYS_SDRAM_1_SIZE       (32 << 20)      /* at least 32 MiB */
 203 #define PHYS_SDRAM_2            OMAP34XX_SDRC_CS1
 204
 205 /*
 206  * FLASH and environment organization
 207  */
 208
 209 /* **** PISMO SUPPORT *** */
 210 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
 211 #define CONFIG_SYS_FLASH_BASE           NAND_BASE
 212
 213 /* Monitor at start of flash */
 214 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 215 #define CONFIG_SYS_ONENAND_BASE         ONENAND_MAP
 216
 217 #define CONFIG_ENV_IS_IN_NAND           1
 218 #define ONENAND_ENV_OFFSET              0x260000 /* environment starts here */
 219 #define SMNAND_ENV_OFFSET               0x260000 /* environment starts here */
 220
 221 #define CONFIG_SYS_ENV_SECT_SIZE        (128 << 10)
 222 #define CONFIG_ENV_OFFSET               SMNAND_ENV_OFFSET
 223 #define CONFIG_ENV_ADDR                 CONFIG_ENV_OFFSET
 224
 225 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 226 #define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
 227 #define CONFIG_SYS_INIT_RAM_SIZE        0x800
 228 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR + \
 229                                          CONFIG_SYS_INIT_RAM_SIZE - \
 230                                          GENERATED_GBL_DATA_SIZE)
 231
 232 #define CONFIG_OMAP3_SPI
 233
 234 /*
 235  * USB
 236  *
 237  * Currently only EHCI is enabled, the MUSB OTG controller
 238  * is not enabled.
 239  */
 240
 241 /* USB EHCI */
 242 #define CONFIG_USB_EHCI
 243 #define CONFIG_USB_EHCI_OMAP
 244 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO        162
 245
 246 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
 247 #define CONFIG_USB_HOST_ETHER
 248 #define CONFIG_USB_ETHER_SMSC95XX
 249
 250 #define CONFIG_USB_ETHER
 251 #define CONFIG_USB_ETHER_RNDIS
 252
 253 /* Defines for SPL */
 254 #define CONFIG_SPL_FRAMEWORK
 255 #define CONFIG_SPL_NAND_SIMPLE
 256
 257 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      1
 258 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
 259
 260 #define CONFIG_SPL_BOARD_INIT
 261 #define CONFIG_SPL_NAND_BASE
 262 #define CONFIG_SPL_NAND_DRIVERS
 263 #define CONFIG_SPL_NAND_ECC
 264 #define CONFIG_SPL_OMAP3_ID_NAND
 265 #define CONFIG_SPL_LDSCRIPT             "arch/arm/mach-omap2/u-boot-spl.lds"
 266
 267 /* NAND boot config */
 268 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 269 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 270 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
 271 #define CONFIG_SYS_NAND_OOBSIZE         64
 272 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 273 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
 274 /*
 275  * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
 276  * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
 277  */
 278 #define CONFIG_SYS_NAND_ECCPOS          { 2, 3, 4, 5, 6, 7, 8, 9, \
 279                                          10, 11, 12, 13 }
 280 #define CONFIG_SYS_NAND_ECCSIZE         512
 281 #define CONFIG_SYS_NAND_ECCBYTES        3
 282 #define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_HAM1_CODE_HW
 283
 284 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 285 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x80000
 286
 287 #define CONFIG_SPL_TEXT_BASE            0x40200800
 288 #define CONFIG_SPL_MAX_SIZE             (SRAM_SCRATCH_SPACE_ADDR - \
 289                                          CONFIG_SPL_TEXT_BASE)
 290
 291 /*
 292  * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
 293  * older x-loader implementations. And move the BSS area so that it
 294  * doesn't overlap with TEXT_BASE.
 295  */
 296 #define CONFIG_SYS_TEXT_BASE            0x80008000
 297 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
 298 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000         /* 512 KB */
 299
 300 #define CONFIG_SYS_SPL_MALLOC_START     0x80208000
 301 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
 302
 303 #endif /* __CONFIG_H */