include/configs/tao3530.h

   1 /*
   2  * Configuration settings for the TechNexion TAO-3530 SOM
   3  * equipped on Thunder baseboard.
   4  *
   5  * Edward Lin <linuxfae@technexion.com>
   6  * Tapani Utriainen <linuxfae@technexion.com>
   7  *
   8  * Copyright (C) 2013 Stefan Roese <sr@denx.de>
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #ifndef __CONFIG_H
  14 #define __CONFIG_H
  15
  16 /*
  17  * High Level Configuration Options
  18  */
  19 #define CONFIG_OMAP                     /* in a TI OMAP core */
  20
  21 #define CONFIG_OMAP_GPIO
  22
  23 #define CONFIG_SDRC                     /* Has an SDRC controller */
  24
  25 #include <asm/arch/cpu.h>               /* get chip and board defs */
  26 #include <asm/arch/omap.h>
  27
  28 /* Clock Defines */
  29 #define V_OSCK                  26000000        /* Clock output from T2 */
  30 #define V_SCLK                  (V_OSCK >> 1)
  31
  32 #define CONFIG_MISC_INIT_R
  33
  34 #define CONFIG_CMDLINE_TAG
  35 #define CONFIG_SETUP_MEMORY_TAGS
  36 #define CONFIG_INITRD_TAG
  37 #define CONFIG_REVISION_TAG
  38
  39 /*
  40  * Size of malloc() pool
  41  */
  42 #define CONFIG_SYS_MALLOC_LEN           (4 << 20)
  43 #define CONFIG_ENV_SIZE                 (128 << 10)     /* 128 KiB sector */
  44
  45 /*
  46  * Hardware drivers
  47  */
  48
  49 /*
  50  * NS16550 Configuration
  51  */
  52 #define V_NS16550_CLK                   48000000        /* 48MHz (APLL96/2) */
  53
  54 #define CONFIG_SYS_NS16550_SERIAL
  55 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  56 #define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
  57
  58 /*
  59  * select serial console configuration
  60  */
  61 #define CONFIG_CONS_INDEX               3
  62 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
  63
  64 /* allow to overwrite serial and ethaddr */
  65 #define CONFIG_ENV_OVERWRITE
  66 #define CONFIG_BAUDRATE                 115200
  67
  68 /* GPIO banks */
  69 #define CONFIG_OMAP3_GPIO_2             /* GPIO32 ..63  is in GPIO bank 2 */
  70 #define CONFIG_OMAP3_GPIO_3             /* GPIO64 ..95  is in GPIO bank 3 */
  71 #define CONFIG_OMAP3_GPIO_4             /* GPIO96 ..127 is in GPIO bank 4 */
  72 #define CONFIG_OMAP3_GPIO_5             /* GPIO128..159 is in GPIO bank 5 */
  73 #define CONFIG_OMAP3_GPIO_6             /* GPIO160..191 is in GPIO bank 6 */
  74
  75 /* commands to include */
  76 #define CONFIG_CMD_MTDPARTS     /* Enable MTD parts commands */
  77 #define CONFIG_MTD_DEVICE       /* needed for mtdparts commands */
  78 #define MTDIDS_DEFAULT                  "nand0=nand"
  79 #define MTDPARTS_DEFAULT                "mtdparts=nand:512k(x-loader),"\
  80                                         "1920k(u-boot),128k(u-boot-env),"\
  81                                         "4m(kernel),-(fs)"
  82
  83 #define CONFIG_CMD_NAND         /* NAND support                 */
  84
  85 #define CONFIG_SYS_I2C
  86 #define CONFIG_SYS_I2C_OMAP34XX
  87 #define CONFIG_SYS_OMAP24_I2C_SPEED     100000
  88 #define CONFIG_SYS_OMAP24_I2C_SLAVE     1
  89 #define CONFIG_I2C_MULTI_BUS
  90
  91 /*
  92  * TWL4030
  93  */
  94 #define CONFIG_TWL4030_POWER
  95 #define CONFIG_TWL4030_LED
  96
  97 /*
  98  * Board NAND Info.
  99  */
 100 #define CONFIG_NAND_OMAP_GPMC
 101 #define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
 102                                                         /* to access nand */
 103 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
 104                                                         /* to access nand at */
 105                                                         /* CS0 */
 106
 107 #define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of NAND */
 108                                                         /* devices */
 109 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
 110 /* Environment information */
 111
 112 #define CONFIG_EXTRA_ENV_SETTINGS \
 113         "loadaddr=0x82000000\0" \
 114         "console=ttyO2,115200n8\0" \
 115         "mpurate=600\0" \
 116         "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \
 117         "tv_mode=omapfb.mode=tv:ntsc\0" \
 118         "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \
 119         "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \
 120         "extra_options= \0" \
 121         "mmcdev=0\0" \
 122         "mmcroot=/dev/mmcblk0p2 rw\0" \
 123         "mmcrootfstype=ext3 rootwait\0" \
 124         "nandroot=ubi0:rootfs ubi.mtd=4\0" \
 125         "nandrootfstype=ubifs\0" \
 126         "mmcargs=setenv bootargs console=${console} " \
 127                 "mpurate=${mpurate} " \
 128                 "${video_mode} " \
 129                 "root=${mmcroot} " \
 130                 "rootfstype=${mmcrootfstype} " \
 131                 "${extra_options}\0" \
 132         "nandargs=setenv bootargs console=${console} " \
 133                 "mpurate=${mpurate} " \
 134                 "${video_mode} " \
 135                 "${network_setting} " \
 136                 "root=${nandroot} " \
 137                 "rootfstype=${nandrootfstype} "\
 138                 "${extra_options}\0" \
 139         "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 140         "bootscript=echo Running bootscript from mmc ...; " \
 141                 "source ${loadaddr}\0" \
 142         "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 143         "mmcboot=echo Booting from mmc ...; " \
 144                 "run mmcargs; " \
 145                 "bootm ${loadaddr}\0" \
 146         "nandboot=echo Booting from nand ...; " \
 147                 "run nandargs; " \
 148                 "nand read ${loadaddr} 280000 400000; " \
 149                 "bootm ${loadaddr}\0" \
 150
 151 #define CONFIG_BOOTCOMMAND \
 152         "if mmc rescan ${mmcdev}; then " \
 153                 "if run loadbootscript; then " \
 154                         "run bootscript; " \
 155                 "else " \
 156                         "if run loaduimage; then " \
 157                                 "run mmcboot; " \
 158                         "else run nandboot; " \
 159                         "fi; " \
 160                 "fi; " \
 161         "else run nandboot; fi"
 162
 163 /*
 164  * Miscellaneous configurable options
 165  */
 166 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 167 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 168
 169 /* turn on command-line edit/hist/auto */
 170 #define CONFIG_CMDLINE_EDITING
 171 #define CONFIG_COMMAND_HISTORY
 172 #define CONFIG_AUTO_COMPLETE
 173
 174 /* Print Buffer Size */
 175 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 176                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 177 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 178 /* Boot Argument Buffer Size */
 179 #define CONFIG_SYS_BARGSIZE             (CONFIG_SYS_CBSIZE)
 180
 181 #define CONFIG_SYS_ALT_MEMTEST          1
 182 #define CONFIG_SYS_MEMTEST_START        (0x82000000)            /* memtest */
 183                                                                 /* defaults */
 184 #define CONFIG_SYS_MEMTEST_END          (0x83FFFFFF)            /* 64MB */
 185 #define CONFIG_SYS_MEMTEST_SCRATCH      (0x81000000)    /* dummy address */
 186
 187 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0)     /* default */
 188                                                         /* load address */
 189 #define CONFIG_SYS_TEXT_BASE            0x80008000
 190
 191 /*
 192  * OMAP3 has 12 GP timers, they can be driven by the system clock
 193  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 194  * This rate is divided by a local divisor.
 195  */
 196 #define CONFIG_SYS_TIMERBASE            (OMAP34XX_GPT2)
 197 #define CONFIG_SYS_PTV                  2       /* Divisor: 2^(PTV+1) => 8 */
 198
 199 /*
 200  * Stack sizes
 201  *
 202  * The stack sizes are set up in start.S using the settings below
 203  */
 204 #define CONFIG_STACKSIZE        (128 << 10)     /* regular stack 128 KiB */
 205
 206 /*
 207  * Physical Memory Map
 208  */
 209 #define CONFIG_NR_DRAM_BANKS    2       /* CS1 may or may not be populated */
 210 #define PHYS_SDRAM_1            OMAP34XX_SDRC_CS0
 211 #define PHYS_SDRAM_1_SIZE       (32 << 20)      /* at least 32 MiB */
 212 #define PHYS_SDRAM_2            OMAP34XX_SDRC_CS1
 213
 214 /*
 215  * FLASH and environment organization
 216  */
 217
 218 /* **** PISMO SUPPORT *** */
 219 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
 220 #define CONFIG_SYS_FLASH_BASE           NAND_BASE
 221
 222 /* Monitor at start of flash */
 223 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 224 #define CONFIG_SYS_ONENAND_BASE         ONENAND_MAP
 225
 226 #define CONFIG_ENV_IS_IN_NAND           1
 227 #define ONENAND_ENV_OFFSET              0x260000 /* environment starts here */
 228 #define SMNAND_ENV_OFFSET               0x260000 /* environment starts here */
 229
 230 #define CONFIG_SYS_ENV_SECT_SIZE        (128 << 10)
 231 #define CONFIG_ENV_OFFSET               SMNAND_ENV_OFFSET
 232 #define CONFIG_ENV_ADDR                 CONFIG_ENV_OFFSET
 233
 234 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 235 #define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
 236 #define CONFIG_SYS_INIT_RAM_SIZE        0x800
 237 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR + \
 238                                          CONFIG_SYS_INIT_RAM_SIZE - \
 239                                          GENERATED_GBL_DATA_SIZE)
 240
 241 #define CONFIG_OMAP3_SPI
 242
 243 /*
 244  * USB
 245  *
 246  * Currently only EHCI is enabled, the MUSB OTG controller
 247  * is not enabled.
 248  */
 249
 250 /* USB EHCI */
 251 #define CONFIG_USB_EHCI
 252 #define CONFIG_USB_EHCI_OMAP
 253 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO        162
 254
 255 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
 256 #define CONFIG_USB_HOST_ETHER
 257 #define CONFIG_USB_ETHER_SMSC95XX
 258
 259 #define CONFIG_USB_ETHER
 260 #define CONFIG_USB_ETHER_RNDIS
 261
 262 /* Defines for SPL */
 263 #define CONFIG_SPL_FRAMEWORK
 264 #define CONFIG_SPL_NAND_SIMPLE
 265
 266 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      1
 267 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
 268
 269 #define CONFIG_SPL_BOARD_INIT
 270 #define CONFIG_SPL_NAND_BASE
 271 #define CONFIG_SPL_NAND_DRIVERS
 272 #define CONFIG_SPL_NAND_ECC
 273 #define CONFIG_SPL_OMAP3_ID_NAND
 274 #define CONFIG_SPL_LDSCRIPT             "arch/arm/mach-omap2/u-boot-spl.lds"
 275
 276 /* NAND boot config */
 277 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 278 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 279 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
 280 #define CONFIG_SYS_NAND_OOBSIZE         64
 281 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 282 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
 283 /*
 284  * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
 285  * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
 286  */
 287 #define CONFIG_SYS_NAND_ECCPOS          { 2, 3, 4, 5, 6, 7, 8, 9, \
 288                                          10, 11, 12, 13 }
 289 #define CONFIG_SYS_NAND_ECCSIZE         512
 290 #define CONFIG_SYS_NAND_ECCBYTES        3
 291 #define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_HAM1_CODE_HW
 292
 293 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 294 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x80000
 295
 296 #define CONFIG_SPL_TEXT_BASE            0x40200800
 297 #define CONFIG_SPL_MAX_SIZE             (SRAM_SCRATCH_SPACE_ADDR - \
 298                                          CONFIG_SPL_TEXT_BASE)
 299
 300 /*
 301  * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
 302  * older x-loader implementations. And move the BSS area so that it
 303  * doesn't overlap with TEXT_BASE.
 304  */
 305 #define CONFIG_SYS_TEXT_BASE            0x80008000
 306 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
 307 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000         /* 512 KB */
 308
 309 #define CONFIG_SYS_SPL_MALLOC_START     0x80208000
 310 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
 311
 312 #endif /* __CONFIG_H */