include/configs/uc101.h

   1 /*
   2  * (C) Copyright 2003-2006
   3  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 /*
  28  * High Level Configuration Options
  29  * (easy to change)
  30  */
  31
  32 #define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU               */
  33 #define CONFIG_MPC5200          1       /* (more precisely an MPC5200 CPU)      */
  34 #define CONFIG_UC101            1       /* UC101 board                  */
  35
  36 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000 /* ... running at 33.000000MHz         */
  37
  38 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH     */
  39 #define BOOTFLAG_WARM           0x02    /* Software reboot                      */
  40
  41 #define CONFIG_BOARD_EARLY_INIT_R
  42
  43 #define CONFIG_HIGH_BATS        1       /* High BATs supported                  */
  44
  45 /*
  46  * Serial console configuration
  47  */
  48 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1   */
  49 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps    */
  50 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
  51
  52 /* Partitions */
  53 #define CONFIG_DOS_PARTITION
  54
  55
  56 /*
  57  * BOOTP options
  58  */
  59 #define CONFIG_BOOTP_BOOTFILESIZE
  60 #define CONFIG_BOOTP_BOOTPATH
  61 #define CONFIG_BOOTP_GATEWAY
  62 #define CONFIG_BOOTP_HOSTNAME
  63
  64
  65 /*
  66  * Command line configuration.
  67  */
  68 #include <config_cmd_default.h>
  69
  70 #define CONFIG_CMD_DATE
  71 #define CONFIG_CMD_DISPLAY
  72 #define CONFIG_CMD_DHCP
  73 #define CONFIG_CMD_PING
  74 #define CONFIG_CMD_EEPROM
  75 #define CONFIG_CMD_I2C
  76 #define CONFIG_CMD_DTT
  77 #define CONFIG_CMD_IDE
  78 #define CONFIG_CMD_FAT
  79 #define CONFIG_CMD_NFS
  80 #define CONFIG_CMD_MII
  81 #define CONFIG_CMD_SNTP
  82
  83
  84 #define CONFIG_TIMESTAMP        1       /* Print image info with timestamp */
  85
  86 #if (TEXT_BASE == 0xFFF00000) /* Boot low */
  87 #   define CONFIG_SYS_LOWBOOT           1
  88 #endif
  89
  90 /*
  91  * Autobooting
  92  */
  93 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
  94
  95 #define CONFIG_PREBOOT  "echo;" \
  96         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  97         "echo"
  98
  99 #undef  CONFIG_BOOTARGS
 100
 101 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 102         "netdev=eth0\0"                                                 \
 103         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 104                 "nfsroot=${serverip}:${rootpath}\0"                     \
 105         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 106         "addwdt=setenv bootargs ${bootargs} wdt=off"                    \
 107         "addip=setenv bootargs ${bootargs} "                            \
 108                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 109                 ":${hostname}:${netdev}:off panic=1\0"                  \
 110         "flash_nfs=run nfsargs addip;"                                  \
 111                 "bootm ${kernel_addr}\0"                                \
 112         "net_nfs=tftp 300000 ${bootfile};run nfsargs addip addwdt;bootm\0" \
 113         "rootpath=/opt/eldk/ppc_82xx\0"                                 \
 114         ""
 115
 116 #define CONFIG_BOOTCOMMAND      "run net_nfs"
 117
 118 #define CONFIG_MISC_INIT_R      1
 119
 120 /*
 121  * IPB Bus clocking configuration.
 122  */
 123 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK         /* define for 133MHz speed */
 124
 125 /*
 126  * I2C configuration
 127  */
 128 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 129 #define CONFIG_SYS_I2C_MODULE           2       /* Select I2C module #1 or #2 */
 130
 131 #define CONFIG_SYS_I2C_SPEED            100000 /* 100 kHz */
 132 #define CONFIG_SYS_I2C_SLAVE            0x7F
 133
 134 /*
 135  * EEPROM configuration
 136  */
 137 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x58
 138 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 139 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 140 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 141
 142 /*
 143  * RTC configuration
 144  */
 145 #define CONFIG_RTC_PCF8563
 146 #define CONFIG_SYS_I2C_RTC_ADDR         0x51
 147
 148 /* I2C SYSMON (LM75) */
 149 #define CONFIG_DTT_LM81                 1       /* ON Semi's LM75               */
 150 #define CONFIG_DTT_SENSORS              {0}     /* Sensor addresses             */
 151 #define CONFIG_SYS_DTT_MAX_TEMP         70
 152 #define CONFIG_SYS_DTT_LOW_TEMP         -30
 153 #define CONFIG_SYS_DTT_HYSTERESIS               3
 154
 155 /*
 156  * Flash configuration
 157  */
 158 #define CONFIG_SYS_FLASH_BASE           0xFF800000
 159
 160 #define CONFIG_SYS_FLASH_SIZE           0x00800000 /* 8 MByte */
 161 #define CONFIG_SYS_MAX_FLASH_SECT       140     /* max num of sects on one chip */
 162
 163 #define CONFIG_ENV_ADDR         (TEXT_BASE+0x40000) /* second sector */
 164 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of flash banks
 165                                            (= chip selects) */
 166 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Flash Erase Timeout (in ms)  */
 167 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (in ms)  */
 168
 169 #define CONFIG_FLASH_CFI_DRIVER
 170 #define CONFIG_SYS_FLASH_CFI
 171 #define CONFIG_SYS_FLASH_EMPTY_INFO
 172 #define CONFIG_SYS_FLASH_CFI_AMD_RESET
 173
 174 /*
 175  * Environment settings
 176  */
 177 #define CONFIG_ENV_IS_IN_FLASH  1
 178 #define CONFIG_ENV_SIZE         0x4000
 179 #define CONFIG_ENV_SECT_SIZE    0x10000
 180 #define CONFIG_ENV_OFFSET_REDUND   (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
 181 #define CONFIG_ENV_SIZE_REDUND     (CONFIG_ENV_SIZE)
 182
 183 /*
 184  * Memory map
 185  */
 186 #define CONFIG_SYS_MBAR         0xF0000000
 187 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 188
 189 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 190 #define CONFIG_SYS_SRAM_BASE            0x80100000      /* CS 1 */
 191 #define CONFIG_SYS_DISPLAY_BASE 0x80600000      /* CS 3 */
 192 #define CONFIG_SYS_IB_MASTER            0xc0510000      /* CS 6 */
 193 #define CONFIG_SYS_IB_EPLD              0xc0500000      /* CS 7 */
 194
 195 /* Settings for XLB = 132 MHz */
 196 #define SDRAM_DDR        1
 197 #define SDRAM_MODE      0x018D0000
 198 #define SDRAM_EMODE     0x40090000
 199 #define SDRAM_CONTROL   0x714f0f00
 200 #define SDRAM_CONFIG1   0x73722930
 201 #define SDRAM_CONFIG2   0x47770000
 202 #define SDRAM_TAPDELAY  0x10000000
 203
 204 /* SRAM */
 205 #define SRAM_BASE               CONFIG_SYS_SRAM_BASE    /* SRAM base address    */
 206 #define SRAM_LEN                0x1fffff
 207 #define SRAM_END                (SRAM_BASE + SRAM_LEN)
 208
 209 /* Use ON-Chip SRAM until RAM will be available */
 210 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 211 #ifdef CONFIG_POST
 212 /* preserve space for the post_word at end of on-chip SRAM */
 213 #define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
 214 #else
 215 #define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
 216 #endif
 217
 218
 219 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* size in bytes reserved for initial data */
 220 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 221 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 222
 223 #define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
 224 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 225 #   define CONFIG_SYS_RAMBOOT           1
 226 #endif
 227
 228 #define CONFIG_SYS_MONITOR_LEN          (192 << 10)     /* Reserve 192 kB for Monitor   */
 229 #define CONFIG_SYS_MALLOC_LEN           (512 << 10)     /* Reserve 128 kB for malloc()  */
 230 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 231
 232 /*
 233  * Ethernet configuration
 234  */
 235 #define CONFIG_MPC5xxx_FEC      1
 236 #define CONFIG_PHY_ADDR         0x00
 237 #define CONFIG_MII              1
 238
 239 /*
 240  * GPIO configuration
 241  */
 242 #define CONFIG_SYS_GPS_PORT_CONFIG      0x4d558044
 243
 244 /*use  Hardware WDT */
 245 #define CONFIG_HW_WATCHDOG
 246
 247 /*
 248  * Miscellaneous configurable options
 249  */
 250 #define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
 251 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt   */
 252 #if defined(CONFIG_CMD_KGDB)
 253 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
 254 #else
 255 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
 256 #endif
 257 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 258 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 259 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 260
 261 /* Enable an alternate, more extensive memory test */
 262 #define CONFIG_SYS_ALT_MEMTEST
 263
 264 #define CONFIG_SYS_MEMTEST_START        0x00300000      /* memtest works on */
 265 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 3 ... 15 MB in DRAM  */
 266
 267 #define CONFIG_SYS_LOAD_ADDR            0x300000        /* default load address */
 268
 269 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 270
 271 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs                     */
 272 #if defined(CONFIG_CMD_KGDB)
 273 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value        */
 274 #endif
 275
 276 /*
 277  * Enable loopw command.
 278  */
 279 #define CONFIG_LOOPW
 280
 281 /*
 282  * Various low-level settings
 283  */
 284 #if defined(CONFIG_MPC5200)
 285 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 286 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 287 #else
 288 #define CONFIG_SYS_HID0_INIT            0
 289 #define CONFIG_SYS_HID0_FINAL           0
 290 #endif
 291
 292 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 293 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 294 #define CONFIG_SYS_BOOTCS_CFG           0x00045D00
 295 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 296 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 297
 298 /* 8Mbit SRAM @0x80100000 */
 299 #define CONFIG_SYS_CS1_START            CONFIG_SYS_SRAM_BASE
 300 #define CONFIG_SYS_CS1_SIZE             0x00200000
 301 #define CONFIG_SYS_CS1_CFG              0x21D00
 302
 303 /* Display H1, Status Inputs, EPLD @0x80600000 8 Bit */
 304 #define CONFIG_SYS_CS3_START            CONFIG_SYS_DISPLAY_BASE
 305 #define CONFIG_SYS_CS3_SIZE             0x00000100
 306 #define CONFIG_SYS_CS3_CFG              0x00081802
 307
 308 /* Interbus Master 16 Bit */
 309 #define CONFIG_SYS_CS6_START            CONFIG_SYS_IB_MASTER
 310 #define CONFIG_SYS_CS6_SIZE             0x00010000
 311 #define CONFIG_SYS_CS6_CFG              0x00FF3500
 312
 313 /* Interbus EPLD 8 Bit */
 314 #define CONFIG_SYS_CS7_START            CONFIG_SYS_IB_EPLD
 315 #define CONFIG_SYS_CS7_SIZE             0x00010000
 316 #define CONFIG_SYS_CS7_CFG              0x00081800
 317
 318 #define CONFIG_SYS_CS_BURST             0x00000000
 319 #define CONFIG_SYS_CS_DEADCYCLE 0x33333333
 320
 321 /*-----------------------------------------------------------------------
 322  * IDE/ATA stuff Supports IDE harddisk
 323  *-----------------------------------------------------------------------
 324  */
 325
 326 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 327
 328 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 329 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 330
 331 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 332 #define CONFIG_SYS_IDE_MAXDEVICE        2       /* max. 2 drives per IDE bus    */
 333
 334 #define CONFIG_IDE_PREINIT      1
 335
 336 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 337
 338 #define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
 339
 340 /* Offset for data I/O                  */
 341 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x0060)
 342
 343 /* Offset for normal register accesses  */
 344 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
 345
 346 /* Offset for alternate registers       */
 347 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x005C)
 348
 349 /* Interval between registers                                                */
 350 #define CONFIG_SYS_ATA_STRIDE          4
 351
 352 #define CONFIG_ATAPI            1
 353
 354 /*---------------------------------------------------------------------*/
 355 /* Display addresses                                                   */
 356 /*---------------------------------------------------------------------*/
 357 #define CONFIG_SYS_DISP_CHR_RAM (CONFIG_SYS_DISPLAY_BASE + 0x38)
 358 #define CONFIG_SYS_DISP_CWORD           (CONFIG_SYS_DISPLAY_BASE + 0x30)
 359
 360 #endif /* __CONFIG_H */