include/configs/v38b.h

   1 /*
   2  * (C) Copyright 2003-2006 Wolfgang Denk, DENX Software Engineering,
   3  * wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this project.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the Free
   9  * Software Foundation; either version 2 of the License, or (at your option)
  10  * any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  15  * for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, write to the Free Software Foundation, Inc., 59
  19  * Temple Place, Suite 330, Boston, MA 02111-1307 USA
  20  */
  21
  22 #ifndef __CONFIG_H
  23 #define __CONFIG_H
  24
  25 /*
  26  * High Level Configuration Options
  27  * (easy to change)
  28  */
  29 #define CONFIG_MPC5xxx                  1       /* This is an MPC5xxx CPU */
  30 #define CONFIG_MPC5200                  1       /* This is an MPC5200 CPU */
  31 #define CONFIG_V38B                     1       /* ...on V38B board */
  32 #define CFG_MPC5XXX_CLKIN       33000000        /* ...running at 33.000000MHz */
  33
  34 #define CONFIG_RTC_PCF8563              1       /* has PCF8563 RTC */
  35 #define CONFIG_MPC5200_DDR              1       /* has DDR SDRAM */
  36
  37 #undef CONFIG_HW_WATCHDOG                       /* don't use watchdog */
  38
  39 #define CONFIG_NETCONSOLE               1
  40
  41 #define CONFIG_BOARD_EARLY_INIT_R       1       /* do board-specific init */
  42 #define CONFIG_BOARD_EARLY_INIT_F       1       /* do board-specific init */
  43
  44 #define CFG_XLB_PIPELINING              1       /* gives better performance */
  45
  46 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH  */
  47 #define BOOTFLAG_WARM           0x02    /* Software reboot */
  48
  49 #define CFG_CACHELINE_SIZE      32      /* For MPC5xxx CPUs */
  50 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  51 #  define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value */
  52 #endif
  53
  54 /*
  55  * Serial console configuration
  56  */
  57 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1 */
  58 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps */
  59 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
  60
  61 /*
  62  * DDR
  63  */
  64 #define SDRAM_DDR               1       /* is DDR */
  65 /* Settings for XLB = 132 MHz */
  66 #define SDRAM_MODE              0x018D0000
  67 #define SDRAM_EMODE             0x40090000
  68 #define SDRAM_CONTROL           0x704f0f00
  69 #define SDRAM_CONFIG1           0x73722930
  70 #define SDRAM_CONFIG2           0x47770000
  71 #define SDRAM_TAPDELAY          0x10000000
  72
  73 /*
  74  * PCI - no suport
  75  */
  76 #undef CONFIG_PCI
  77
  78 /*
  79  * Partitions
  80  */
  81 #define CONFIG_MAC_PARTITION    1
  82 #define CONFIG_DOS_PARTITION    1
  83
  84 /*
  85  * USB
  86  */
  87 #define CONFIG_USB_OHCI
  88 #define CONFIG_USB_STORAGE
  89 #define CONFIG_USB_CLOCK        0x0001BBBB
  90 #define CONFIG_USB_CONFIG       0x00001000
  91
  92 /*
  93  * Supported commands
  94  */
  95 #define CONFIG_COMMANDS         (CONFIG_CMD_DFL | \
  96                                  CFG_CMD_FAT    | \
  97                                  CFG_CMD_I2C    | \
  98                                  CFG_CMD_IDE    | \
  99                                  CFG_CMD_PING   | \
 100                                  CFG_CMD_DHCP   | \
 101                                  CFG_CMD_DIAG   | \
 102                                  CFG_CMD_IRQ    | \
 103                                  CFG_CMD_JFFS2  | \
 104                                  CFG_CMD_MII    | \
 105                                  CFG_CMD_SDRAM  | \
 106                                  CFG_CMD_DATE   | \
 107                                  CFG_CMD_USB    | \
 108                                  CFG_CMD_FAT)
 109
 110 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
 111
 112 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 113 #include <cmd_confdefs.h>
 114
 115 /*
 116  * Boot low with 16 MB Flash
 117  */
 118 #define CFG_LOWBOOT             1
 119 #define CFG_LOWBOOT16           1
 120
 121 /*
 122  * Autobooting
 123  */
 124 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds */
 125
 126 #define CONFIG_PREBOOT  "echo;" \
 127         "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
 128         "echo"
 129
 130 #undef CONFIG_BOOTARGS
 131
 132 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 133         "bootcmd=run net_nfs\0"                                         \
 134         "bootdelay=3\0"                                                 \
 135         "baudrate=115200\0"                                             \
 136         "preboot=echo;echo Type \"run flash_nfs\" to mount root "       \
 137                 "filesystem over NFS; echo\0"                           \
 138         "netdev=eth0\0"                                                 \
 139         "ramargs=setenv bootargs root=/dev/ram rw wdt=off \0"           \
 140         "addip=setenv bootargs $(bootargs) "                            \
 141                 "ip=$(ipaddr):$(serverip):$(gatewayip):"                \
 142                 "$(netmask):$(hostname):$(netdev):off panic=1\0"        \
 143         "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0"            \
 144         "flash_self=run ramargs addip;bootm $(kernel_addr) "            \
 145                 "$(ramdisk_addr)\0"                                     \
 146         "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"     \
 147         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 148                 "nfsroot=$(serverip):$(rootpath) wdt=off\0"             \
 149         "hostname=v38b\0"                                               \
 150         "ethact=FEC ETHERNET\0"                                         \
 151         "rootpath=/opt/eldk-3.1.1/ppc_6xx\0"                            \
 152         "update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; "    \
 153                 "cp.b 200000 ff000000 $(filesize);"                     \
 154                 "prot on ff000000 ff03ffff\0"                           \
 155         "load=tftp 200000 $(u-boot)\0"                                  \
 156         "netmask=255.255.0.0\0"                                         \
 157         "ipaddr=192.168.160.18\0"                                       \
 158         "serverip=192.168.1.1\0"                                        \
 159         "ethaddr=00:e0:ee:00:05:2e\0"                                   \
 160         "bootfile=/tftpboot/v38b/uImage\0"                              \
 161         "u-boot=/tftpboot/v38b/u-boot.bin\0"                            \
 162         ""
 163
 164 #define CONFIG_BOOTCOMMAND      "run net_nfs"
 165
 166 #if defined(CONFIG_MPC5200)
 167 /*
 168  * IPB Bus clocking configuration.
 169  */
 170 #undef CFG_IPBCLK_EQUALS_XLBCLK                 /* define for 133MHz speed */
 171 #endif
 172
 173 /*
 174  * I2C configuration
 175  */
 176 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 177 #define CFG_I2C_MODULE          2       /* Select I2C module #1 or #2 */
 178 #define CFG_I2C_SPEED           100000  /* 100 kHz */
 179 #define CFG_I2C_SLAVE           0x7F
 180
 181 /*
 182  * EEPROM configuration
 183  */
 184 #define CFG_I2C_EEPROM_ADDR             0x50    /* 1010000x */
 185 #define CFG_I2C_EEPROM_ADDR_LEN         1
 186 #define CFG_EEPROM_PAGE_WRITE_BITS      3
 187 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  70
 188
 189 /*
 190  * RTC configuration
 191  */
 192 #define CFG_I2C_RTC_ADDR                0x51
 193
 194 /*
 195  * Flash configuration - use CFI driver
 196  */
 197 #define CFG_FLASH_CFI           1               /* Flash is CFI conformant */
 198 #define CFG_FLASH_CFI_DRIVER    1               /* Use the common driver */
 199 #define CFG_FLASH_CFI_AMD_RESET 1
 200 #define CFG_FLASH_BASE          0xFF000000
 201 #define CFG_MAX_FLASH_BANKS     1               /* max num of flash banks */
 202 #define CFG_FLASH_BANKS_LIST    { CFG_FLASH_BASE }
 203 #define CFG_FLASH_SIZE          0x01000000      /* 16 MiB */
 204 #define CFG_MAX_FLASH_SECT      256             /* max num of sects on one chip */
 205 #define CFG_FLASH_USE_BUFFER_WRITE      1       /* flash write speed-up */
 206
 207 /*
 208  * Environment settings
 209  */
 210 #define CFG_ENV_IS_IN_FLASH     1
 211 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + 0x00040000)
 212 #define CFG_ENV_SIZE            0x10000
 213 #define CFG_ENV_SECT_SIZE       0x10000
 214 #define CONFIG_ENV_OVERWRITE    1
 215
 216 /*
 217  * Memory map
 218  */
 219 #define CFG_MBAR                0xF0000000
 220 #define CFG_SDRAM_BASE          0x00000000
 221 #define CFG_DEFAULT_MBAR        0x80000000
 222
 223 /* Use SRAM until RAM will be available */
 224 #define CFG_INIT_RAM_ADDR       MPC5XXX_SRAM
 225 #define CFG_INIT_RAM_END        MPC5XXX_SRAM_SIZE       /* End of used area in DPRAM */
 226
 227 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
 228 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 229 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 230
 231 #define CFG_MONITOR_BASE        TEXT_BASE
 232 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 233 #   define CFG_RAMBOOT          1
 234 #endif
 235
 236 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256kB for Monitor */
 237 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128kB for malloc() */
 238 #define CFG_BOOTMAPSZ           (8 << 20)       /* Linux initial memory map */
 239
 240 /*
 241  * Ethernet configuration
 242  */
 243 #define CONFIG_MPC5xxx_FEC      1
 244 #define CONFIG_PHY_ADDR         0x00
 245 #define CONFIG_MII              1
 246
 247 /*
 248  * GPIO configuration
 249  */
 250 #define CFG_GPS_PORT_CONFIG     0x90001404
 251
 252 /*
 253  * Miscellaneous configurable options
 254  */
 255 #define CFG_LONGHELP                    /* undef to save memory */
 256 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt */
 257 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 258 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size */
 259 #else
 260 #define CFG_CBSIZE              256     /* Console I/O Buffer Size */
 261 #endif
 262 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)   /* Print Buffer Size */
 263 #define CFG_MAXARGS             16              /* max number of command args */
 264 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size */
 265
 266 #define CFG_MEMTEST_START       0x00100000      /* memtest works on */
 267 #define CFG_MEMTEST_END         0x00f00000      /* 1 ... 15 MB in DRAM */
 268
 269 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 270
 271 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 272
 273 /*
 274  * Various low-level settings
 275  */
 276 #define CFG_HID0_INIT           HID0_ICE | HID0_ICFI
 277 #define CFG_HID0_FINAL          HID0_ICE
 278
 279 #define CFG_BOOTCS_START        CFG_FLASH_BASE
 280 #define CFG_BOOTCS_SIZE         CFG_FLASH_SIZE
 281 #define CFG_BOOTCS_CFG          0x00047801
 282 #define CFG_CS0_START           CFG_FLASH_BASE
 283 #define CFG_CS0_SIZE            CFG_FLASH_SIZE
 284
 285 #define CFG_CS_BURST            0x00000000
 286 #define CFG_CS_DEADCYCLE        0x33333333
 287
 288 #define CFG_RESET_ADDRESS       0xff000000
 289
 290 /*
 291  * IDE/ATA (supports IDE harddisk)
 292  */
 293 #undef CONFIG_IDE_8xx_PCCARD            /* Don't use IDE with PC Card Adapter */
 294 #undef CONFIG_IDE_8xx_DIRECT            /* Direct IDE not supported */
 295 #undef CONFIG_IDE_LED                   /* LED for ide not supported */
 296
 297 #define CONFIG_IDE_RESET                /* reset for ide supported */
 298 #define CONFIG_IDE_PREINIT
 299
 300 #define CFG_IDE_MAXBUS          1       /* max. 1 IDE bus */
 301 #define CFG_IDE_MAXDEVICE       1       /* max. 1 drive per IDE bus */
 302
 303 #define CFG_ATA_IDE0_OFFSET     0x0000
 304
 305 #define CFG_ATA_BASE_ADDR       MPC5XXX_ATA
 306
 307 #define CFG_ATA_DATA_OFFSET     (0x0060)        /* data I/O offset */
 308
 309 #define CFG_ATA_REG_OFFSET      (CFG_ATA_DATA_OFFSET)   /* normal register accesses offset */
 310
 311 #define CFG_ATA_ALT_OFFSET      (0x005C)        /* alternate registers offset */
 312
 313 #define CFG_ATA_STRIDE          4               /* Interval between registers */
 314
 315 /*
 316  * Status LED
 317  */
 318 #define  CONFIG_STATUS_LED              /* Status LED enabled */
 319 #define  CONFIG_BOARD_SPECIFIC_LED      /* version has board specific leds */
 320
 321 #define CFG_LED_BASE    MPC5XXX_GPT7_ENABLE     /* Timer 7 GPIO */
 322 #ifndef __ASSEMBLY__
 323 typedef unsigned int led_id_t;
 324
 325 #define __led_toggle(_msk) \
 326         do { \
 327                 *((volatile long *) (CFG_LED_BASE)) ^= (_msk); \
 328         } while(0)
 329
 330 #define __led_set(_msk, _st) \
 331         do { \
 332                 if ((_st)) \
 333                         *((volatile long *) (CFG_LED_BASE)) &= ~(_msk); \
 334                 else \
 335                         *((volatile long *) (CFG_LED_BASE)) |= (_msk); \
 336         } while(0)
 337
 338 #define __led_init(_msk, st) \
 339         do { \
 340                 *((volatile long *) (CFG_LED_BASE)) |= 0x34; \
 341         } while(0)
 342 #endif /* __ASSEMBLY__ */
 343
 344 #endif /* __CONFIG_H */