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1 /*
2 * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl
3 *
4 * Configuation settings for the TI OMAP VoiceBlue board.
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 #ifndef __CONFIG_H
25 #define __CONFIG_H
26
27 #include <configs/omap1510.h>
28
29 /*
30 * High Level Configuration Options
31 * (easy to change)
32 */
33 #define CONFIG_ARM925T 1 /* This is an arm925t CPU */
34 #define CONFIG_OMAP 1 /* in a TI OMAP core */
35 #define CONFIG_OMAP1510 1 /* which is in a 5910 */
36
37 /* Input clock of PLL */
38 #define CONFIG_SYS_CLK_FREQ 150000000 /* 150MHz input clock */
39 #define CONFIG_XTAL_FREQ 12000000
40
41 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
42
43 #define CONFIG_MISC_INIT_R /* There is nothing to really init */
44 #define BOARD_LATE_INIT /* but we flash the LEDs here */
45
46 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
47 #define CONFIG_SETUP_MEMORY_TAGS 1
48 #define CONFIG_INITRD_TAG 1
49
50 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
51
52 /*
53 * Physical Memory Map
54 */
55 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
56 #define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
57 #define PHYS_SDRAM_1_SIZE SZ_64M
58
59 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
60 #define PHYS_FLASH_2 0x0c000000
61
62 #define CFG_LOAD_ADDR PHYS_SDRAM_1 + 0x400000 /* default load address */
63
64 /*
65 * FLASH organization
66 */
67 #define CFG_FLASH_CFI /* Flash is CFI conformant */
68 #define CFG_FLASH_CFI_DRIVER /* Use the common driver */
69 #define CFG_MAX_FLASH_BANKS 1
70 #ifdef VOICEBLUE_SMALL_FLASH
71 #define CFG_FLASH_BANKS_LIST { PHYS_FLASH_2 }
72 #else
73 #define CFG_FLASH_BANKS_LIST { PHYS_FLASH_1 }
74 #endif
75
76 /* FIXME: Does not work on AMD flash */
77 /* #define CFG_FLASH_USE_BUFFER_WRITE 1 */ /* use buffered writes (20x faster) */
78 #define CFG_MAX_FLASH_SECT 512 /* max # of sectors on one chip */
79
80 #define CFG_MONITOR_BASE PHYS_FLASH_1
81 #define CFG_MONITOR_LEN SZ_128K
82
83 /*
84 * Environment settings
85 */
86 #ifdef VOICEBLUE_SMALL_FLASH
87 #define CFG_ENV_IS_NOWHERE
88 #define CFG_ENV_SIZE SZ_1K
89 #else
90 #define CFG_ENV_IS_IN_FLASH
91 #define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_MONITOR_LEN)
92 #define CFG_ENV_SIZE SZ_8K
93 #define CFG_ENV_SECT_SIZE SZ_64K
94 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
95 #define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
96
97 #define CONFIG_ENV_OVERWRITE
98
99 #endif
100
101 /*
102 * Size of malloc() pool and stack
103 */
104 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
105 #ifdef VOICEBLUE_SMALL_FLASH
106 #define CFG_MALLOC_LEN (SZ_64K - CFG_GBL_DATA_SIZE)
107 #define CONFIG_STACKSIZE SZ_8K
108 #define PHYS_SDRAM_1_RESERVED 0
109 #else
110 #define CFG_MALLOC_LEN SZ_4M
111 #define CONFIG_STACKSIZE SZ_1M
112 #define PHYS_SDRAM_1_RESERVED (CFG_MONITOR_LEN + CFG_MALLOC_LEN + CONFIG_STACKSIZE)
113 #endif
114
115 /*
116 * Hardware drivers
117 */
118 #define CONFIG_DRIVER_SMC91111
119 #define CONFIG_SMC91111_BASE 0x08000300
120
121 /*
122 * NS16550 Configuration
123 */
124 #define CFG_NS16550
125 #define CFG_NS16550_SERIAL
126 #define CFG_NS16550_REG_SIZE (-4)
127 #define CFG_NS16550_CLK (CONFIG_XTAL_FREQ) /* can be 12M/32Khz or 48Mhz */
128 #define CFG_NS16550_COM1 OMAP1510_UART1_BASE /* uart1 */
129
130 #define CONFIG_CONS_INDEX 1
131 #define CONFIG_BAUDRATE 115200
132 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
133
134
135 /*
136 * Command line configuration.
137 */
138 #include <config_cmd_default.h>
139
140 #define CONFIG_CMD_BDI
141 #define CONFIG_CMD_LOADB
142 #define CONFIG_CMD_IMI
143 #define CONFIG_CMD_FLASH
144 #define CONFIG_CMD_MEMORY
145 #define CONFIG_CMD_NET
146 #define CONFIG_CMD_BOOTD
147 #define CONFIG_CMD_DHCP
148 #define CONFIG_CMD_PING
149 #define CONFIG_CMD_RUN
150
151 #if !defined(VOICEBLUE_SMALL_FLASH)
152 #define CONFIG_CMD_ENV
153 #define CONFIG_CMD_JFFS2
154 #endif
155
156
157 /*
158 * BOOTP options
159 */
160 #define CONFIG_BOOTP_SUBNETMASK
161 #define CONFIG_BOOTP_GATEWAY
162 #define CONFIG_BOOTP_HOSTNAME
163 #define CONFIG_BOOTP_BOOTPATH
164
165
166 #define CONFIG_LOOPW
167
168 #ifdef VOICEBLUE_SMALL_FLASH
169 #define CONFIG_BOOTDELAY 0
170 #undef CONFIG_BOOTARGS /* the preboot command will set bootargs*/
171 #define CFG_AUTOLOAD "n" /* no autoload */
172 #define CONFIG_PREBOOT "run setup"
173 #define CONFIG_EXTRA_ENV_SETTINGS \
174 "setup=setenv bootargs console=ttyS0,${baudrate} " \
175 "root=/dev/nfs ip=dhcp\0" \
176 "update=erase c000000 c03ffff; " \
177 "cp.b 10400000 c000000 ${filesize}\0"
178 #else
179 #define CONFIG_BOOTDELAY 3
180 #undef CONFIG_BOOTARGS /* boot command will set bootargs */
181 #define CFG_AUTOLOAD "n" /* no autoload */
182 #define CONFIG_BOOTCOMMAND "run nboot"
183 #define CONFIG_PREBOOT "run setup"
184 #define CONFIG_EXTRA_ENV_SETTINGS \
185 "silent=1\0" \
186 "ospart=0\0" \
187 "swapos=no\0" \
188 "setpart=" \
189 "if test $swapos = yes; then " \
190 "if test $ospart -eq 0; then chpart 4; else chpart 3; fi; "\
191 "setenv swapos no; saveenv; " \
192 "else " \
193 "if test $ospart -eq 0; then chpart 3; else chpart 4; fi; "\
194 "fi\0" \
195 "setup=setenv bootargs console=ttyS0,$baudrate " \
196 "mtdparts=$mtdparts\0" \
197 "nfsargs=setenv bootargs $bootargs " \
198 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \
199 "nfsroot=$rootpath root=/dev/nfs\0" \
200 "flashargs=run setpart; setenv bootargs $bootargs " \
201 "root=/dev/mtdblock$partition ro " \
202 "rootfstype=jffs2\0" \
203 "initrdargs=setenv bootargs $bootargs " \
204 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \
205 "fboot=run flashargs; fsload /boot/uImage; bootm\0" \
206 "iboot=bootp; run initrdargs; tftp; bootm\0" \
207 "nboot=bootp; run nfsargs; tftp; bootm\0"
208 #endif
209
210 #ifndef VOICEBLUE_SMALL_FLASH
211 #define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */
212
213 #if 1 /* feel free to disable for development */
214 #define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
215 #define CONFIG_AUTOBOOT_PROMPT "\nVoiceBlue Enterprise - booting...\n"
216 #define CONFIG_AUTOBOOT_DELAY_STR "." /* 1st "password" */
217 #endif
218
219 /*
220 * JFFS2 partitions (mtdparts command line support)
221 */
222 #define CONFIG_JFFS2_CMDLINE
223 #define MTDIDS_DEFAULT "nor0=omapflash.0"
224 #define MTDPARTS_DEFAULT "mtdparts=omapflash.0:128k(uboot),64k(env),64k(r_env),16256k(data1),-(data2)"
225
226 #endif /* VOICEBLUE_SMALL_FLASH */
227
228
229 /*
230 * Miscellaneous configurable options
231 */
232 #ifndef VOICEBLUE_SMALL_FLASH
233 #define CFG_HUSH_PARSER
234 #define CFG_PROMPT_HUSH_PS2 "> "
235 #define CONFIG_AUTO_COMPLETE
236 #endif
237 #define CFG_LONGHELP /* undef to save memory */
238 #define CFG_PROMPT "# " /* Monitor Command Prompt */
239 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
240 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
241 #define CFG_MAXARGS 16 /* max number of command args */
242 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
243
244 #define CFG_MEMTEST_START PHYS_SDRAM_1
245 #define CFG_MEMTEST_END PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - PHYS_SDRAM_1_RESERVED
246
247 #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
248
249 /* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1.
250 * This time is further subdivided by a local divisor.
251 */
252 #define CFG_TIMERBASE OMAP1510_TIMER1_BASE
253 #define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */
254 #define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
255
256 #define OMAP5910_DPLL_DIV 1
257 #define OMAP5910_DPLL_MUL ((CONFIG_SYS_CLK_FREQ * \
258 (1 << OMAP5910_DPLL_DIV)) / CONFIG_XTAL_FREQ)
259
260 #define OMAP5910_ARM_PER_DIV 2 /* CKL/4 */
261 #define OMAP5910_LCD_DIV 2 /* CKL/4 */
262 #define OMAP5910_ARM_DIV 0 /* CKL/1 */
263 #define OMAP5910_DSP_DIV 0 /* CKL/1 */
264 #define OMAP5910_TC_DIV 1 /* CKL/2 */
265 #define OMAP5910_DSP_MMU_DIV 1 /* CKL/2 */
266 #define OMAP5910_ARM_TIM_SEL 1 /* CKL used for MPU timers */
267
268 #define OMAP5910_ARM_EN_CLK 0x03d6 /* 0000 0011 1101 0110b Clock Enable */
269 #define OMAP5910_ARM_CKCTL ((OMAP5910_ARM_PER_DIV) | \
270 (OMAP5910_LCD_DIV << 2) | \
271 (OMAP5910_ARM_DIV << 4) | \
272 (OMAP5910_DSP_DIV << 6) | \
273 (OMAP5910_TC_DIV << 8) | \
274 (OMAP5910_DSP_MMU_DIV << 10) | \
275 (OMAP5910_ARM_TIM_SEL << 12))
276
277 #define VOICEBLUE_LED_REG 0x04030000
278
279 #endif /* __CONFIG_H */