include/configs/work_92105.h

   1 /*
   2  * WORK Microwave work_92105 board configuration file
   3  *
   4  * (C) Copyright 2014  DENX Software Engineering GmbH
   5  * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef __CONFIG_WORK_92105_H__
  11 #define __CONFIG_WORK_92105_H__
  12
  13 /* SoC and board defines */
  14 #include <linux/sizes.h>
  15 #include <asm/arch/cpu.h>
  16
  17 /*
  18  * Define work_92105 machine type by hand -- done only for compatibility
  19  * with original board code
  20  */
  21 #define MACH_TYPE_WORK_92105            736
  22 #define CONFIG_MACH_TYPE                MACH_TYPE_WORK_92105
  23
  24 #define CONFIG_SYS_ICACHE_OFF
  25 #define CONFIG_SYS_DCACHE_OFF
  26 #if !defined(CONFIG_SPL_BUILD)
  27 #define CONFIG_SKIP_LOWLEVEL_INIT
  28 #endif
  29 #define CONFIG_BOARD_EARLY_INIT_R
  30
  31 /* generate LPC32XX-specific SPL image */
  32 #define CONFIG_LPC32XX_SPL
  33
  34 /*
  35  * Memory configurations
  36  */
  37 #define CONFIG_NR_DRAM_BANKS            1
  38 #define CONFIG_SYS_MALLOC_LEN           SZ_1M
  39 #define CONFIG_SYS_SDRAM_BASE           EMC_DYCS0_BASE
  40 #define CONFIG_SYS_SDRAM_SIZE           SZ_128M
  41 #define CONFIG_SYS_TEXT_BASE            0x80100000
  42 #define CONFIG_SYS_MEMTEST_START        (CONFIG_SYS_SDRAM_BASE + SZ_32K)
  43 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_TEXT_BASE - SZ_1M)
  44
  45 #define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE + SZ_32K)
  46
  47 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + SZ_512K \
  48                                          - GENERATED_GBL_DATA_SIZE)
  49
  50 /*
  51  * Serial Driver
  52  */
  53 #define CONFIG_SYS_LPC32XX_UART         5   /* UART5 - NS16550 */
  54 #define CONFIG_BAUDRATE                 115200
  55
  56 /*
  57  * Ethernet Driver
  58  */
  59
  60 #define CONFIG_PHY_SMSC
  61 #define CONFIG_LPC32XX_ETH
  62 #define CONFIG_PHYLIB
  63 #define CONFIG_PHY_ADDR 0
  64 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  65 /* FIXME: remove "Waiting for PHY auto negotiation to complete..." message */
  66
  67 /*
  68  * I2C driver
  69  */
  70
  71 #define CONFIG_SYS_I2C_LPC32XX
  72 #define CONFIG_SYS_I2C
  73 #define CONFIG_SYS_I2C_SPEED 350000
  74
  75 /*
  76  * I2C EEPROM
  77  */
  78
  79 #define CONFIG_CMD_EEPROM
  80 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x56
  81 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  82
  83 /*
  84  * I2C RTC
  85  */
  86
  87 #define CONFIG_CMD_DATE
  88 #define CONFIG_RTC_DS1374
  89
  90 /*
  91  * I2C Temperature Sensor (DTT)
  92  */
  93
  94 #define CONFIG_CMD_DTT
  95 #define CONFIG_DTT_SENSORS { 0, 1 }
  96 #define CONFIG_DTT_DS620
  97
  98 /*
  99  * U-Boot General Configurations
 100  */
 101 #define CONFIG_SYS_LONGHELP
 102 #define CONFIG_SYS_CBSIZE               1024
 103 #define CONFIG_SYS_PBSIZE               \
 104         (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 105 #define CONFIG_SYS_MAXARGS              16
 106 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 107
 108 #define CONFIG_AUTO_COMPLETE
 109 #define CONFIG_CMDLINE_EDITING
 110
 111 /*
 112  * No NOR
 113  */
 114
 115 #define CONFIG_SYS_NO_FLASH
 116
 117 /*
 118  * NAND chip timings for FIXME: which one?
 119  */
 120
 121 #define CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY  333333333
 122 #define CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY   10000000
 123 #define CONFIG_LPC32XX_NAND_MLC_NAND_TA      18181818
 124 #define CONFIG_LPC32XX_NAND_MLC_RD_HIGH      31250000
 125 #define CONFIG_LPC32XX_NAND_MLC_RD_LOW       45454545
 126 #define CONFIG_LPC32XX_NAND_MLC_WR_HIGH      40000000
 127 #define CONFIG_LPC32XX_NAND_MLC_WR_LOW       83333333
 128
 129 /*
 130  * NAND
 131  */
 132
 133 /* driver configuration */
 134 #define CONFIG_SYS_NAND_SELF_INIT
 135 #define CONFIG_SYS_MAX_NAND_DEVICE 1
 136 #define CONFIG_SYS_MAX_NAND_CHIPS 1
 137 #define CONFIG_SYS_NAND_BASE MLC_NAND_BASE
 138 #define CONFIG_NAND_LPC32XX_MLC
 139
 140 #define CONFIG_CMD_NAND
 141
 142 /*
 143  * GPIO
 144  */
 145
 146 #define CONFIG_LPC32XX_GPIO
 147
 148 /*
 149  * SSP/SPI/DISPLAY
 150  */
 151
 152 #define CONFIG_LPC32XX_SSP
 153 #define CONFIG_LPC32XX_SSP_TIMEOUT 100000
 154 #define CONFIG_CMD_MAX6957
 155 #define CONFIG_CMD_HD44760
 156 /*
 157  * Environment
 158  */
 159
 160 #define CONFIG_ENV_IS_IN_NAND           1
 161 #define CONFIG_ENV_SIZE                 0x00020000
 162 #define CONFIG_ENV_OFFSET               0x00100000
 163 #define CONFIG_ENV_OFFSET_REDUND        0x00120000
 164 #define CONFIG_ENV_ADDR                 0x80000100
 165
 166 /*
 167  * Boot Linux
 168  */
 169 #define CONFIG_CMDLINE_TAG
 170 #define CONFIG_SETUP_MEMORY_TAGS
 171 #define CONFIG_INITRD_TAG
 172
 173 #define CONFIG_BOOTFILE                 "uImage"
 174 #define CONFIG_BOOTARGS                 "console=ttyS2,115200n8"
 175 #define CONFIG_LOADADDR                 0x80008000
 176
 177 /*
 178  * SPL
 179  */
 180
 181 /* SPL will be executed at offset 0 */
 182 #define CONFIG_SPL_TEXT_BASE 0x00000000
 183 /* SPL will use SRAM as stack */
 184 #define CONFIG_SPL_STACK     0x0000FFF8
 185 #define CONFIG_SPL_BOARD_INIT
 186 /* Use the framework and generic lib */
 187 #define CONFIG_SPL_FRAMEWORK
 188 /* SPL will use serial */
 189 /* SPL will load U-Boot from NAND offset 0x40000 */
 190 #define CONFIG_SPL_NAND_DRIVERS
 191 #define CONFIG_SPL_NAND_BASE
 192 #define CONFIG_SPL_NAND_BOOT
 193 #define CONFIG_SYS_NAND_U_BOOT_OFFS  0x00040000
 194 #define CONFIG_SPL_PAD_TO 0x20000
 195 /* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
 196 #define CONFIG_SYS_MONITOR_LEN 0x40000 /* actually, MAX size */
 197 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
 198 #define CONFIG_SYS_NAND_U_BOOT_DST   CONFIG_SYS_TEXT_BASE
 199
 200 /*
 201  * Include SoC specific configuration
 202  */
 203 #include <asm/arch/config.h>
 204
 205 #endif  /* __CONFIG_WORK_92105_H__*/