include/configs/xaeniax.h

   1 /*
   2  * (C) Copyright 2004-2005
   3  * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
   4  *
   5  * (C) Copyright 2004
   6  * Vincent Dubey, Xa SA, vincent.dubey@xa-ch.com
   7  *
   8  * (C) Copyright 2002
   9  * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.ne
  10  *
  11  * (C) Copyright 2002
  12  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  13  * Marius Groeger <mgroeger@sysgo.de>
  14  *
  15  * Configuation settings for the xaeniax board.
  16  *
  17  * See file CREDITS for list of people who contributed to this
  18  * project.
  19  *
  20  * This program is free software; you can redistribute it and/or
  21  * modify it under the terms of the GNU General Public License as
  22  * published by the Free Software Foundation; either version 2 of
  23  * the License, or (at your option) any later version.
  24  *
  25  * This program is distributed in the hope that it will be useful,
  26  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  27  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  28  * GNU General Public License for more details.
  29  *
  30  * You should have received a copy of the GNU General Public License
  31  * along with this program; if not, write to the Free Software
  32  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  33  * MA 02111-1307 USA
  34  */
  35
  36 #ifndef __CONFIG_H
  37 #define __CONFIG_H
  38
  39 /*
  40  * High Level Configuration Options
  41  * (easy to change)
  42  */
  43 #define CONFIG_CPU_PXA25X               1       /* This is an PXA255 CPU    */
  44 #define CONFIG_XAENIAX          1       /* on a xaeniax board       */
  45 #define CONFIG_SYS_TEXT_BASE    0x0
  46
  47
  48 #define CONFIG_BOARD_LATE_INIT
  49
  50
  51 #undef CONFIG_USE_IRQ                   /* we don't need IRQ/FIQ stuff */
  52
  53 /* we will never enable dcache, because we have to setup MMU first */
  54 #define CONFIG_SYS_DCACHE_OFF
  55
  56 /*
  57  * select serial console configuration
  58  */
  59 #define CONFIG_PXA_SERIAL
  60 #define CONFIG_BTUART          1       /* we use BTUART on XAENIAX */
  61
  62
  63 /* allow to overwrite serial and ethaddr */
  64 #define CONFIG_ENV_OVERWRITE
  65
  66 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
  67
  68 #define CONFIG_BAUDRATE         115200
  69
  70 /*
  71  * BOOTP options
  72  */
  73 #define CONFIG_BOOTP_BOOTFILESIZE
  74 #define CONFIG_BOOTP_BOOTPATH
  75 #define CONFIG_BOOTP_GATEWAY
  76 #define CONFIG_BOOTP_HOSTNAME
  77
  78
  79 /*
  80  * Command line configuration.
  81  */
  82 #include <config_cmd_default.h>
  83
  84 #define CONFIG_CMD_DHCP
  85 #define CONFIG_CMD_DIAG
  86 #define CONFIG_CMD_NFS
  87 #define CONFIG_CMD_SDRAM
  88 #define CONFIG_CMD_SNTP
  89
  90 #undef CONFIG_CMD_DTT
  91
  92
  93 #define CONFIG_ETHADDR          08:00:3e:26:0a:5b
  94 #define CONFIG_NETMASK          255.255.255.0
  95 #define CONFIG_IPADDR           192.168.68.201
  96 #define CONFIG_SERVERIP         192.168.68.62
  97
  98 #define CONFIG_BOOTDELAY        3
  99 #define CONFIG_BOOTCOMMAND      "bootm 0x00100000"
 100 #define CONFIG_BOOTARGS         "console=ttyS1,115200"
 101 #define CONFIG_CMDLINE_TAG              1       /* enable passing of ATAGs */
 102 #define CONFIG_SETUP_MEMORY_TAGS        1
 103 #define CONFIG_INITRD_TAG               1
 104
 105 #if defined(CONFIG_CMD_KGDB)
 106 #define CONFIG_KGDB_BAUDRATE    115200                  /* speed to run kgdb serial port */
 107 #define CONFIG_KGDB_SER_INDEX   1                       /* which serial port to use */
 108 #endif
 109
 110 /*
 111  * Size of malloc() pool; this lives below the uppermost 128 KiB which are
 112  * used for the RAM copy of the uboot code
 113  */
 114 #define CONFIG_SYS_MALLOC_LEN       (CONFIG_ENV_SIZE + 128*1024)
 115
 116 /*
 117  * Miscellaneous configurable options
 118  */
 119 #define CONFIG_SYS_LONGHELP                             /* undef to save memory */
 120 #define CONFIG_SYS_HUSH_PARSER          1
 121
 122
 123 #ifdef CONFIG_SYS_HUSH_PARSER
 124 #define CONFIG_SYS_PROMPT               "u-boot$ "      /* Monitor Command Prompt */
 125 #else
 126 #define CONFIG_SYS_PROMPT               "u-boot=> "     /* Monitor Command Prompt */
 127 #endif
 128 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size      */
 129 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 130 #define CONFIG_SYS_MAXARGS              16              /* max number of command args   */
 131 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 132 #define CONFIG_SYS_DEVICE_NULLDEV       1
 133
 134 #define CONFIG_SYS_MEMTEST_START        0xa0400000      /* memtest works on     */
 135 #define CONFIG_SYS_MEMTEST_END          0xa0800000      /* 4 ... 8 MB in DRAM   */
 136
 137 #define CONFIG_SYS_LOAD_ADDR            0xa1000000      /* default load address */
 138
 139 #define CONFIG_SYS_HZ                   1000
 140 #define CONFIG_SYS_CPUSPEED             0x141           /* set core clock to 400/200/100 MHz */
 141
 142 /*
 143  * Physical Memory Map
 144  */
 145 #define CONFIG_NR_DRAM_BANKS    1          /* we have 1 banks (partition) of DRAM */
 146 #define PHYS_SDRAM_1            0xa0000000 /* SDRAM Bank #1 */
 147 #define PHYS_SDRAM_1_SIZE       0x04000000 /* 64 MB */
 148 #define PHYS_SDRAM_2            0xa4000000 /* SDRAM Bank #2 */
 149 #define PHYS_SDRAM_2_SIZE       0x00000000 /* 0 MB */
 150 #define PHYS_SDRAM_3            0xa8000000 /* SDRAM Bank #3 */
 151 #define PHYS_SDRAM_3_SIZE       0x00000000 /* 0 MB */
 152 #define PHYS_SDRAM_4            0xac000000 /* SDRAM Bank #4 */
 153 #define PHYS_SDRAM_4_SIZE       0x00000000 /* 0 MB */
 154
 155 #define PHYS_FLASH_1            0x00000000 /* Flash Bank #1 */
 156 #define PHYS_FLASH_2            0x04000000 /* Flash Bank #2 */
 157 #define PHYS_FLASH_SIZE         0x02000000 /* 32 MB */
 158 #define PHYS_FLASH_BANK_SIZE    0x02000000 /* 32 MB Banks */
 159 #define PHYS_FLASH_SECT_SIZE    0x00040000 /* 256 KB sectors (x2) */
 160
 161 #define CONFIG_SYS_DRAM_BASE            0xa0000000
 162 #define CONFIG_SYS_DRAM_SIZE            0x04000000
 163
 164 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 165
 166 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 167 #define CONFIG_SYS_INIT_SP_ADDR         0xfffff800
 168
 169 /*
 170  * FLASH and environment organization
 171  */
 172 #define CONFIG_SYS_MAX_FLASH_BANKS      1    /* max number of memory banks              */
 173 #define CONFIG_SYS_MAX_FLASH_SECT       128  /* max number of sectors on one chip    */
 174
 175 /* timeout values are in ticks */
 176 #define CONFIG_SYS_FLASH_ERASE_TOUT     (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
 177 #define CONFIG_SYS_FLASH_WRITE_TOUT     (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 178
 179 /* FIXME */
 180 #define CONFIG_ENV_IS_IN_FLASH  1
 181 #define CONFIG_ENV_ADDR         (PHYS_FLASH_1 + 0x40000)/* Addr of Environment Sector   */
 182 #define CONFIG_ENV_SIZE         0x40000                 /* Total Size of Environment Sector     */
 183
 184 /*
 185  * Stack sizes
 186  *
 187  * The stack sizes are set up in start.S using the settings below
 188  */
 189 #define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
 190 #ifdef CONFIG_USE_IRQ
 191 #define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
 192 #define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
 193 #endif
 194
 195 /*
 196  * SMSC91C111 Network Card
 197  */
 198 #define CONFIG_SMC91111         1
 199 #define CONFIG_SMC91111_BASE            0x10000300  /* chip select 3         */
 200 #define CONFIG_SMC_USE_32_BIT           1          /* 32 bit bus  */
 201 #undef  CONFIG_SMC_91111_EXT_PHY                   /* we use internal phy   */
 202 #undef  CONFIG_SHOW_ACTIVITY
 203 #define CONFIG_NET_RETRY_COUNT          10         /* # of retries          */
 204
 205 /*
 206  * GPIO settings
 207  */
 208
 209 /*
 210  * GP05 == nUSBReset  is 1
 211  * GP10 == CFReset   is 1
 212  * GP13 == nCFDataEnable is 1
 213  * GP14 == nCFAddrEnable is 1
 214  * GP15 == nCS1      is 1
 215  * GP21 == ComBrdReset is 1
 216  * GP24 == SFRM      is 1
 217  * GP25 == TXD       is 1
 218  * GP31 == SYNC      is 1
 219  * GP33 == nCS5      is 1
 220  * GP39 == FFTXD     is 1
 221  * GP41 == RTS       is 1
 222  * GP43 == BTTXD     is 1
 223  * GP45 == BTRTS     is 1
 224  * GP47 == TXD       is 1
 225  * GP48 == nPOE      is 1
 226  * GP49 == nPWE      is 1
 227  * GP50 == nPIOR     is 1
 228  * GP51 == nPIOW     is 1
 229  * GP52 == nPCE[1]   is 1
 230  * GP53 == nPCE[2]   is 1
 231  * GP54 == nPSKTSEL  is 1
 232  * GP55 == nPREG     is 1
 233  * GP78 == nCS2      is 1
 234  * GP79 == nCS3      is 1
 235  * GP80 == nCS4      is 1
 236  * GP82 == NSSPSFRM  is 1
 237  * GP83 == NSSPTXD   is 1
 238  */
 239 #define CONFIG_SYS_GPSR0_VAL            0x8320E420
 240 #define CONFIG_SYS_GPSR1_VAL            0x00FFAA82
 241 #define CONFIG_SYS_GPSR2_VAL            0x000DC000
 242
 243 /*
 244  * GP03 == LANReset  is 0
 245  * GP06 == USBWakeUp  is 0
 246  * GP11 == USBControl is 0
 247  * GP12 == Buzzer     is 0
 248  * GP16 == PWM0       is 0
 249  * GP17 == PWM1       is 0
 250  * GP23 == SCLK      is 0
 251  * GP30 == SDATA_OUT is 0
 252  * GP81 == NSSPCLK   is 0
 253  */
 254 #define CONFIG_SYS_GPCR0_VAL            0x40C31848
 255 #define CONFIG_SYS_GPCR1_VAL            0x00000000
 256 #define CONFIG_SYS_GPCR2_VAL            0x00020000
 257
 258 /*
 259  * GP00 == CPUWakeUpUSB is input
 260  * GP01 == GP reset is input
 261  * GP02 == LANInterrupt is input
 262  * GP03 == LANReset     is output
 263  * GP04 == USBInterrupt is input
 264  * GP05 == nUSBReset    is output
 265  * GP06 == USBWakeUp    is output
 266  * GP07 == CFReady/nBusy is input
 267  * GP08 == nCFCardDetect1 is input
 268  * GP09 == nCFCardDetect2 is input
 269  * GP10 == nCFReset   is output
 270  * GP11 == USBControl is output
 271  * GP12 == Buzzer     is output
 272  * GP13 == CFDataEnable is output
 273  * GP14 == CFAddressEnable is output
 274  * GP15 == nCS1      is output
 275  * GP16 == PWM0      is output
 276  * GP17 == PWM1      is output
 277  * GP18 == RDY       is input
 278  * GP19 == ReaderReady is input
 279  * GP20 == ReaderReset is input
 280  * GP21 == ComBrdReset is output
 281  * GP23 == SCLK      is output
 282  * GP24 == SFRM      is output
 283  * GP25 == TXD       is output
 284  * GP26 == RXD       is input
 285  * GP27 == EXTCLK    is input
 286  * GP28 == BITCLK    is output
 287  * GP29 == SDATA_IN0 is input
 288  * GP30 == SDATA_OUT is output
 289  * GP31 == SYNC      is output
 290  * GP32 == SYSSCLK   is output
 291  * GP33 == nCS5      is output
 292  * GP34 == FFRXD     is input
 293  * GP35 == CTS       is input
 294  * GP36 == DCD       is input
 295  * GP37 == DSR       is input
 296  * GP38 == RI        is input
 297  * GP39 == FFTXD     is output
 298  * GP40 == DTR       is output
 299  * GP41 == RTS       is output
 300  * GP42 == BTRXD     is input
 301  * GP43 == BTTXD     is output
 302  * GP44 == BTCTS     is input
 303  * GP45 == BTRTS     is output
 304  * GP46 == RXD       is input
 305  * GP47 == TXD       is output
 306  * GP48 == nPOE      is output
 307  * GP49 == nPWE      is output
 308  * GP50 == nPIOR     is output
 309  * GP51 == nPIOW     is output
 310  * GP52 == nPCE[1]   is output
 311  * GP53 == nPCE[2]   is output
 312  * GP54 == nPSKTSEL  is output
 313  * GP55 == nPREG     is output
 314  * GP56 == nPWAIT    is input
 315  * GP57 == nPIOS16   is input
 316  * GP58 == LDD[0]    is output
 317  * GP59 == LDD[1]    is output
 318  * GP60 == LDD[2]    is output
 319  * GP61 == LDD[3]    is output
 320  * GP62 == LDD[4]    is output
 321  * GP63 == LDD[5]    is output
 322  * GP64 == LDD[6]    is output
 323  * GP65 == LDD[7]    is output
 324  * GP66 == LDD[8]    is output
 325  * GP67 == LDD[9]    is output
 326  * GP68 == LDD[10]   is output
 327  * GP69 == LDD[11]   is output
 328  * GP70 == LDD[12]   is output
 329  * GP71 == LDD[13]   is output
 330  * GP72 == LDD[14]   is output
 331  * GP73 == LDD[15]   is output
 332  * GP74 == LCD_FCLK  is output
 333  * GP75 == LCD_LCLK  is output
 334  * GP76 == LCD_PCLK  is output
 335  * GP77 == LCD_ACBIAS is output
 336  * GP78 == nCS2      is output
 337  * GP79 == nCS3      is output
 338  * GP80 == nCS4      is output
 339  * GP81 == NSSPCLK   is output
 340  * GP82 == NSSPSFRM  is output
 341  * GP83 == NSSPTXD   is output
 342  * GP84 == NSSPRXD   is input
 343  */
 344 #define CONFIG_SYS_GPDR0_VAL            0xD3E3FC68
 345 #define CONFIG_SYS_GPDR1_VAL            0xFCFFAB83
 346 #define CONFIG_SYS_GPDR2_VAL            0x000FFFFF
 347
 348 /*
 349  * GP01 == GP reset is AF01
 350  * GP15 == nCS1     is AF10
 351  * GP16 == PWM0     is AF10
 352  * GP17 == PWM1     is AF10
 353  * GP18 == RDY      is AF01
 354  * GP23 == SCLK     is AF10
 355  * GP24 == SFRM     is AF10
 356  * GP25 == TXD      is AF10
 357  * GP26 == RXD      is AF01
 358  * GP27 == EXTCLK   is AF01
 359  * GP28 == BITCLK   is AF01
 360  * GP29 == SDATA_IN0 is AF10
 361  * GP30 == SDATA_OUT is AF01
 362  * GP31 == SYNC     is AF01
 363  * GP32 == SYSCLK   is AF01
 364  * GP33 == nCS5  is AF10
 365  * GP34 == FFRXD is AF01
 366  * GP35 == CTS   is AF01
 367  * GP36 == DCD   is AF01
 368  * GP37 == DSR   is AF01
 369  * GP38 == RI    is AF01
 370  * GP39 == FFTXD is AF10
 371  * GP40 == DTR   is AF10
 372  * GP41 == RTS   is AF10
 373  * GP42 == BTRXD is AF01
 374  * GP43 == BTTXD is AF10
 375  * GP44 == BTCTS is AF01
 376  * GP45 == BTRTS is AF10
 377  * GP46 == RXD   is AF10
 378  * GP47 == TXD   is AF01
 379  * GP48 == nPOE  is AF10
 380  * GP49 == nPWE  is AF10
 381  * GP50 == nPIOR is AF10
 382  * GP51 == nPIOW is AF10
 383  * GP52 == nPCE[1] is AF10
 384  * GP53 == nPCE[2] is AF10
 385  * GP54 == nPSKTSEL is AF10
 386  * GP55 == nPREG   is AF10
 387  * GP56 == nPWAIT  is AF01
 388  * GP57 == nPIOS16 is AF01
 389  * GP58 == LDD[0]  is AF10
 390  * GP59 == LDD[1]  is AF10
 391  * GP60 == LDD[2]  is AF10
 392  * GP61 == LDD[3]  is AF10
 393  * GP62 == LDD[4]  is AF10
 394  * GP63 == LDD[5]  is AF10
 395  * GP64 == LDD[6]  is AF10
 396  * GP65 == LDD[7]  is AF10
 397  * GP66 == LDD[8]  is AF10
 398  * GP67 == LDD[9]  is AF10
 399  * GP68 == LDD[10] is AF10
 400  * GP69 == LDD[11] is AF10
 401  * GP70 == LDD[12] is AF10
 402  * GP71 == LDD[13] is AF10
 403  * GP72 == LDD[14] is AF10
 404  * GP73 == LDD[15] is AF10
 405  * GP74 == LCD_FCLK is AF10
 406  * GP75 == LCD_LCLK is AF10
 407  * GP76 == LCD_PCLK is AF10
 408  * GP77 == LCD_ACBIAS is AF10
 409  * GP78 == nCS2     is AF10
 410  * GP79 == nCS3     is AF10
 411  * GP80 == nCS4     is AF10
 412  * GP81 == NSSPCLK  is AF01
 413  * GP82 == NSSPSFRM is AF01
 414  * GP83 == NSSPTXD  is AF01
 415  * GP84 == NSSPRXD  is AF10
 416  */
 417 #define CONFIG_SYS_GAFR0_L_VAL          0x80000004
 418 #define CONFIG_SYS_GAFR0_U_VAL          0x595A801A
 419 #define CONFIG_SYS_GAFR1_L_VAL          0x699A9559
 420 #define CONFIG_SYS_GAFR1_U_VAL          0xAAA5AAAA
 421 #define CONFIG_SYS_GAFR2_L_VAL          0xAAAAAAAA
 422 #define CONFIG_SYS_GAFR2_U_VAL          0x00000256
 423
 424 /*
 425  * clock settings
 426  */
 427 /* RDH = 1
 428  * PH  = 0
 429  * VFS = 0
 430  * BFS = 0
 431  * SSS = 0
 432  */
 433 #define CONFIG_SYS_PSSR_VAL             0x00000030
 434
 435 #define CONFIG_SYS_CKEN                 0x00000080  /*  */
 436 #define CONFIG_SYS_ICMR                 0x00000000  /* No interrupts enabled        */
 437 #define CONFIG_SYS_CCCR                 CCCR_L27|CCCR_M2|CCCR_N10
 438
 439
 440 /*
 441  * Memory settings
 442  *
 443  * This is the configuration for nCS0/1 -> flash banks
 444  * configuration for nCS1 :
 445  * [31]    0    -
 446  * [30:28] 000  -
 447  * [27:24] 0000 -
 448  * [23:20] 0000 -
 449  * [19]    0    -
 450  * [18:16] 000  -
 451  * configuration for nCS0:
 452  * [15]    0    - Slower Device
 453  * [14:12] 010  - CS deselect to CS time: 2*(2*MemClk) = 40 ns
 454  * [11:08] 0011 - Address to data valid in bursts: (3+1)*MemClk = 40 ns
 455  * [07:04] 1111 - " for first access: (23+2)*MemClk = 250 ns (fixme 12+2?)
 456  * [03]    0    - 32 Bit bus width
 457  * [02:00] 010  - burst OF 4 ROM or FLASH
 458 */
 459 #define CONFIG_SYS_MSC0_VAL             0x000023D2
 460
 461 /* This is the configuration for nCS2/3 -> USB controller, LAN
 462  * configuration for nCS3: LAN
 463  * [31]    0    - Slower Device
 464  * [30:28] 001  - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns
 465  * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns
 466  * [23:20] 0010 - RDF3: Address for first access: (2+1)*MemClk = 30 ns
 467  * [19]    0    - 32 Bit bus width
 468  * [18:16] 100  - variable latency I/O
 469  * configuration for nCS2: USB
 470  * [15]    1    - Faster Device
 471  * [14:12] 010  - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns
 472  * [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns
 473  * [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns
 474  * [03]    1    - 16 Bit bus width
 475  * [02:00] 100  - variable latency I/O
 476  */
 477 #define CONFIG_SYS_MSC1_VAL             0x1224A26C
 478
 479 /* This is the configuration for nCS4/5 -> LAN
 480  * configuration for nCS5:
 481  * [31]    0    -
 482  * [30:28] 000  -
 483  * [27:24] 0000 -
 484  * [23:20] 0000 -
 485  * [19]    0    -
 486  * [18:16] 000  -
 487  * configuration for nCS4: LAN
 488  * [15]    1    - Faster Device
 489  * [14:12] 010  - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns
 490  * [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns
 491  * [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns
 492  * [03]    0    - 32 Bit bus width
 493  * [02:00] 100  - variable latency I/O
 494  */
 495 #define CONFIG_SYS_MSC2_VAL             0x00001224
 496
 497 /* MDCNFG: SDRAM Configuration Register
 498  *
 499  * [31:29]   000 - reserved
 500  * [28]      0   - no SA1111 compatiblity mode
 501  * [27]      0   - latch return data with return clock
 502  * [26]      0   - alternate addressing for pair 2/3
 503  * [25:24]   00  - timings
 504  * [23]      0   - internal banks in lower partition 2/3 (not used)
 505  * [22:21]   00  - row address bits for partition 2/3 (not used)
 506  * [20:19]   00  - column address bits for partition 2/3 (not used)
 507  * [18]      0   - SDRAM partition 2/3 width is 32 bit
 508  * [17]      0   - SDRAM partition 3 disabled
 509  * [16]      0   - SDRAM partition 2 disabled
 510  * [15:13]   000 - reserved
 511  * [12]      0   - no SA1111 compatiblity mode
 512  * [11]      1   - latch return data with return clock
 513  * [10]      0   - no alternate addressing for pair 0/1
 514  * [09:08]   10  - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk
 515  * [7]       1   - 4 internal banks in lower partition pair
 516  * [06:05]   10  - 13 row address bits for partition 0/1
 517  * [04:03]   01  - 9 column address bits for partition 0/1
 518  * [02]      0   - SDRAM partition 0/1 width is 32 bit
 519  * [01]      0   - disable SDRAM partition 1
 520  * [00]      1   - enable  SDRAM partition 0
 521  */
 522 /* use the configuration above but disable partition 0 */
 523 #define CONFIG_SYS_MDCNFG_VAL           0x00000AC9
 524
 525 /* MDREFR: SDRAM Refresh Control Register
 526  *
 527  * [32:26] 0     - reserved
 528  * [25]    0     - K2FREE: not free running
 529  * [24]    0     - K1FREE: not free running
 530  * [23]    0     - K0FREE: not free running
 531  * [22]    0     - SLFRSH: self refresh disabled
 532  * [21]    0     - reserved
 533  * [20]    1     - APD: auto power down
 534  * [19]    0     - K2DB2: SDCLK2 is MemClk
 535  * [18]    0     - K2RUN: disable SDCLK2
 536  * [17]    0     - K1DB2: SDCLK1 is MemClk
 537  * [16]    1     - K1RUN: enable SDCLK1
 538  * [15]    1     - E1PIN: SDRAM clock enable
 539  * [14]    0     - K0DB2: SDCLK0 is MemClk
 540  * [13]    0     - K0RUN: disable SDCLK0
 541  * [12]    0     - E0PIN: disable SDCKE0
 542  * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
 543  */
 544 #define CONFIG_SYS_MDREFR_VAL           0x00138018 /* mh: was 0x00118018 */
 545
 546 /* MDMRS: Mode Register Set Configuration Register
 547  *
 548  * [31]      0       - reserved
 549  * [30:23]   00000000- MDMRS2: SDRAM2/3 MRS Value. (not used)
 550  * [22:20]   011     - MDCL2:  SDRAM2/3 Cas Latency.  (not used)
 551  * [19]      0       - MDADD2: SDRAM2/3 burst Type. Fixed to sequential.  (not used)
 552  * [18:16]   010     - MDBL2:  SDRAM2/3 burst Length. Fixed to 4.  (not used)
 553  * [15]      0       - reserved
 554  * [14:07]   00000000- MDMRS0: SDRAM0/1 MRS Value.
 555  * [06:04]   011     - MDCL0:  SDRAM0/1 Cas Latency.
 556  * [03]      0       - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
 557  * [02:00]   010     - MDBL0:  SDRAM0/1 burst Length. Fixed to 4.
 558  */
 559 #define CONFIG_SYS_MDMRS_VAL            0x00320032
 560
 561 #define CONFIG_SYS_FLYCNFG_VAL          0x00000000
 562 #define CONFIG_SYS_SXCNFG_VAL           0x00000000
 563
 564 /*
 565  * PCMCIA and CF Interfaces
 566  */
 567 #define CONFIG_SYS_MECR_VAL             0x00000000
 568 #define CONFIG_SYS_MCMEM0_VAL           0x00010504
 569 #define CONFIG_SYS_MCMEM1_VAL           0x00010504
 570 #define CONFIG_SYS_MCATT0_VAL           0x00010504
 571 #define CONFIG_SYS_MCATT1_VAL           0x00010504
 572 #define CONFIG_SYS_MCIO0_VAL            0x00004715
 573 #define CONFIG_SYS_MCIO1_VAL            0x00004715
 574
 575
 576 #endif  /* __CONFIG_H */