include/configs/xupv2p.h

   1 /*
   2  * (C) Copyright 2007 Czech Technical University.
   3  *
   4  * Michal SIMEK <monstr@monstr.eu>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #ifndef __CONFIG_H
  26 #define __CONFIG_H
  27
  28 #include "../board/xilinx/xupv2p/xparameters.h"
  29
  30 #define CONFIG_MICROBLAZE       1       /* MicroBlaze CPU */
  31 #define CONFIG_XUPV2P           1
  32
  33 /* uart */
  34 #define CONFIG_SERIAL_BASE      XILINX_UART_BASEADDR
  35 #define CONFIG_BAUDRATE         XILINX_UART_BAUDRATE
  36 #define CFG_BAUDRATE_TABLE      { CONFIG_BAUDRATE }
  37
  38 /* ethernet */
  39 #define CONFIG_EMAC     1
  40 #define XPAR_EMAC_0_DEVICE_ID   XPAR_XEMAC_NUM_INSTANCES
  41
  42 /*
  43  * setting reset address
  44  *
  45  * TEXT_BASE is set to place, where the U-BOOT run in RAM, but
  46  * if you want to store U-BOOT in flash, set CFG_RESET_ADDRESS
  47  * to FLASH memory and after loading bitstream jump to FLASH.
  48  * U-BOOT auto-relocate to TEXT_BASE. After RESET command Microblaze
  49  * jump to CFG_RESET_ADDRESS where is the original U-BOOT code.
  50  */
  51 #define CFG_RESET_ADDRESS       0x36000000
  52
  53 /* gpio */
  54 #define CFG_GPIO_0              1
  55 #define CFG_GPIO_0_ADDR         XILINX_GPIO_BASEADDR
  56
  57 /* interrupt controller */
  58 #define CFG_INTC_0              1
  59 #define CFG_INTC_0_ADDR         XILINX_INTC_BASEADDR
  60 #define CFG_INTC_0_NUM          XILINX_INTC_NUM_INTR_INPUTS
  61
  62 /* timer */
  63 #define CFG_TIMER_0             1
  64 #define CFG_TIMER_0_ADDR        XILINX_TIMER_BASEADDR
  65 #define CFG_TIMER_0_IRQ         XILINX_TIMER_IRQ
  66 #define FREQUENCE               XILINX_CLOCK_FREQ
  67 #define CFG_TIMER_0_PRELOAD     ( FREQUENCE/1000 )
  68
  69 /*
  70  * memory layout - Example
  71  * TEXT_BASE = 0x3600_0000;
  72  * CFG_SRAM_BASE = 0x3000_0000;
  73  * CFG_SRAM_SIZE = 0x1000_0000;
  74  *
  75  * CFG_GBL_DATA_OFFSET = 0x3000_0000 + 0x1000_0000 - 0x1000 = 0x3FFF_F000
  76  * CFG_MONITOR_BASE = 0x3FFF_F000 - 0x40000 = 0x3FFB_F000
  77  * CFG_MALLOC_BASE = 0x3FFB_F000 - 0x40000 = 0x3FF7_F000
  78  *
  79  * 0x3000_0000  CFG_SDRAM_BASE
  80  *                                      FREE
  81  * 0x3600_0000  TEXT_BASE
  82  *              U-BOOT code
  83  * 0x3602_0000
  84  *                                      FREE
  85  *
  86  *                                      STACK
  87  * 0x3FF7_F000  CFG_MALLOC_BASE
  88  *                                      MALLOC_AREA     256kB   Alloc
  89  * 0x3FFB_F000  CFG_MONITOR_BASE
  90  *                                      MONITOR_CODE    256kB   Env
  91  * 0x3FFF_F000  CFG_GBL_DATA_OFFSET
  92  *                                      GLOBAL_DATA     4kB     bd, gd
  93  * 0x4000_0000  CFG_SDRAM_BASE + CFG_SDRAM_SIZE
  94  */
  95
  96 /* ddr sdram - main memory */
  97 #define CFG_SDRAM_BASE          XILINX_RAM_START
  98 #define CFG_SDRAM_SIZE          XILINX_RAM_SIZE
  99 #define CFG_MEMTEST_START       CFG_SDRAM_BASE
 100 #define CFG_MEMTEST_END         (CFG_SDRAM_BASE + 0x1000)
 101
 102 /* global pointer */
 103 #define CFG_GBL_DATA_SIZE       0x1000  /* size of global data */
 104 #define CFG_GBL_DATA_OFFSET     (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE) /* start of global data */
 105
 106 /* monitor code */
 107 #define SIZE                    0x40000
 108 #define CFG_MONITOR_LEN         SIZE
 109 #define CFG_MONITOR_BASE        (CFG_GBL_DATA_OFFSET - CFG_MONITOR_LEN)
 110 #define CFG_MONITOR_END         (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
 111 #define CFG_MALLOC_LEN          SIZE
 112 #define CFG_MALLOC_BASE         (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
 113
 114 /* stack */
 115 #define CFG_INIT_SP_OFFSET      CFG_MALLOC_BASE
 116
 117 #define CFG_NO_FLASH            1
 118 #define CFG_ENV_IS_NOWHERE      1
 119 #define CFG_ENV_SIZE            0x1000
 120 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE - CFG_ENV_SIZE)
 121
 122
 123 /*
 124  * Command line configuration.
 125  */
 126 #include <config_cmd_default.h>
 127
 128 #define CONFIG_CMD_MEMORY
 129 #define CONFIG_CMD_IRQ
 130 #define CONFIG_CMD_BDI
 131 #define CONFIG_CMD_NET
 132 #define CONFIG_CMD_IMI
 133 #define CONFIG_CMD_ECHO
 134 #define CONFIG_CMD_CACHE
 135 #define CONFIG_CMD_RUN
 136 #define CONFIG_CMD_AUTOSCRIPT
 137 #define CONFIG_CMD_ASKENV
 138 #define CONFIG_CMD_LOADS
 139 #define CONFIG_CMD_LOADB
 140 #define CONFIG_CMD_MISC
 141 #define CONFIG_CMD_FAT
 142 #define CONFIG_CMD_EXT2
 143 #define CONFIG_CMD_PING
 144
 145
 146 /* Miscellaneous configurable options */
 147 #define CFG_PROMPT      "U-Boot-mONStR> "
 148 #define CFG_CBSIZE      512     /* size of console buffer */
 149 #define CFG_PBSIZE      (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* print buffer size */
 150 #define CFG_MAXARGS     15      /* max number of command args */
 151 #define CFG_LONGHELP
 152 #define CFG_LOAD_ADDR   0x12000000 /* default load address */
 153
 154 #define CONFIG_BOOTDELAY        30
 155 #define CONFIG_BOOTARGS         "root=romfs"
 156 #define CONFIG_HOSTNAME         "ml401"
 157 #define CONFIG_BOOTCOMMAND      "base 0;tftp 11000000 image.img;bootm"
 158 #define CONFIG_IPADDR           192.168.0.3
 159 #define CONFIG_SERVERIP         192.168.0.5
 160 #define CONFIG_GATEWAYIP        192.168.0.1
 161 #define CONFIG_ETHADDR          00:E0:0C:00:00:FD
 162
 163 /* architecture dependent code */
 164 #define CFG_USR_EXCEP   /* user exception */
 165 #define CFG_HZ  1000
 166
 167 #define CONFIG_PREBOOT  "echo U-BOOT by mONStR;"        \
 168         "base 0;" \
 169         "echo"
 170
 171 /* system ace */
 172 #define CONFIG_SYSTEMACE
 173 /* #define DEBUG_SYSTEMACE */
 174 #define SYSTEMACE_CONFIG_FPGA
 175 #define CFG_SYSTEMACE_BASE      XILINX_SYSACE_BASEADDR
 176 #define CFG_SYSTEMACE_WIDTH     XILINX_SYSACE_MEM_WIDTH
 177 #define CONFIG_DOS_PARTITION
 178
 179 #endif  /* __CONFIG_H */