include/configs/yucca.h

   1 /*
   2  * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /************************************************************************
  24  * 1 january 2005       Alain Saurel <asaurel@amcc.com>
  25  * Adapted to current Das U-Boot source
  26  ***********************************************************************/
  27 /************************************************************************
  28  * yucca.h - configuration for AMCC 440SPe Ref (yucca)
  29  ***********************************************************************/
  30
  31 #ifndef __CONFIG_H
  32 #define __CONFIG_H
  33
  34 #define DEBUG
  35 #undef DEBUG
  36
  37 /*-----------------------------------------------------------------------
  38  * High Level Configuration Options
  39  *----------------------------------------------------------------------*/
  40 #define CONFIG_4xx                      1       /* ... PPC4xx family    */
  41 #define CONFIG_440                      1       /* ... PPC440 family    */
  42 #define CONFIG_440SPE                   1       /* Specifc SPe support  */
  43 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init  */
  44 #undef  CFG_DRAM_TEST                           /* Disable-takes long time */
  45 #define CONFIG_SYS_CLK_FREQ     33333333        /* external freq to pll */
  46 #define EXTCLK_33_33            33333333
  47 #define EXTCLK_66_66            66666666
  48 #define EXTCLK_50               50000000
  49 #define EXTCLK_83               83333333
  50
  51 #define CONFIG_IBM_EMAC4_V4             1
  52 #define CONFIG_MISC_INIT_F              1       /* Use misc_init_f()    */
  53 #undef  CONFIG_SHOW_BOOT_PROGRESS
  54 #undef  CONFIG_STRESS
  55 #undef  ENABLE_ECC
  56 /*-----------------------------------------------------------------------
  57  * Base addresses -- Note these are effective addresses where the
  58  * actual resources get mapped (not physical addresses)
  59  *----------------------------------------------------------------------*/
  60 #define CFG_SDRAM_BASE          0x00000000      /* _must_ be 0          */
  61 #define CFG_FLASH_BASE          0xfff00000      /* start of FLASH       */
  62 #define CFG_MONITOR_BASE        0xfffb0000      /* start of monitor     */
  63 #define CFG_PERIPHERAL_BASE     0xa0000000      /* internal peripherals */
  64 #define CFG_ISRAM_BASE          0x90000000      /* internal SRAM        */
  65
  66 #define CFG_PCI_MEMBASE         0x80000000      /* mapped PCI memory    */
  67 #define CFG_PCI_BASE            0xd0000000      /* internal PCI regs    */
  68 #define CFG_PCI_TARGBASE        CFG_PCI_MEMBASE
  69
  70 #define CFG_PCIE_MEMBASE        0xb0000000      /* mapped PCIe memory   */
  71 #define CFG_PCIE_MEMSIZE        0x01000000
  72 #define CFG_PCIE_BASE           0xe0000000      /* PCIe UTL regs */
  73
  74 #define CFG_PCIE0_CFGBASE       0xc0000000
  75 #define CFG_PCIE0_XCFGBASE      0xc0000400
  76 #define CFG_PCIE1_CFGBASE       0xc0001000
  77 #define CFG_PCIE1_XCFGBASE      0xc0001400
  78 #define CFG_PCIE2_CFGBASE       0xc0002000
  79 #define CFG_PCIE2_XCFGBASE      0xc0002400
  80
  81 /* System RAM mapped to PCI space */
  82 #define CONFIG_PCI_SYS_MEM_BUS  CFG_SDRAM_BASE
  83 #define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
  84 #define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
  85
  86 #define CFG_FPGA_BASE           0xe2000000      /* epld                 */
  87 #define CFG_OPER_FLASH          0xe7000000      /* SRAM - OPER Flash    */
  88
  89 /* #define CFG_NVRAM_BASE_ADDR 0x08000000 */
  90 /*-----------------------------------------------------------------------
  91  * Initial RAM & stack pointer (placed in internal SRAM)
  92  *----------------------------------------------------------------------*/
  93 #define CFG_TEMP_STACK_OCM      1
  94 #define CFG_OCM_DATA_ADDR       CFG_ISRAM_BASE
  95 #define CFG_INIT_RAM_ADDR       CFG_ISRAM_BASE  /* Initial RAM address  */
  96 #define CFG_INIT_RAM_END        0x2000          /* End of used area in RAM */
  97 #define CFG_GBL_DATA_SIZE       128             /* num bytes initial data */
  98
  99 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 100 #define CFG_POST_WORD_ADDR      (CFG_GBL_DATA_OFFSET - 0x4)
 101 #define CFG_INIT_SP_OFFSET      CFG_POST_WORD_ADDR
 102
 103 #define CFG_MONITOR_LEN         (320 * 1024)    /* Reserve 320 kB for Mon */
 104 #define CFG_MALLOC_LEN          (512 * 1024)    /* Reserve 512 kB for malloc */
 105
 106 /*-----------------------------------------------------------------------
 107  * Serial Port
 108  *----------------------------------------------------------------------*/
 109 #define CONFIG_SERIAL_MULTI     1
 110 #undef CONFIG_UART1_CONSOLE
 111
 112 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 113 #undef CFG_EXT_SERIAL_CLOCK
 114 /* #define CFG_EXT_SERIAL_CLOCK (1843200 * 6) */ /* Ext clk @ 11.059 MHz */
 115
 116 #define CONFIG_BAUDRATE         115200
 117
 118 #define CFG_BAUDRATE_TABLE  \
 119         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 120
 121 /*-----------------------------------------------------------------------
 122  * DDR SDRAM
 123  *----------------------------------------------------------------------*/
 124 #undef CONFIG_SPD_EEPROM                /* Use SPD EEPROM for setup     */
 125 #define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses        */
 126 #define IIC0_DIMM0_ADDR         0x53
 127 #define IIC0_DIMM1_ADDR         0x52
 128
 129 /*-----------------------------------------------------------------------
 130  * I2C
 131  *----------------------------------------------------------------------*/
 132 #define CONFIG_HARD_I2C         1       /* I2C with hardware support    */
 133 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged               */
 134 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
 135 #define CFG_I2C_SLAVE           0x7F
 136
 137 #define IIC0_BOOTPROM_ADDR      0x50
 138 #define IIC0_ALT_BOOTPROM_ADDR  0x54
 139
 140 /* Don't probe these addrs */
 141 #define CFG_I2C_NOPROBES        {0x50, 0x52, 0x53, 0x54}
 142
 143 /* #if (CONFIG_COMMANDS & CFG_CMD_EEPROM) */
 144 /* #define CFG_I2C_EEPROM_ADDR  0x50 */ /* I2C boot EEPROM              */
 145 #define CFG_I2C_EEPROM_ADDR_LEN 2       /* Bytes of address             */
 146 /* #endif */
 147
 148 /*-----------------------------------------------------------------------
 149  * Environment
 150  *----------------------------------------------------------------------*/
 151 /* #define CFG_NVRAM_SIZE       (0x2000 - 8) */ /* NVRAM size(8k)- RTC regs */
 152
 153 #undef  CFG_ENV_IS_IN_NVRAM             /* ... not in NVRAM             */
 154 #define CFG_ENV_IS_IN_FLASH     1       /* Environment uses flash       */
 155 #undef  CFG_ENV_IS_IN_EEPROM            /* ... not in EEPROM            */
 156 #define CONFIG_ENV_OVERWRITE    1
 157
 158 #define CONFIG_PREBOOT  "echo;" \
 159         "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
 160         "echo"
 161
 162 #undef  CONFIG_BOOTARGS
 163
 164 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 165         "netdev=eth0\0"                                                 \
 166         "hostname=yucca\0"                                              \
 167         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 168                 "nfsroot=${serverip}:${rootpath}\0"                     \
 169         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 170         "addip=setenv bootargs ${bootargs} "                            \
 171                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 172                 ":${hostname}:${netdev}:off panic=1\0"                  \
 173         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 174         "flash_nfs=run nfsargs addip addtty;"                           \
 175                 "bootm ${kernel_addr}\0"                                \
 176         "flash_self=run ramargs addip addtty;"                          \
 177                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 178         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 179                 "bootm\0"                                               \
 180         "rootpath=/opt/eldk/ppc_4xx\0"                          \
 181         "bootfile=yucca/uImage\0"                                       \
 182         "kernel_addr=E7F10000\0"                                        \
 183         "ramdisk_addr=E7F20000\0"                                       \
 184         "load=tftp 100000 yuca/u-boot.bin\0"                            \
 185         "update=protect off 2:4-7;era 2:4-7;"                           \
 186                 "cp.b ${fileaddr} FFFB0000 ${filesize};"                \
 187                 "setenv filesize;saveenv\0"                             \
 188         "upd=run load;run update\0"                                     \
 189         ""
 190 #define CONFIG_BOOTCOMMAND      "run flash_self"
 191
 192 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
 193
 194 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 195 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
 196
 197 #define CONFIG_COMMANDS        (CONFIG_CMD_DFL  | \
 198                                 CFG_CMD_ASKENV  | \
 199                                 CFG_CMD_EEPROM  | \
 200                                 CFG_CMD_DHCP    | \
 201                                 CFG_CMD_DIAG    | \
 202                                 CFG_CMD_ELF     | \
 203                                 CFG_CMD_I2C     | \
 204                                 CFG_CMD_IRQ     | \
 205                                 CFG_CMD_MII     | \
 206                                 CFG_CMD_NET     | \
 207                                 CFG_CMD_NFS     | \
 208                                 CFG_CMD_PCI     | \
 209                                 CFG_CMD_PING    | \
 210                                 CFG_CMD_REGINFO | \
 211                                 CFG_CMD_SDRAM   )
 212
 213 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 214 #include <cmd_confdefs.h>
 215
 216 #define CONFIG_MII              1       /* MII PHY management           */
 217 #undef CONFIG_NET_MULTI
 218 #define CONFIG_PHY_ADDR         1       /* PHY address, See schematics  */
 219 #define CONFIG_HAS_ETH0
 220 #define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
 221 #define CONFIG_PHY_RESET_DELAY  1000
 222 #define CONFIG_CIS8201_PHY      1       /* Enable 'special' RGMII mode for Cicada phy */
 223 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 224 #define CFG_RX_ETH_BUFFER       32      /* Number of ethernet rx buffers & descriptors */
 225
 226 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 227
 228 /*
 229  * Miscellaneous configurable options
 230  */
 231 #define CFG_LONGHELP                            /* undef to save memory         */
 232 #define CFG_PROMPT              "=> "           /* Monitor Command Prompt       */
 233
 234 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 235 #define CFG_CBSIZE              1024            /* Console I/O Buffer Size      */
 236 #else
 237 #define CFG_CBSIZE              256             /* Console I/O Buffer Size      */
 238 #endif
 239 #define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 240 #define CFG_MAXARGS             16              /* max number of command args   */
 241 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 242
 243 #define CFG_MEMTEST_START       0x0400000       /* memtest works on             */
 244 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM          */
 245
 246 #define CFG_LOAD_ADDR           0x100000        /* default load address         */
 247 #define CFG_EXTBDINFO           1               /* To use extended board_into (bd_t) */
 248
 249 #define CFG_HZ                  1000            /* decrementer freq: 1 ms ticks */
 250
 251 /*-----------------------------------------------------------------------
 252  * FLASH related
 253  *----------------------------------------------------------------------*/
 254 #define CFG_MAX_FLASH_BANKS     3       /* number of banks              */
 255 #define CFG_MAX_FLASH_SECT      256     /* sectors per device           */
 256
 257 #undef  CFG_FLASH_CHECKSUM
 258 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms) */
 259 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms) */
 260
 261 #define CFG_FLASH_ADDR0         0x5555
 262 #define CFG_FLASH_ADDR1         0x2aaa
 263 #define CFG_FLASH_WORD_SIZE     unsigned char
 264
 265 #define CFG_FLASH_2ND_16BIT_DEV 1       /* evb440SPe has 8 and 16bit device */
 266 #define CFG_FLASH_2ND_ADDR      0xe7c00000 /* evb440SPe has 8 and 16bit device*/
 267
 268 #ifdef CFG_ENV_IS_IN_FLASH
 269 #define CFG_ENV_SECT_SIZE       0x10000 /* size of one complete sector  */
 270 #define CFG_ENV_ADDR            0xfffa0000
 271 /* #define CFG_ENV_ADDR         (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) */
 272 #define CFG_ENV_SIZE            0x10000 /* Size of Environment vars     */
 273 #endif /* CFG_ENV_IS_IN_FLASH */
 274 /*-----------------------------------------------------------------------
 275  * PCI stuff
 276  *-----------------------------------------------------------------------
 277  */
 278 /* General PCI */
 279 #define CONFIG_PCI                      /* include pci support          */
 280 #define CONFIG_PCI_PNP          1       /* do pci plug-and-play         */
 281 #define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
 282 #undef CONFIG_PCI_CONFIG_HOST_BRIDGE
 283
 284 /* Board-specific PCI */
 285 #define CFG_PCI_PRE_INIT        1       /* enable board pci_pre_init()  */
 286 #define CFG_PCI_TARGET_INIT             /* let board init pci target    */
 287 #undef  CFG_PCI_MASTER_INIT
 288
 289 #define CFG_PCI_SUBSYS_VENDORID 0x1014  /* IBM                          */
 290 #define CFG_PCI_SUBSYS_DEVICEID 0xcafe  /* Whatever                     */
 291 /* #define CFG_PCI_SUBSYS_ID    CFG_PCI_SUBSYS_DEVICEID */
 292
 293 /*
 294  *  NETWORK Support (PCI):
 295  */
 296 /* Support for Intel 82557/82559/82559ER chips. */
 297 #define CONFIG_EEPRO100
 298
 299 /*
 300  * For booting Linux, the board info and command line data
 301  * have to be in the first 8 MB of memory, since this is
 302  * the maximum mapped by the Linux kernel during initialization.
 303  */
 304 #define CFG_BOOTMAPSZ           (8 << 20)       /*Initial Memory map for Linux*/
 305 /*-----------------------------------------------------------------------
 306  * Cache Configuration
 307  */
 308 #define CFG_DCACHE_SIZE         8192    /* For AMCC 405 CPUs            */
 309 #define CFG_CACHELINE_SIZE      32      /* ...                          */
 310 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 311 #define CFG_CACHELINE_SHIFT     5       /* log base 2 of the above value */
 312 #endif
 313
 314 /*
 315  * Internal Definitions
 316  *
 317  * Boot Flags
 318  */
 319 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 320 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 321
 322 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 323 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 324 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 325 #endif
 326
 327 /* FB Divisor selection */
 328 #define FPGA_FB_DIV_6           6
 329 #define FPGA_FB_DIV_10          10
 330 #define FPGA_FB_DIV_12          12
 331 #define FPGA_FB_DIV_20          20
 332
 333 /* VCO Divisor selection */
 334 #define FPGA_VCO_DIV_4          4
 335 #define FPGA_VCO_DIV_6          6
 336 #define FPGA_VCO_DIV_8          8
 337 #define FPGA_VCO_DIV_10         10
 338
 339 /*----------------------------------------------------------------------------+
 340 | FPGA registers and bit definitions
 341 +----------------------------------------------------------------------------*/
 342 /* PowerPC 440SPe Board FPGA is reached with physical address 0x1 E2000000. */
 343 /* TLB initialization makes it correspond to logical address 0xE2000000. */
 344 /* => Done init_chip.s in bootlib */
 345 #define FPGA_REG_BASE_ADDR      0xE2000000
 346 #define FPGA_GPIO_BASE_ADDR     0xE2010000
 347 #define FPGA_INT_BASE_ADDR      0xE2020000
 348
 349 /*----------------------------------------------------------------------------+
 350 | Display
 351 +----------------------------------------------------------------------------*/
 352 #define PPC440SPE_DISPLAY       FPGA_REG_BASE_ADDR
 353
 354 #define PPC440SPE_DISPLAY_D8    (FPGA_REG_BASE_ADDR+0x06)
 355 #define PPC440SPE_DISPLAY_D4    (FPGA_REG_BASE_ADDR+0x04)
 356 #define PPC440SPE_DISPLAY_D2    (FPGA_REG_BASE_ADDR+0x02)
 357 #define PPC440SPE_DISPLAY_D1    (FPGA_REG_BASE_ADDR+0x00)
 358 /*define   WRITE_DISPLAY_DIGIT(n) IOREG8(FPGA_REG_BASE_ADDR + (2*n))*/
 359 /*#define   IOREG8(addr) *((volatile unsigned char *)(addr))*/
 360
 361 /*----------------------------------------------------------------------------+
 362 | ethernet/reset/boot Register 1
 363 +----------------------------------------------------------------------------*/
 364 #define FPGA_REG10      (FPGA_REG_BASE_ADDR+0x10)
 365
 366 #define FPGA_REG10_10MHZ_ENABLE         0x8000
 367 #define FPGA_REG10_100MHZ_ENABLE        0x4000
 368 #define FPGA_REG10_GIGABIT_ENABLE       0x2000
 369 #define FPGA_REG10_FULL_DUPLEX          0x1000  /* force Full Duplex*/
 370 #define FPGA_REG10_RESET_ETH            0x0800
 371 #define FPGA_REG10_AUTO_NEG_DIS         0x0400
 372 #define FPGA_REG10_INTP_ETH             0x0200
 373
 374 #define FPGA_REG10_RESET_HISR           0x0080
 375 #define FPGA_REG10_ENABLE_DISPLAY       0x0040
 376 #define FPGA_REG10_RESET_SDRAM          0x0020
 377 #define FPGA_REG10_OPER_BOOT            0x0010
 378 #define FPGA_REG10_SRAM_BOOT            0x0008
 379 #define FPGA_REG10_SMALL_BOOT           0x0004
 380 #define FPGA_REG10_FORCE_COLA           0x0002
 381 #define FPGA_REG10_COLA_MANUAL          0x0001
 382
 383 #define FPGA_REG10_SDRAM_ENABLE         0x0020
 384
 385 #define FPGA_REG10_ENET_ENCODE2(n) ((((unsigned long)(n))&0x0F)<<4) /*from ocotea ?*/
 386 #define FPGA_REG10_ENET_DECODE2(n) ((((unsigned long)(n))>>4)&0x0F) /*from ocotea ?*/
 387
 388 /*----------------------------------------------------------------------------+
 389 | MUX control
 390 +----------------------------------------------------------------------------*/
 391 #define FPGA_REG12      (FPGA_REG_BASE_ADDR+0x12)
 392
 393 #define FPGA_REG12_EBC_CTL              0x8000
 394 #define FPGA_REG12_UART1_CTS_RTS        0x4000
 395 #define FPGA_REG12_UART0_RX_ENABLE      0x2000
 396 #define FPGA_REG12_UART1_RX_ENABLE      0x1000
 397 #define FPGA_REG12_UART2_RX_ENABLE      0x0800
 398 #define FPGA_REG12_EBC_OUT_ENABLE       0x0400
 399 #define FPGA_REG12_GPIO0_OUT_ENABLE     0x0200
 400 #define FPGA_REG12_GPIO1_OUT_ENABLE     0x0100
 401 #define FPGA_REG12_GPIO_SELECT          0x0010
 402 #define FPGA_REG12_GPIO_CHREG           0x0008
 403 #define FPGA_REG12_GPIO_CLK_CHREG       0x0004
 404 #define FPGA_REG12_GPIO_OETRI           0x0002
 405 #define FPGA_REG12_EBC_ERROR            0x0001
 406
 407 /*----------------------------------------------------------------------------+
 408 | PCI Clock control
 409 +----------------------------------------------------------------------------*/
 410 #define FPGA_REG16      (FPGA_REG_BASE_ADDR+0x16)
 411
 412 #define FPGA_REG16_PCI_CLK_CTL0         0x8000
 413 #define FPGA_REG16_PCI_CLK_CTL1         0x4000
 414 #define FPGA_REG16_PCI_CLK_CTL2         0x2000
 415 #define FPGA_REG16_PCI_CLK_CTL3         0x1000
 416 #define FPGA_REG16_PCI_CLK_CTL4         0x0800
 417 #define FPGA_REG16_PCI_CLK_CTL5         0x0400
 418 #define FPGA_REG16_PCI_CLK_CTL6         0x0200
 419 #define FPGA_REG16_PCI_CLK_CTL7         0x0100
 420 #define FPGA_REG16_PCI_CLK_CTL8         0x0080
 421 #define FPGA_REG16_PCI_CLK_CTL9         0x0040
 422 #define FPGA_REG16_PCI_EXT_ARB0         0x0020
 423 #define FPGA_REG16_PCI_MODE_1           0x0010
 424 #define FPGA_REG16_PCI_TARGET_MODE      0x0008
 425 #define FPGA_REG16_PCI_INTP_MODE        0x0004
 426
 427 /* FB1 Divisor selection */
 428 #define FPGA_REG16_FB2_DIV_MASK         0x1000
 429 #define FPGA_REG16_FB2_DIV_LOW          0x0000
 430 #define FPGA_REG16_FB2_DIV_HIGH         0x1000
 431 /* FB2 Divisor selection */
 432 /* S3 switch on Board */
 433 #define FPGA_REG16_FB1_DIV_MASK         0x2000
 434 #define FPGA_REG16_FB1_DIV_LOW          0x0000
 435 #define FPGA_REG16_FB1_DIV_HIGH         0x2000
 436 /* PCI0 Clock Selection */
 437 /* S3 switch on Board */
 438 #define FPGA_REG16_PCI0_CLK_MASK        0x0c00
 439 #define FPGA_REG16_PCI0_CLK_33_33       0x0000
 440 #define FPGA_REG16_PCI0_CLK_66_66       0x0800
 441 #define FPGA_REG16_PCI0_CLK_100         0x0400
 442 #define FPGA_REG16_PCI0_CLK_133_33      0x0c00
 443 /* VCO Divisor selection */
 444 /* S3 switch on Board */
 445 #define FPGA_REG16_VCO_DIV_MASK         0xc000
 446 #define FPGA_REG16_VCO_DIV_4            0x0000
 447 #define FPGA_REG16_VCO_DIV_8            0x4000
 448 #define FPGA_REG16_VCO_DIV_6            0x8000
 449 #define FPGA_REG16_VCO_DIV_10           0xc000
 450 /* Master Clock Selection */
 451 /* S3, S4 switches on Board */
 452 #define FPGA_REG16_MASTER_CLK_MASK      0x01c0
 453 #define FPGA_REG16_MASTER_CLK_EXT       0x0000
 454 #define FPGA_REG16_MASTER_CLK_66_66     0x0040
 455 #define FPGA_REG16_MASTER_CLK_50        0x0080
 456 #define FPGA_REG16_MASTER_CLK_33_33     0x00c0
 457 #define FPGA_REG16_MASTER_CLK_25        0x0100
 458
 459 /*----------------------------------------------------------------------------+
 460 | PCI Miscellaneous
 461 +----------------------------------------------------------------------------*/
 462 #define FPGA_REG18      (FPGA_REG_BASE_ADDR+0x18)
 463
 464 #define FPGA_REG18_PCI_PRSNT1           0x8000
 465 #define FPGA_REG18_PCI_PRSNT2           0x4000
 466 #define FPGA_REG18_PCI_INTA             0x2000
 467 #define FPGA_REG18_PCI_SLOT0_INTP       0x1000
 468 #define FPGA_REG18_PCI_SLOT1_INTP       0x0800
 469 #define FPGA_REG18_PCI_SLOT2_INTP       0x0400
 470 #define FPGA_REG18_PCI_SLOT3_INTP       0x0200
 471 #define FPGA_REG18_PCI_PCI0_VC          0x0100
 472 #define FPGA_REG18_PCI_PCI0_VTH1        0x0080
 473 #define FPGA_REG18_PCI_PCI0_VTH2        0x0040
 474 #define FPGA_REG18_PCI_PCI0_VTH3        0x0020
 475
 476 /*----------------------------------------------------------------------------+
 477 | PCIe Miscellaneous
 478 +----------------------------------------------------------------------------*/
 479 #define FPGA_REG1A      (FPGA_REG_BASE_ADDR+0x1A)
 480
 481 #define FPGA_REG1A_PE0_GLED             0x8000
 482 #define FPGA_REG1A_PE1_GLED             0x4000
 483 #define FPGA_REG1A_PE2_GLED             0x2000
 484 #define FPGA_REG1A_PE0_YLED             0x1000
 485 #define FPGA_REG1A_PE1_YLED             0x0800
 486 #define FPGA_REG1A_PE2_YLED             0x0400
 487 #define FPGA_REG1A_PE0_PWRON            0x0200
 488 #define FPGA_REG1A_PE1_PWRON            0x0100
 489 #define FPGA_REG1A_PE2_PWRON            0x0080
 490 #define FPGA_REG1A_PE0_REFCLK_ENABLE    0x0040
 491 #define FPGA_REG1A_PE1_REFCLK_ENABLE    0x0020
 492 #define FPGA_REG1A_PE2_REFCLK_ENABLE    0x0010
 493 #define FPGA_REG1A_PE_SPREAD0           0x0008
 494 #define FPGA_REG1A_PE_SPREAD1           0x0004
 495 #define FPGA_REG1A_PE_SELSOURCE_0       0x0002
 496 #define FPGA_REG1A_PE_SELSOURCE_1       0x0001
 497
 498 /*----------------------------------------------------------------------------+
 499 | PCIe Miscellaneous
 500 +----------------------------------------------------------------------------*/
 501 #define FPGA_REG1C      (FPGA_REG_BASE_ADDR+0x1C)
 502
 503 #define FPGA_REG1C_PE0_ROOTPOINT        0x8000
 504 #define FPGA_REG1C_PE1_ENDPOINT         0x4000
 505 #define FPGA_REG1C_PE2_ENDPOINT         0x2000
 506 #define FPGA_REG1C_PE0_PRSNT            0x1000
 507 #define FPGA_REG1C_PE1_PRSNT            0x0800
 508 #define FPGA_REG1C_PE2_PRSNT            0x0400
 509 #define FPGA_REG1C_PE0_WAKE             0x0080
 510 #define FPGA_REG1C_PE1_WAKE             0x0040
 511 #define FPGA_REG1C_PE2_WAKE             0x0020
 512 #define FPGA_REG1C_PE0_PERST            0x0010
 513 #define FPGA_REG1C_PE1_PERST            0x0008
 514 #define FPGA_REG1C_PE2_PERST            0x0004
 515
 516 /*----------------------------------------------------------------------------+
 517 | Defines
 518 +----------------------------------------------------------------------------*/
 519 #define PERIOD_133_33MHZ        7500    /* 7,5ns */
 520 #define PERIOD_100_00MHZ        10000   /* 10ns */
 521 #define PERIOD_83_33MHZ         12000   /* 12ns */
 522 #define PERIOD_75_00MHZ         13333   /* 13,333ns */
 523 #define PERIOD_66_66MHZ         15000   /* 15ns */
 524 #define PERIOD_50_00MHZ         20000   /* 20ns */
 525 #define PERIOD_33_33MHZ         30000   /* 30ns */
 526 #define PERIOD_25_00MHZ         40000   /* 40ns */
 527
 528 /*---------------------------------------------------------------------------*/
 529
 530 #endif  /* __CONFIG_H */