include/configs/zylonite.h

   1 /*
   2  * (C) Copyright 2002
   3  * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
   4  *
   5  * (C) Copyright 2002
   6  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   7  * Marius Groeger <mgroeger@sysgo.de>
   8  *
   9  * Configuation settings for the Zylonite board.
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 #ifndef __CONFIG_H
  31 #define __CONFIG_H
  32
  33 /*
  34  * High Level Configuration Options
  35  * (easy to change)
  36  */
  37 #define CONFIG_CPU_MONAHANS     1       /* Intel Monahan CPU    */
  38 #define CONFIG_ZYLONITE         1       /* Zylonite board       */
  39
  40 /* #define CONFIG_LCD           1 */
  41 #ifdef CONFIG_LCD
  42 #define CONFIG_SHARP_LM8V31
  43 #endif
  44 /* #define CONFIG_MMC           1 */
  45 #define BOARD_LATE_INIT         1
  46
  47 #undef CONFIG_SKIP_RELOCATE_UBOOT
  48 #undef CONFIG_USE_IRQ                   /* we don't need IRQ/FIQ stuff */
  49
  50 /*
  51  * Size of malloc() pool
  52  */
  53 #define CFG_MALLOC_LEN      (CFG_ENV_SIZE + 128*1024)
  54 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
  55
  56 /*
  57  * Hardware drivers
  58  */
  59
  60 #undef TURN_ON_ETHERNET
  61 #ifdef TURN_ON_ETHERNET
  62 # define CONFIG_DRIVER_SMC91111 1
  63 # define CONFIG_SMC91111_BASE   0x14000300
  64 # define CONFIG_SMC91111_EXT_PHY
  65 # define CONFIG_SMC_USE_32_BIT
  66 # undef CONFIG_SMC_USE_IOFUNCS          /* just for use with the kernel */
  67 #endif
  68
  69 /*
  70  * select serial console configuration
  71  */
  72 #define CONFIG_FFUART          1
  73
  74 /* allow to overwrite serial and ethaddr */
  75 #define CONFIG_ENV_OVERWRITE
  76
  77 #define CONFIG_BAUDRATE         115200
  78
  79 #ifdef TURN_ON_ETHERNET
  80 # define CONFIG_COMMANDS        (CONFIG_CMD_DFL | CFG_CMD_PING)
  81 #else
  82 # define CONFIG_COMMANDS        ((CONFIG_CMD_DFL \
  83                                   | CFG_CMD_ENV \
  84                                   | CFG_CMD_NAND) \
  85                                  & ~(CFG_CMD_NET \
  86                                      | CFG_CMD_FLASH \
  87                                      | CFG_CMD_IMLS))
  88 #endif
  89
  90 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  91 #include <cmd_confdefs.h>
  92
  93 #define CONFIG_BOOTDELAY        -1
  94 #define CONFIG_ETHADDR          08:00:3e:26:0a:5b
  95 #define CONFIG_NETMASK          255.255.0.0
  96 #define CONFIG_IPADDR           192.168.0.21
  97 #define CONFIG_SERVERIP         192.168.0.250
  98 #define CONFIG_BOOTCOMMAND      "bootm 80000"
  99 #define CONFIG_BOOTARGS         "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
 100 #define CONFIG_CMDLINE_TAG
 101 #define CONFIG_TIMESTAMP
 102
 103 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 104 #define CONFIG_KGDB_BAUDRATE    230400          /* speed to run kgdb serial port */
 105 #define CONFIG_KGDB_SER_INDEX   2               /* which serial port to use */
 106 #endif
 107
 108 /*
 109  * Miscellaneous configurable options
 110  */
 111 #define CFG_HUSH_PARSER         1
 112 #define CFG_PROMPT_HUSH_PS2     "> "
 113
 114 #define CFG_LONGHELP                            /* undef to save memory         */
 115 #ifdef CFG_HUSH_PARSER
 116 #define CFG_PROMPT              "$ "            /* Monitor Command Prompt */
 117 #else
 118 #define CFG_PROMPT              "=> "           /* Monitor Command Prompt */
 119 #endif
 120 #define CFG_CBSIZE              256             /* Console I/O Buffer Size      */
 121 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 122 #define CFG_MAXARGS             16              /* max number of command args   */
 123 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 124 #define CFG_DEVICE_NULLDEV      1
 125
 126 #define CFG_MEMTEST_START       0x9c000000      /* memtest works on     */
 127 #define CFG_MEMTEST_END         0x9c400000      /* 4 ... 8 MB in DRAM   */
 128
 129 #undef  CFG_CLKS_IN_HZ          /* everything, incl board info, in Hz */
 130
 131 #define CFG_LOAD_ADDR   (CFG_DRAM_BASE + 0x8000) /* default load address */
 132
 133 #define CFG_HZ                  3250000         /* incrementer freq: 3.25 MHz */
 134
 135 /* Monahans Core Frequency */
 136 #define CFG_MONAHANS_RUN_MODE_OSC_RATIO         16 /* valid values: 8, 16, 24, 31 */
 137 #define CFG_MONAHANS_TURBO_RUN_MODE_RATIO       1  /* valid values: 1, 2 */
 138
 139                                                 /* valid baudrates */
 140 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 141
 142 /* #define CFG_MMC_BASE         0xF0000000 */
 143
 144 /*
 145  * Stack sizes
 146  *
 147  * The stack sizes are set up in start.S using the settings below
 148  */
 149 #define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
 150 #ifdef CONFIG_USE_IRQ
 151 #define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
 152 #define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
 153 #endif
 154
 155 /*
 156  * Physical Memory Map
 157  */
 158 #define CONFIG_NR_DRAM_BANKS    4          /* we have 2 banks of DRAM */
 159 #define PHYS_SDRAM_1            0xa0000000 /* SDRAM Bank #1 */
 160 #define PHYS_SDRAM_1_SIZE       0x04000000 /* 64 MB */
 161 #define PHYS_SDRAM_2            0xa4000000 /* SDRAM Bank #2 */
 162 #define PHYS_SDRAM_2_SIZE       0x00000000 /* 0 MB */
 163 #define PHYS_SDRAM_3            0xa8000000 /* SDRAM Bank #3 */
 164 #define PHYS_SDRAM_3_SIZE       0x00000000 /* 0 MB */
 165 #define PHYS_SDRAM_4            0xac000000 /* SDRAM Bank #4 */
 166 #define PHYS_SDRAM_4_SIZE       0x00000000 /* 0 MB */
 167
 168 #define CFG_DRAM_BASE           0x80000000 /* at CS0 */
 169 #define CFG_DRAM_SIZE           0x04000000 /* 64 MB Ram */
 170
 171 #undef CFG_SKIP_DRAM_SCRUB
 172
 173
 174 /*
 175  * NAND Flash
 176  */
 177 /* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */
 178 #define CONFIG_NEW_NAND_CODE
 179 #define CFG_NAND0_BASE          0x0
 180 #undef CFG_NAND1_BASE
 181
 182 #define CFG_NAND_BASE_LIST      { CFG_NAND0_BASE }
 183 #define CFG_MAX_NAND_DEVICE     1       /* Max number of NAND devices */
 184
 185 /* nand timeout values */
 186 #define CFG_NAND_PROG_ERASE_TO  3000
 187 #define CFG_NAND_OTHER_TO       100
 188 #define CFG_NAND_SENDCMD_RETRY  3
 189 #undef NAND_ALLOW_ERASE_ALL     /* Allow erasing bad blocks - don't use */
 190
 191 /* NAND Timing Parameters (in ns) */
 192 #define NAND_TIMING_tCH         10
 193 #define NAND_TIMING_tCS         0
 194 #define NAND_TIMING_tWH         20
 195 #define NAND_TIMING_tWP         40
 196
 197 #define NAND_TIMING_tRH         20
 198 #define NAND_TIMING_tRP         40
 199
 200 #define NAND_TIMING_tR          11123
 201 #define NAND_TIMING_tWHR        100
 202 #define NAND_TIMING_tAR         10
 203
 204 /* NAND debugging */
 205 #define CFG_DFC_DEBUG1 /* usefull */
 206 #undef CFG_DFC_DEBUG2  /* noisy */
 207 #undef CFG_DFC_DEBUG3  /* extremly noisy  */
 208
 209 #define CONFIG_MTD_DEBUG
 210 #define CONFIG_MTD_DEBUG_VERBOSE 1
 211
 212 #define ADDR_COLUMN             1
 213 #define ADDR_PAGE               2
 214 #define ADDR_COLUMN_PAGE        3
 215
 216 #define NAND_ChipID_UNKNOWN     0x00
 217 #define NAND_MAX_FLOORS         1
 218 #define NAND_MAX_CHIPS          1
 219
 220 #define CFG_NO_FLASH            1
 221
 222 #define CFG_ENV_IS_IN_NAND      1
 223 #define CFG_ENV_OFFSET          0x40000
 224 #define CFG_ENV_OFFSET_REDUND   0x44000
 225 #define CFG_ENV_SIZE            0x4000
 226
 227
 228 #endif  /* __CONFIG_H */