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1 /*
2 * (C) Copyright 2002
3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
4 *
5 * (C) Copyright 2002
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * Configuation settings for the Zylonite board.
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30 #ifndef __CONFIG_H
31 #define __CONFIG_H
32
33 /*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37 #define CONFIG_CPU_MONAHANS 1 /* Intel Monahan CPU */
38 #define CONFIG_ZYLONITE 1 /* Zylonite board */
39
40 /* #define CONFIG_LCD 1 */
41 #ifdef CONFIG_LCD
42 #define CONFIG_SHARP_LM8V31
43 #endif
44 /* #define CONFIG_MMC 1 */
45 #define BOARD_LATE_INIT 1
46
47 #undef CONFIG_SKIP_RELOCATE_UBOOT
48 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
49
50 /*
51 * Size of malloc() pool
52 */
53 #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
54 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
55
56 /*
57 * Hardware drivers
58 */
59
60 #undef TURN_ON_ETHERNET
61 #ifdef TURN_ON_ETHERNET
62 # define CONFIG_DRIVER_SMC91111 1
63 # define CONFIG_SMC91111_BASE 0x14000300
64 # define CONFIG_SMC91111_EXT_PHY
65 # define CONFIG_SMC_USE_32_BIT
66 # undef CONFIG_SMC_USE_IOFUNCS /* just for use with the kernel */
67 #endif
68
69 /*
70 * select serial console configuration
71 */
72 #define CONFIG_FFUART 1
73
74 /* allow to overwrite serial and ethaddr */
75 #define CONFIG_ENV_OVERWRITE
76
77 #define CONFIG_BAUDRATE 115200
78
79
80 /*
81 * Command line configuration.
82 */
83 #include <config_cmd_default.h>
84
85 #ifdef TURN_ON_ETHERNET
86 #define CONFIG_CMD_PING
87 #else
88 #define CONFIG_CMD_ENV
89 #define CONFIG_CMD_NAND
90
91 #undef CONFIG_CMD_NET
92 #undef CONFIG_CMD_FLASH
93 #undef CONFIG_CMD_IMLS
94 #endif
95
96
97 #define CONFIG_BOOTDELAY -1
98 #define CONFIG_ETHADDR 08:00:3e:26:0a:5b
99 #define CONFIG_NETMASK 255.255.0.0
100 #define CONFIG_IPADDR 192.168.0.21
101 #define CONFIG_SERVERIP 192.168.0.250
102 #define CONFIG_BOOTCOMMAND "bootm 80000"
103 #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
104 #define CONFIG_CMDLINE_TAG
105 #define CONFIG_TIMESTAMP
106
107 #if defined(CONFIG_CMD_KGDB)
108 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
109 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
110 #endif
111
112 /*
113 * Miscellaneous configurable options
114 */
115 #define CFG_HUSH_PARSER 1
116 #define CFG_PROMPT_HUSH_PS2 "> "
117
118 #define CFG_LONGHELP /* undef to save memory */
119 #ifdef CFG_HUSH_PARSER
120 #define CFG_PROMPT "$ " /* Monitor Command Prompt */
121 #else
122 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
123 #endif
124 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
125 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
126 #define CFG_MAXARGS 16 /* max number of command args */
127 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
128 #define CFG_DEVICE_NULLDEV 1
129
130 #define CFG_MEMTEST_START 0x9c000000 /* memtest works on */
131 #define CFG_MEMTEST_END 0x9c400000 /* 4 ... 8 MB in DRAM */
132
133 #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
134
135 #define CFG_LOAD_ADDR (CFG_DRAM_BASE + 0x8000) /* default load address */
136
137 #define CFG_HZ 3250000 /* incrementer freq: 3.25 MHz */
138
139 /* Monahans Core Frequency */
140 #define CFG_MONAHANS_RUN_MODE_OSC_RATIO 16 /* valid values: 8, 16, 24, 31 */
141 #define CFG_MONAHANS_TURBO_RUN_MODE_RATIO 1 /* valid values: 1, 2 */
142
143 /* valid baudrates */
144 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
145
146 /* #define CFG_MMC_BASE 0xF0000000 */
147
148 /*
149 * Stack sizes
150 *
151 * The stack sizes are set up in start.S using the settings below
152 */
153 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
154 #ifdef CONFIG_USE_IRQ
155 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
156 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
157 #endif
158
159 /*
160 * Physical Memory Map
161 */
162 #define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
163 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
164 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
165 #define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
166 #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
167 #define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
168 #define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
169 #define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
170 #define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
171
172 #define CFG_DRAM_BASE 0x80000000 /* at CS0 */
173 #define CFG_DRAM_SIZE 0x04000000 /* 64 MB Ram */
174
175 #undef CFG_SKIP_DRAM_SCRUB
176
177
178 /*
179 * NAND Flash
180 */
181 #define CONFIG_NEW_NAND_CODE
182 #define CFG_NAND0_BASE 0x0
183 #undef CFG_NAND1_BASE
184
185 #define CFG_NAND_BASE_LIST { CFG_NAND0_BASE }
186 #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
187
188 /* nand timeout values */
189 #define CFG_NAND_PROG_ERASE_TO 3000
190 #define CFG_NAND_OTHER_TO 100
191 #define CFG_NAND_SENDCMD_RETRY 3
192 #undef NAND_ALLOW_ERASE_ALL /* Allow erasing bad blocks - don't use */
193
194 /* NAND Timing Parameters (in ns) */
195 #define NAND_TIMING_tCH 10
196 #define NAND_TIMING_tCS 0
197 #define NAND_TIMING_tWH 20
198 #define NAND_TIMING_tWP 40
199
200 #define NAND_TIMING_tRH 20
201 #define NAND_TIMING_tRP 40
202
203 #define NAND_TIMING_tR 11123
204 #define NAND_TIMING_tWHR 100
205 #define NAND_TIMING_tAR 10
206
207 /* NAND debugging */
208 #define CFG_DFC_DEBUG1 /* usefull */
209 #undef CFG_DFC_DEBUG2 /* noisy */
210 #undef CFG_DFC_DEBUG3 /* extremly noisy */
211
212 #define CONFIG_MTD_DEBUG
213 #define CONFIG_MTD_DEBUG_VERBOSE 1
214
215 #define ADDR_COLUMN 1
216 #define ADDR_PAGE 2
217 #define ADDR_COLUMN_PAGE 3
218
219 #define NAND_ChipID_UNKNOWN 0x00
220 #define NAND_MAX_FLOORS 1
221 #define NAND_MAX_CHIPS 1
222
223 #define CFG_NO_FLASH 1
224
225 #define CFG_ENV_IS_IN_NAND 1
226 #define CFG_ENV_OFFSET 0x40000
227 #define CFG_ENV_OFFSET_REDUND 0x44000
228 #define CFG_ENV_SIZE 0x4000
229
230
231 #endif /* __CONFIG_H */