include/gdb/sim-d10v.h

   1 /* This file defines the interface between the d10v simulator and gdb.
   2
   3    Copyright 1999, 2002, 2007, 2008, 2009, 2010, 2011
   4    Free Software Foundation, Inc.
   5
   6    This file is part of GDB.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 #if !defined (SIM_D10V_H)
  22 #define SIM_D10V_H
  23
  24 #ifdef __cplusplus
  25 extern "C" { // }
  26 #endif
  27
  28 /* GDB interprets addresses as:
  29
  30    0x00xxxxxx: Physical unified memory segment     (Unified memory)
  31    0x01xxxxxx: Physical instruction memory segment (On-chip insn memory)
  32    0x02xxxxxx: Physical data memory segment        (On-chip data memory)
  33    0x10xxxxxx: Logical data address segment        (DMAP translated memory)
  34    0x11xxxxxx: Logical instruction address segment (IMAP translated memory)
  35
  36    The remote d10v board interprets addresses as:
  37
  38    0x00xxxxxx: Physical unified memory segment     (Unified memory)
  39    0x01xxxxxx: Physical instruction memory segment (On-chip insn memory)
  40    0x02xxxxxx: Physical data memory segment        (On-chip data memory)
  41
  42    The following translate a virtual DMAP/IMAP offset into a physical
  43    memory segment assigning the translated address to PHYS.  Since a
  44    memory access may cross a page boundrary the number of bytes for
  45    which the translation is applicable (or 0 for an invalid virtual
  46    offset) is returned. */
  47
  48 enum
  49   {
  50     SIM_D10V_MEMORY_UNIFIED = 0x00000000,
  51     SIM_D10V_MEMORY_INSN = 0x01000000,
  52     SIM_D10V_MEMORY_DATA = 0x02000000,
  53     SIM_D10V_MEMORY_DMAP = 0x10000000,
  54     SIM_D10V_MEMORY_IMAP = 0x11000000
  55   };
  56
  57 extern unsigned long sim_d10v_translate_dmap_addr
  58   (unsigned long offset,
  59    int nr_bytes,
  60    unsigned long *phys,
  61    void *regcache,
  62    unsigned long (*dmap_register) (void *regcache, int reg_nr));
  63
  64 extern unsigned long sim_d10v_translate_imap_addr
  65   (unsigned long offset,
  66    int nr_bytes,
  67    unsigned long *phys,
  68    void *regcache,
  69    unsigned long (*imap_register) (void *regcache, int reg_nr));
  70
  71 extern unsigned long sim_d10v_translate_addr
  72   (unsigned long vaddr,
  73    int nr_bytes,
  74    unsigned long *phys,
  75    void *regcache,
  76    unsigned long (*dmap_register) (void *regcache, int reg_nr),
  77    unsigned long (*imap_register) (void *regcache, int reg_nr));
  78
  79
  80 /* The simulator makes use of the following register information. */
  81
  82 enum sim_d10v_regs
  83 {
  84   SIM_D10V_R0_REGNUM,
  85   SIM_D10V_R1_REGNUM,
  86   SIM_D10V_R2_REGNUM,
  87   SIM_D10V_R3_REGNUM,
  88   SIM_D10V_R4_REGNUM,
  89   SIM_D10V_R5_REGNUM,
  90   SIM_D10V_R6_REGNUM,
  91   SIM_D10V_R7_REGNUM,
  92   SIM_D10V_R8_REGNUM,
  93   SIM_D10V_R9_REGNUM,
  94   SIM_D10V_R10_REGNUM,
  95   SIM_D10V_R11_REGNUM,
  96   SIM_D10V_R12_REGNUM,
  97   SIM_D10V_R13_REGNUM,
  98   SIM_D10V_R14_REGNUM,
  99   SIM_D10V_R15_REGNUM,
 100   SIM_D10V_CR0_REGNUM,
 101   SIM_D10V_CR1_REGNUM,
 102   SIM_D10V_CR2_REGNUM,
 103   SIM_D10V_CR3_REGNUM,
 104   SIM_D10V_CR4_REGNUM,
 105   SIM_D10V_CR5_REGNUM,
 106   SIM_D10V_CR6_REGNUM,
 107   SIM_D10V_CR7_REGNUM,
 108   SIM_D10V_CR8_REGNUM,
 109   SIM_D10V_CR9_REGNUM,
 110   SIM_D10V_CR10_REGNUM,
 111   SIM_D10V_CR11_REGNUM,
 112   SIM_D10V_CR12_REGNUM,
 113   SIM_D10V_CR13_REGNUM,
 114   SIM_D10V_CR14_REGNUM,
 115   SIM_D10V_CR15_REGNUM,
 116   SIM_D10V_A0_REGNUM,
 117   SIM_D10V_A1_REGNUM,
 118   SIM_D10V_SPI_REGNUM,
 119   SIM_D10V_SPU_REGNUM,
 120   SIM_D10V_IMAP0_REGNUM,
 121   SIM_D10V_IMAP1_REGNUM,
 122   SIM_D10V_DMAP0_REGNUM,
 123   SIM_D10V_DMAP1_REGNUM,
 124   SIM_D10V_DMAP2_REGNUM,
 125   SIM_D10V_DMAP3_REGNUM,
 126   SIM_D10V_TS2_DMAP_REGNUM
 127 };
 128
 129 enum
 130 {
 131   SIM_D10V_NR_R_REGS = 16,
 132   SIM_D10V_NR_A_REGS = 2,
 133   SIM_D10V_NR_IMAP_REGS = 2,
 134   SIM_D10V_NR_DMAP_REGS = 4,
 135   SIM_D10V_NR_CR_REGS = 16
 136 };
 137
 138 #ifdef __cplusplus
 139 }
 140 #endif
 141
 142 #endif