include/hw/dma/pl080.h

   1 /*
   2  * ARM PrimeCell PL080/PL081 DMA controller
   3  *
   4  * Copyright (c) 2006 CodeSourcery.
   5  * Copyright (c) 2018 Linaro Limited
   6  * Written by Paul Brook, Peter Maydell
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 or
  10  * (at your option) any later version.
  11  */
  12
  13 /* This is a model of the Arm PrimeCell PL080/PL081 DMA controller:
  14  * The PL080 TRM is:
  15  * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0196g/DDI0196.pdf
  16  * and the PL081 TRM is:
  17  * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0218e/DDI0218.pdf
  18  *
  19  * QEMU interface:
  20  * + sysbus IRQ 0: DMACINTR combined interrupt line
  21  * + sysbus IRQ 1: DMACINTERR error interrupt request
  22  * + sysbus IRQ 2: DMACINTTC count interrupt request
  23  * + sysbus MMIO region 0: MemoryRegion for the device's registers
  24  * + QOM property "downstream": MemoryRegion defining where DMA
  25  *   bus master transactions are made
  26  */
  27
  28 #ifndef HW_DMA_PL080_H
  29 #define HW_DMA_PL080_H
  30
  31 #include "hw/sysbus.h"
  32 #include "qom/object.h"
  33
  34 #define PL080_MAX_CHANNELS 8
  35
  36 typedef struct {
  37     uint32_t src;
  38     uint32_t dest;
  39     uint32_t lli;
  40     uint32_t ctrl;
  41     uint32_t conf;
  42 } pl080_channel;
  43
  44 #define TYPE_PL080 "pl080"
  45 #define TYPE_PL081 "pl081"
  46 OBJECT_DECLARE_SIMPLE_TYPE(PL080State, PL080)
  47
  48 struct PL080State {
  49     SysBusDevice parent_obj;
  50
  51     MemoryRegion iomem;
  52     uint8_t tc_int;
  53     uint8_t tc_mask;
  54     uint8_t err_int;
  55     uint8_t err_mask;
  56     uint32_t conf;
  57     uint32_t sync;
  58     uint32_t req_single;
  59     uint32_t req_burst;
  60     pl080_channel chan[PL080_MAX_CHANNELS];
  61     int nchannels;
  62     /* Flag to avoid recursive DMA invocations.  */
  63     int running;
  64     qemu_irq irq;
  65     qemu_irq interr;
  66     qemu_irq inttc;
  67
  68     MemoryRegion *downstream;
  69     AddressSpace downstream_as;
  70 };
  71
  72 #endif