include/hw/intc/imx_avic.h

   1 /*
   2  * i.MX31 Vectored Interrupt Controller
   3  *
   4  * Note this is NOT the PL192 provided by ARM, but
   5  * a custom implementation by Freescale.
   6  *
   7  * Copyright (c) 2008 OKL
   8  * Copyright (c) 2011 NICTA Pty Ltd
   9  * Originally written by Hans Jiang
  10  * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
  11  *
  12  * This code is licensed under the GPL version 2 or later.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  * TODO: implement vectors.
  16  */
  17 #ifndef IMX_AVIC_H
  18 #define IMX_AVIC_H
  19
  20 #include "hw/sysbus.h"
  21 #include "qom/object.h"
  22
  23 #define TYPE_IMX_AVIC "imx.avic"
  24 typedef struct IMXAVICState IMXAVICState;
  25 #define IMX_AVIC(obj) OBJECT_CHECK(IMXAVICState, (obj), TYPE_IMX_AVIC)
  26
  27 #define IMX_AVIC_NUM_IRQS 64
  28
  29 /* Interrupt Control Bits */
  30 #define ABFLAG (1<<25)
  31 #define ABFEN  (1<<24)
  32 #define NIDIS  (1<<22) /* Normal Interrupt disable */
  33 #define FIDIS  (1<<21) /* Fast interrupt disable */
  34 #define NIAD   (1<<20) /* Normal Interrupt Arbiter Rise ARM level */
  35 #define FIAD   (1<<19) /* Fast Interrupt Arbiter Rise ARM level */
  36 #define NM     (1<<18) /* Normal interrupt mode */
  37
  38 #define PRIO_PER_WORD (sizeof(uint32_t) * 8 / 4)
  39 #define PRIO_WORDS (IMX_AVIC_NUM_IRQS/PRIO_PER_WORD)
  40
  41 struct IMXAVICState {
  42     /*< private >*/
  43     SysBusDevice parent_obj;
  44
  45     /*< public >*/
  46     MemoryRegion iomem;
  47     uint64_t pending;
  48     uint64_t enabled;
  49     uint64_t is_fiq;
  50     uint32_t intcntl;
  51     uint32_t intmask;
  52     qemu_irq irq;
  53     qemu_irq fiq;
  54     uint32_t prio[PRIO_WORDS]; /* Priorities are 4-bits each */
  55 };
  56
  57 #endif /* IMX_AVIC_H */