4 * Copyright (c) 2004 Fabrice Bellard
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
20 * split out pci bus specific stuff from pci.[hc] to pci_bridge.[hc]
21 * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
22 * VA Linux Systems Japan K.K.
26 #ifndef QEMU_PCI_BRIDGE_H
27 #define QEMU_PCI_BRIDGE_H
29 #include "hw/pci/pci.h"
30 #include "hw/pci/pci_bus.h"
31 #include "qom/object.h"
33 typedef struct PCIBridgeWindows PCIBridgeWindows
;
36 * Aliases for each of the address space windows that the bridge
37 * can forward. Mapped into the bridge's parent's address space,
40 struct PCIBridgeWindows
{
41 MemoryRegion alias_pref_mem
;
42 MemoryRegion alias_mem
;
43 MemoryRegion alias_io
;
45 * When bridge control VGA forwarding is enabled, bridges will
46 * provide positive decode on the PCI VGA defined I/O port and
47 * MMIO ranges. When enabled forwarding is only qualified on the
48 * I/O and memory enable bits in the bridge command register.
50 MemoryRegion alias_vga
[QEMU_PCI_VGA_NUM_REGIONS
];
53 #define TYPE_PCI_BRIDGE "base-pci-bridge"
54 OBJECT_DECLARE_SIMPLE_TYPE(PCIBridge
, PCI_BRIDGE
)
64 * Memory regions for the bridge's address spaces. These regions are not
65 * directly added to system_memory/system_io or its descendants.
66 * Bridge's secondary bus points to these, so that devices
67 * under the bridge see these regions as its address spaces.
68 * The regions are as large as the entire address space -
69 * they don't take into account any windows.
71 MemoryRegion address_space_mem
;
72 MemoryRegion address_space_io
;
74 PCIBridgeWindows
*windows
;
76 pci_map_irq_fn map_irq
;
80 #define PCI_BRIDGE_DEV_PROP_CHASSIS_NR "chassis_nr"
81 #define PCI_BRIDGE_DEV_PROP_MSI "msi"
82 #define PCI_BRIDGE_DEV_PROP_SHPC "shpc"
84 int pci_bridge_ssvid_init(PCIDevice
*dev
, uint8_t offset
,
85 uint16_t svid
, uint16_t ssid
,
88 PCIDevice
*pci_bridge_get_device(PCIBus
*bus
);
89 PCIBus
*pci_bridge_get_sec_bus(PCIBridge
*br
);
91 pcibus_t
pci_bridge_get_base(const PCIDevice
*bridge
, uint8_t type
);
92 pcibus_t
pci_bridge_get_limit(const PCIDevice
*bridge
, uint8_t type
);
94 void pci_bridge_update_mappings(PCIBridge
*br
);
95 void pci_bridge_write_config(PCIDevice
*d
,
96 uint32_t address
, uint32_t val
, int len
);
97 void pci_bridge_disable_base_limit(PCIDevice
*dev
);
98 void pci_bridge_reset(DeviceState
*qdev
);
100 void pci_bridge_initfn(PCIDevice
*pci_dev
, const char *typename
);
101 void pci_bridge_exitfn(PCIDevice
*pci_dev
);
103 void pci_bridge_dev_plug_cb(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
105 void pci_bridge_dev_unplug_cb(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
107 void pci_bridge_dev_unplug_request_cb(HotplugHandler
*hotplug_dev
,
108 DeviceState
*dev
, Error
**errp
);
111 * before qdev initialization(qdev_init()), this function sets bus_name and
112 * map_irq callback which are necessary for pci_bridge_initfn() to
115 void pci_bridge_map_irq(PCIBridge
*br
, const char* bus_name
,
116 pci_map_irq_fn map_irq
);
118 /* TODO: add this define to pci_regs.h in linux and then in qemu. */
119 #define PCI_BRIDGE_CTL_VGA_16BIT 0x10 /* VGA 16-bit decode */
120 #define PCI_BRIDGE_CTL_DISCARD 0x100 /* Primary discard timer */
121 #define PCI_BRIDGE_CTL_SEC_DISCARD 0x200 /* Secondary discard timer */
122 #define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */
123 #define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */
125 typedef struct PCIBridgeQemuCap
{
126 uint8_t id
; /* Standard PCI capability header field */
127 uint8_t next
; /* Standard PCI capability header field */
128 uint8_t len
; /* Standard PCI vendor-specific capability header field */
129 uint8_t type
; /* Red Hat vendor-specific capability type.
130 Types are defined with REDHAT_PCI_CAP_ prefix */
132 uint32_t bus_res
; /* Minimum number of buses to reserve */
133 uint64_t io
; /* IO space to reserve */
134 uint32_t mem
; /* Non-prefetchable memory to reserve */
135 /* At most one of the following two fields may be set to a value
136 * different from -1 */
137 uint32_t mem_pref_32
; /* Prefetchable memory to reserve (32-bit MMIO) */
138 uint64_t mem_pref_64
; /* Prefetchable memory to reserve (64-bit MMIO) */
141 #define REDHAT_PCI_CAP_RESOURCE_RESERVE 1
144 * PCI BUS/IO/MEM/PREFMEM additional resources recorded as a
145 * capability in PCI configuration space to reserve on firmware init.
147 typedef struct PCIResReserve
{
150 uint64_t mem_non_pref
;
151 uint64_t mem_pref_32
;
152 uint64_t mem_pref_64
;
155 int pci_bridge_qemu_reserve_cap_init(PCIDevice
*dev
, int cap_offset
,
156 PCIResReserve res_reserve
, Error
**errp
);
158 #endif /* QEMU_PCI_BRIDGE_H */