include/hw/ppc/xive.h

   1 /*
   2  * QEMU PowerPC XIVE interrupt controller model
   3  *
   4  *
   5  * The POWER9 processor comes with a new interrupt controller, called
   6  * XIVE as "eXternal Interrupt Virtualization Engine".
   7  *
   8  * = Overall architecture
   9  *
  10  *
  11  *              XIVE Interrupt Controller
  12  *              +------------------------------------+      IPIs
  13  *              | +---------+ +---------+ +--------+ |    +-------+
  14  *              | |VC       | |CQ       | |PC      |----> | CORES |
  15  *              | |     esb | |         | |        |----> |       |
  16  *              | |     eas | |  Bridge | |   tctx |----> |       |
  17  *              | |SC   end | |         | |    nvt | |    |       |
  18  *  +------+    | +---------+ +----+----+ +--------+ |    +-+-+-+-+
  19  *  | RAM  |    +------------------|-----------------+      | | |
  20  *  |      |                       |                        | | |
  21  *  |      |                       |                        | | |
  22  *  |      |  +--------------------v------------------------v-v-v--+    other
  23  *  |      <--+                     Power Bus                      +--> chips
  24  *  |  esb |  +---------+-----------------------+------------------+
  25  *  |  eas |            |                       |
  26  *  |  end |         +--|------+                |
  27  *  |  nvt |       +----+----+ |           +----+----+
  28  *  +------+       |SC       | |           |SC       |
  29  *                 |         | |           |         |
  30  *                 | PQ-bits | |           | PQ-bits |
  31  *                 | local   |-+           |  in VC  |
  32  *                 +---------+             +---------+
  33  *                    PCIe                 NX,NPU,CAPI
  34  *
  35  *                   SC: Source Controller (aka. IVSE)
  36  *                   VC: Virtualization Controller (aka. IVRE)
  37  *                   PC: Presentation Controller (aka. IVPE)
  38  *                   CQ: Common Queue (Bridge)
  39  *
  40  *              PQ-bits: 2 bits source state machine (P:pending Q:queued)
  41  *                  esb: Event State Buffer (Array of PQ bits in an IVSE)
  42  *                  eas: Event Assignment Structure
  43  *                  end: Event Notification Descriptor
  44  *                  nvt: Notification Virtual Target
  45  *                 tctx: Thread interrupt Context
  46  *
  47  *
  48  * The XIVE IC is composed of three sub-engines :
  49  *
  50  * - Interrupt Virtualization Source Engine (IVSE), or Source
  51  *   Controller (SC). These are found in PCI PHBs, in the PSI host
  52  *   bridge controller, but also inside the main controller for the
  53  *   core IPIs and other sub-chips (NX, CAP, NPU) of the
  54  *   chip/processor. They are configured to feed the IVRE with events.
  55  *
  56  * - Interrupt Virtualization Routing Engine (IVRE) or Virtualization
  57  *   Controller (VC). Its job is to match an event source with an
  58  *   Event Notification Descriptor (END).
  59  *
  60  * - Interrupt Virtualization Presentation Engine (IVPE) or
  61  *   Presentation Controller (PC). It maintains the interrupt context
  62  *   state of each thread and handles the delivery of the external
  63  *   exception to the thread.
  64  *
  65  * In XIVE 1.0, the sub-engines used to be referred as:
  66  *
  67  *   SC     Source Controller
  68  *   VC     Virtualization Controller
  69  *   PC     Presentation Controller
  70  *   CQ     Common Queue (PowerBUS Bridge)
  71  *
  72  *
  73  * = XIVE internal tables
  74  *
  75  * Each of the sub-engines uses a set of tables to redirect exceptions
  76  * from event sources to CPU threads.
  77  *
  78  *                                           +-------+
  79  *   User or OS                              |  EQ   |
  80  *       or                          +------>|entries|
  81  *   Hypervisor                      |       |  ..   |
  82  *     Memory                        |       +-------+
  83  *                                   |           ^
  84  *                                   |           |
  85  *              +-------------------------------------------------+
  86  *                                   |           |
  87  *   Hypervisor      +------+    +---+--+    +---+--+   +------+
  88  *     Memory        | ESB  |    | EAT  |    | ENDT |   | NVTT |
  89  *    (skiboot)      +----+-+    +----+-+    +----+-+   +------+
  90  *                     ^  |        ^  |        ^  |       ^
  91  *                     |  |        |  |        |  |       |
  92  *              +-------------------------------------------------+
  93  *                     |  |        |  |        |  |       |
  94  *                     |  |        |  |        |  |       |
  95  *                +----|--|--------|--|--------|--|-+   +-|-----+    +------+
  96  *                |    |  |        |  |        |  | |   | | tctx|    |Thread|
  97  *   IPI or   --> |    +  v        +  v        +  v |---| +  .. |----->     |
  98  *  HW events --> |                                 |   |       |    |      |
  99  *    IVSE        |             IVRE                |   | IVPE  |    +------+
 100  *                +---------------------------------+   +-------+
 101  *
 102  *
 103  *
 104  * The IVSE have a 2-bits state machine, P for pending and Q for queued,
 105  * for each source that allows events to be triggered. They are stored in
 106  * an Event State Buffer (ESB) array and can be controlled by MMIOs.
 107  *
 108  * If the event is let through, the IVRE looks up in the Event Assignment
 109  * Structure (EAS) table for an Event Notification Descriptor (END)
 110  * configured for the source. Each Event Notification Descriptor defines
 111  * a notification path to a CPU and an in-memory Event Queue, in which
 112  * will be enqueued an EQ data for the OS to pull.
 113  *
 114  * The IVPE determines if a Notification Virtual Target (NVT) can
 115  * handle the event by scanning the thread contexts of the VCPUs
 116  * dispatched on the processor HW threads. It maintains the state of
 117  * the thread interrupt context (TCTX) of each thread in a NVT table.
 118  *
 119  * = Acronyms
 120  *
 121  *          Description                     In XIVE 1.0, used to be referred as
 122  *
 123  *   EAS    Event Assignment Structure      IVE   Interrupt Virt. Entry
 124  *   EAT    Event Assignment Table          IVT   Interrupt Virt. Table
 125  *   ENDT   Event Notif. Descriptor Table   EQDT  Event Queue Desc. Table
 126  *   EQ     Event Queue                     same
 127  *   ESB    Event State Buffer              SBE   State Bit Entry
 128  *   NVT    Notif. Virtual Target           VPD   Virtual Processor Desc.
 129  *   NVTT   Notif. Virtual Target Table     VPDT  Virtual Processor Desc. Table
 130  *   TCTX   Thread interrupt Context
 131  *
 132  *
 133  * Copyright (c) 2017-2018, IBM Corporation.
 134  *
 135  * This code is licensed under the GPL version 2 or later. See the
 136  * COPYING file in the top-level directory.
 137  *
 138  */
 139
 140 #ifndef PPC_XIVE_H
 141 #define PPC_XIVE_H
 142
 143 #include "sysemu/kvm.h"
 144 #include "hw/sysbus.h"
 145 #include "hw/ppc/xive_regs.h"
 146 #include "qom/object.h"
 147
 148 /*
 149  * XIVE Notifier (Interface between Source and Router)
 150  */
 151
 152 typedef struct XiveNotifier XiveNotifier;
 153
 154 #define TYPE_XIVE_NOTIFIER "xive-notifier"
 155 #define XIVE_NOTIFIER(obj)                                     \
 156     INTERFACE_CHECK(XiveNotifier, (obj), TYPE_XIVE_NOTIFIER)
 157 typedef struct XiveNotifierClass XiveNotifierClass;
 158 DECLARE_CLASS_CHECKERS(XiveNotifierClass, XIVE_NOTIFIER,
 159                        TYPE_XIVE_NOTIFIER)
 160
 161 struct XiveNotifierClass {
 162     InterfaceClass parent;
 163     void (*notify)(XiveNotifier *xn, uint32_t lisn);
 164 };
 165
 166 /*
 167  * XIVE Interrupt Source
 168  */
 169
 170 #define TYPE_XIVE_SOURCE "xive-source"
 171 typedef struct XiveSource XiveSource;
 172 DECLARE_INSTANCE_CHECKER(XiveSource, XIVE_SOURCE,
 173                          TYPE_XIVE_SOURCE)
 174
 175 /*
 176  * XIVE Interrupt Source characteristics, which define how the ESB are
 177  * controlled.
 178  */
 179 #define XIVE_SRC_H_INT_ESB     0x1 /* ESB managed with hcall H_INT_ESB */
 180 #define XIVE_SRC_STORE_EOI     0x2 /* Store EOI supported */
 181
 182 struct XiveSource {
 183     DeviceState parent;
 184
 185     /* IRQs */
 186     uint32_t        nr_irqs;
 187     unsigned long   *lsi_map;
 188
 189     /* PQ bits and LSI assertion bit */
 190     uint8_t         *status;
 191
 192     /* ESB memory region */
 193     uint64_t        esb_flags;
 194     uint32_t        esb_shift;
 195     MemoryRegion    esb_mmio;
 196     MemoryRegion    esb_mmio_emulated;
 197
 198     /* KVM support */
 199     void            *esb_mmap;
 200     MemoryRegion    esb_mmio_kvm;
 201
 202     XiveNotifier    *xive;
 203 };
 204
 205 /*
 206  * ESB MMIO setting. Can be one page, for both source triggering and
 207  * source management, or two different pages. See below for magic
 208  * values.
 209  */
 210 #define XIVE_ESB_4K          12 /* PSI HB only */
 211 #define XIVE_ESB_4K_2PAGE    13
 212 #define XIVE_ESB_64K         16
 213 #define XIVE_ESB_64K_2PAGE   17
 214
 215 static inline bool xive_source_esb_has_2page(XiveSource *xsrc)
 216 {
 217     return xsrc->esb_shift == XIVE_ESB_64K_2PAGE ||
 218         xsrc->esb_shift == XIVE_ESB_4K_2PAGE;
 219 }
 220
 221 static inline size_t xive_source_esb_len(XiveSource *xsrc)
 222 {
 223     return (1ull << xsrc->esb_shift) * xsrc->nr_irqs;
 224 }
 225
 226 /* The trigger page is always the first/even page */
 227 static inline hwaddr xive_source_esb_page(XiveSource *xsrc, uint32_t srcno)
 228 {
 229     assert(srcno < xsrc->nr_irqs);
 230     return (1ull << xsrc->esb_shift) * srcno;
 231 }
 232
 233 /* In a two pages ESB MMIO setting, the odd page is for management */
 234 static inline hwaddr xive_source_esb_mgmt(XiveSource *xsrc, int srcno)
 235 {
 236     hwaddr addr = xive_source_esb_page(xsrc, srcno);
 237
 238     if (xive_source_esb_has_2page(xsrc)) {
 239         addr += (1 << (xsrc->esb_shift - 1));
 240     }
 241
 242     return addr;
 243 }
 244
 245 /*
 246  * Each interrupt source has a 2-bit state machine which can be
 247  * controlled by MMIO. P indicates that an interrupt is pending (has
 248  * been sent to a queue and is waiting for an EOI). Q indicates that
 249  * the interrupt has been triggered while pending.
 250  *
 251  * This acts as a coalescing mechanism in order to guarantee that a
 252  * given interrupt only occurs at most once in a queue.
 253  *
 254  * When doing an EOI, the Q bit will indicate if the interrupt
 255  * needs to be re-triggered.
 256  */
 257 #define XIVE_STATUS_ASSERTED  0x4  /* Extra bit for LSI */
 258 #define XIVE_ESB_VAL_P        0x2
 259 #define XIVE_ESB_VAL_Q        0x1
 260
 261 #define XIVE_ESB_RESET        0x0
 262 #define XIVE_ESB_PENDING      XIVE_ESB_VAL_P
 263 #define XIVE_ESB_QUEUED       (XIVE_ESB_VAL_P | XIVE_ESB_VAL_Q)
 264 #define XIVE_ESB_OFF          XIVE_ESB_VAL_Q
 265
 266 /*
 267  * "magic" Event State Buffer (ESB) MMIO offsets.
 268  *
 269  * The following offsets into the ESB MMIO allow to read or manipulate
 270  * the PQ bits. They must be used with an 8-byte load instruction.
 271  * They all return the previous state of the interrupt (atomically).
 272  *
 273  * Additionally, some ESB pages support doing an EOI via a store and
 274  * some ESBs support doing a trigger via a separate trigger page.
 275  */
 276 #define XIVE_ESB_STORE_EOI      0x400 /* Store */
 277 #define XIVE_ESB_LOAD_EOI       0x000 /* Load */
 278 #define XIVE_ESB_GET            0x800 /* Load */
 279 #define XIVE_ESB_SET_PQ_00      0xc00 /* Load */
 280 #define XIVE_ESB_SET_PQ_01      0xd00 /* Load */
 281 #define XIVE_ESB_SET_PQ_10      0xe00 /* Load */
 282 #define XIVE_ESB_SET_PQ_11      0xf00 /* Load */
 283
 284 uint8_t xive_source_esb_get(XiveSource *xsrc, uint32_t srcno);
 285 uint8_t xive_source_esb_set(XiveSource *xsrc, uint32_t srcno, uint8_t pq);
 286
 287 void xive_source_pic_print_info(XiveSource *xsrc, uint32_t offset,
 288                                 Monitor *mon);
 289
 290 static inline bool xive_source_irq_is_lsi(XiveSource *xsrc, uint32_t srcno)
 291 {
 292     assert(srcno < xsrc->nr_irqs);
 293     return test_bit(srcno, xsrc->lsi_map);
 294 }
 295
 296 static inline void xive_source_irq_set_lsi(XiveSource *xsrc, uint32_t srcno)
 297 {
 298     assert(srcno < xsrc->nr_irqs);
 299     bitmap_set(xsrc->lsi_map, srcno, 1);
 300 }
 301
 302 void xive_source_set_irq(void *opaque, int srcno, int val);
 303
 304 /*
 305  * XIVE Thread interrupt Management (TM) context
 306  */
 307
 308 #define TYPE_XIVE_TCTX "xive-tctx"
 309 typedef struct XiveTCTX XiveTCTX;
 310 DECLARE_INSTANCE_CHECKER(XiveTCTX, XIVE_TCTX,
 311                          TYPE_XIVE_TCTX)
 312
 313 /*
 314  * XIVE Thread interrupt Management register rings :
 315  *
 316  *   QW-0  User       event-based exception state
 317  *   QW-1  O/S        OS context for priority management, interrupt acks
 318  *   QW-2  Pool       hypervisor pool context for virtual processors dispatched
 319  *   QW-3  Physical   physical thread context and security context
 320  */
 321 #define XIVE_TM_RING_COUNT      4
 322 #define XIVE_TM_RING_SIZE       0x10
 323
 324 typedef struct XivePresenter XivePresenter;
 325
 326 struct XiveTCTX {
 327     DeviceState parent_obj;
 328
 329     CPUState    *cs;
 330     qemu_irq    hv_output;
 331     qemu_irq    os_output;
 332
 333     uint8_t     regs[XIVE_TM_RING_COUNT * XIVE_TM_RING_SIZE];
 334
 335     XivePresenter *xptr;
 336 };
 337
 338 /*
 339  * XIVE Router
 340  */
 341 typedef struct XiveFabric XiveFabric;
 342
 343 struct XiveRouter {
 344     SysBusDevice    parent;
 345
 346     XiveFabric *xfb;
 347 };
 348
 349 #define TYPE_XIVE_ROUTER "xive-router"
 350 OBJECT_DECLARE_TYPE(XiveRouter, XiveRouterClass,
 351                     XIVE_ROUTER)
 352
 353 struct XiveRouterClass {
 354     SysBusDeviceClass parent;
 355
 356     /* XIVE table accessors */
 357     int (*get_eas)(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx,
 358                    XiveEAS *eas);
 359     int (*get_end)(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
 360                    XiveEND *end);
 361     int (*write_end)(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
 362                      XiveEND *end, uint8_t word_number);
 363     int (*get_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
 364                    XiveNVT *nvt);
 365     int (*write_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
 366                      XiveNVT *nvt, uint8_t word_number);
 367     uint8_t (*get_block_id)(XiveRouter *xrtr);
 368 };
 369
 370 int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx,
 371                         XiveEAS *eas);
 372 int xive_router_get_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
 373                         XiveEND *end);
 374 int xive_router_write_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
 375                           XiveEND *end, uint8_t word_number);
 376 int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
 377                         XiveNVT *nvt);
 378 int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
 379                           XiveNVT *nvt, uint8_t word_number);
 380 void xive_router_notify(XiveNotifier *xn, uint32_t lisn);
 381
 382 /*
 383  * XIVE Presenter
 384  */
 385
 386 typedef struct XiveTCTXMatch {
 387     XiveTCTX *tctx;
 388     uint8_t ring;
 389 } XiveTCTXMatch;
 390
 391 #define TYPE_XIVE_PRESENTER "xive-presenter"
 392 #define XIVE_PRESENTER(obj)                                     \
 393     INTERFACE_CHECK(XivePresenter, (obj), TYPE_XIVE_PRESENTER)
 394 typedef struct XivePresenterClass XivePresenterClass;
 395 DECLARE_CLASS_CHECKERS(XivePresenterClass, XIVE_PRESENTER,
 396                        TYPE_XIVE_PRESENTER)
 397
 398 struct XivePresenterClass {
 399     InterfaceClass parent;
 400     int (*match_nvt)(XivePresenter *xptr, uint8_t format,
 401                      uint8_t nvt_blk, uint32_t nvt_idx,
 402                      bool cam_ignore, uint8_t priority,
 403                      uint32_t logic_serv, XiveTCTXMatch *match);
 404     bool (*in_kernel)(const XivePresenter *xptr);
 405 };
 406
 407 int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
 408                               uint8_t format,
 409                               uint8_t nvt_blk, uint32_t nvt_idx,
 410                               bool cam_ignore, uint32_t logic_serv);
 411
 412 /*
 413  * XIVE Fabric (Interface between Interrupt Controller and Machine)
 414  */
 415
 416 #define TYPE_XIVE_FABRIC "xive-fabric"
 417 #define XIVE_FABRIC(obj)                                     \
 418     INTERFACE_CHECK(XiveFabric, (obj), TYPE_XIVE_FABRIC)
 419 typedef struct XiveFabricClass XiveFabricClass;
 420 DECLARE_CLASS_CHECKERS(XiveFabricClass, XIVE_FABRIC,
 421                        TYPE_XIVE_FABRIC)
 422
 423 struct XiveFabricClass {
 424     InterfaceClass parent;
 425     int (*match_nvt)(XiveFabric *xfb, uint8_t format,
 426                      uint8_t nvt_blk, uint32_t nvt_idx,
 427                      bool cam_ignore, uint8_t priority,
 428                      uint32_t logic_serv, XiveTCTXMatch *match);
 429 };
 430
 431 /*
 432  * XIVE END ESBs
 433  */
 434
 435 #define TYPE_XIVE_END_SOURCE "xive-end-source"
 436 typedef struct XiveENDSource XiveENDSource;
 437 DECLARE_INSTANCE_CHECKER(XiveENDSource, XIVE_END_SOURCE,
 438                          TYPE_XIVE_END_SOURCE)
 439
 440 struct XiveENDSource {
 441     DeviceState parent;
 442
 443     uint32_t        nr_ends;
 444
 445     /* ESB memory region */
 446     uint32_t        esb_shift;
 447     MemoryRegion    esb_mmio;
 448
 449     XiveRouter      *xrtr;
 450 };
 451
 452 /*
 453  * For legacy compatibility, the exceptions define up to 256 different
 454  * priorities. P9 implements only 9 levels : 8 active levels [0 - 7]
 455  * and the least favored level 0xFF.
 456  */
 457 #define XIVE_PRIORITY_MAX  7
 458
 459 /*
 460  * XIVE Thread Interrupt Management Aera (TIMA)
 461  *
 462  * This region gives access to the registers of the thread interrupt
 463  * management context. It is four page wide, each page providing a
 464  * different view of the registers. The page with the lower offset is
 465  * the most privileged and gives access to the entire context.
 466  */
 467 #define XIVE_TM_HW_PAGE         0x0
 468 #define XIVE_TM_HV_PAGE         0x1
 469 #define XIVE_TM_OS_PAGE         0x2
 470 #define XIVE_TM_USER_PAGE       0x3
 471
 472 void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
 473                         uint64_t value, unsigned size);
 474 uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
 475                            unsigned size);
 476
 477 void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon);
 478 Object *xive_tctx_create(Object *cpu, XivePresenter *xptr, Error **errp);
 479 void xive_tctx_reset(XiveTCTX *tctx);
 480 void xive_tctx_destroy(XiveTCTX *tctx);
 481 void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb);
 482
 483 /*
 484  * KVM XIVE device helpers
 485  */
 486
 487 int kvmppc_xive_source_reset_one(XiveSource *xsrc, int srcno, Error **errp);
 488 void kvmppc_xive_source_set_irq(void *opaque, int srcno, int val);
 489 int kvmppc_xive_cpu_connect(XiveTCTX *tctx, Error **errp);
 490 int kvmppc_xive_cpu_synchronize_state(XiveTCTX *tctx, Error **errp);
 491 int kvmppc_xive_cpu_get_state(XiveTCTX *tctx, Error **errp);
 492 int kvmppc_xive_cpu_set_state(XiveTCTX *tctx, Error **errp);
 493
 494 #endif /* PPC_XIVE_H */