include/lh7a40x.h

   1 /*
   2  * See file CREDITS for list of people who contributed to this
   3  * project.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  */
  20
  21 /*
  22  * lh7a40x SoC series common interface
  23  */
  24
  25 #ifndef __LH7A40X_H__
  26 #define __LH7A40X_H__
  27
  28 /* (SMC) Static Memory Controller (usersguide 4.2.1) */
  29 typedef struct {
  30         volatile u32  attib;
  31         volatile u32  com;
  32         volatile u32  io;
  33         volatile u32  rsvd1;
  34 } /*__attribute__((__packed__))*/ lh7a40x_pccard_t;
  35
  36 typedef struct {
  37         volatile u32      bcr[8];
  38         lh7a40x_pccard_t  pccard[2];
  39         volatile u32      pcmciacon;
  40 } /*__attribute__((__packed__))*/ lh7a40x_smc_t;
  41 #define LH7A40X_SMC_BASE  (0x80002000)
  42 #define LH7A40X_SMC_PTR   ((lh7a40x_smc_t*) LH7A40X_SMC_BASE)
  43
  44 /* (SDMC) Synchronous Dynamic Ram Controller (usersguide 5.3.1) */
  45 typedef struct {
  46         volatile u32  rsvd1;
  47         volatile u32  gblcnfg;
  48         volatile u32  rfshtmr;
  49         volatile u32  bootstat;
  50         volatile u32  sdcsc[4];
  51 } /*__attribute__((__packed__))*/ lh7a40x_sdmc_t;
  52 #define LH7A40X_SDMC_BASE  (0x80002400)
  53 #define LH7A40X_SDMC_PTR   ((lh7a40x_sdmc_t*) LH7A40X_SDMC_BASE)
  54
  55 /* (CSC) Clock and State Controller (userguide 6.2.1) */
  56 typedef struct {
  57         volatile u32  pwrsr;
  58         volatile u32  pwrcnt;
  59         volatile u32  halt;
  60         volatile u32  stby;
  61         volatile u32  bleoi;
  62         volatile u32  mceoi;
  63         volatile u32  teoi;
  64         volatile u32  stfclr;
  65         volatile u32  clkset;
  66         volatile u32  scrreg[2];
  67         volatile u32  rsvd1;
  68         volatile u32  usbreset;
  69 } /*__attribute__((__packed__))*/ lh7a40x_csc_t;
  70 #define LH7A40X_STPWR_BASE  (0x80000400)
  71 #define LH7A40X_CSC_PTR     ((lh7a40x_csc_t*) LH7A40X_STPWR_BASE)
  72
  73 #define CLKSET_SMCROM           (0x01000000)
  74 #define CLKSET_PS               (0x000C0000)
  75 #define CLKSET_PS_0             (0x00000000)
  76 #define CLKSET_PS_1             (0x00040000)
  77 #define CLKSET_PS_2             (0x00080000)
  78 #define CLKSET_PS_3             (0x000C0000)
  79 #define CLKSET_PCLKDIV          (0x00030000)
  80 #define CLKSET_PCLKDIV_2        (0x00000000)
  81 #define CLKSET_PCLKDIV_4        (0x00010000)
  82 #define CLKSET_PCLKDIV_8        (0x00020000)
  83 #define CLKSET_MAINDIV2         (0x0000f800)
  84 #define CLKSET_MAINDIV1         (0x00000780)
  85 #define CLKSET_PREDIV           (0x0000007C)
  86 #define CLKSET_HCLKDIV          (0x00000003)
  87
  88 /* (DMA) Direct Memory Access Controller (userguide 9.2.1) */
  89 typedef struct {
  90         volatile u32  maxcnt;
  91         volatile u32  base;
  92         volatile u32  current;
  93         volatile u32  rsvd1;
  94 } lh7a40x_dmabuf_t;
  95
  96 typedef struct {
  97         volatile u32      control;
  98         volatile u32      interrupt;
  99         volatile u32      rsvd1;
 100         volatile u32      status;
 101         volatile u32      rsvd2;
 102         volatile u32      remain;
 103         volatile u32      rsvd3;
 104         volatile u32      rsvd4;
 105         lh7a40x_dmabuf_t  buf[2];
 106 } /*__attribute__((__packed__))*/ lh7a40x_dmachan_t;
 107
 108
 109 /* (WDT) Watchdog Timer (userguide 11.2.1) */
 110 typedef struct {
 111         volatile u32  ctl;
 112         volatile u32  rst;
 113         volatile u32  status;
 114         volatile u32  count[4];
 115 } /*__attribute__((__packed__))*/ lh7a40x_wdt_t;
 116 #define LH7A40X_WDT_BASE    (0x80001400)
 117 #define LH7A40X_WDT_PTR     ((lh7a40x_wdt_t*) LH7A40X_WDT_BASE)
 118
 119 /* (RTC) Real Time Clock (lh7a400 userguide 12.2.1, lh7a404 userguide 13.2.1) */
 120 typedef struct {
 121         volatile u32  rtcdr;
 122         volatile u32  rtclr;
 123         volatile u32  rtcmr;
 124         volatile u32  unk1;
 125         volatile u32  rtcstat_eoi;
 126         volatile u32  rtccr;
 127         volatile u32  rsvd1[58];
 128 } /*__attribute__((__packed__))*/ lh7a40x_rtc_t;
 129 #define LH7A40X_RTC_BASE    (0x80000D00)
 130 #define LH7A40X_RTC_PTR     ((lh7a40x_rtc_t*) LH7A40X_RTC_BASE)
 131
 132 /* Timers (lh7a400 userguide 13.2.1, lh7a404 userguide 11.2.1) */
 133 typedef struct {
 134         volatile u32  load;
 135         volatile u32  value;
 136         volatile u32  control;
 137         volatile u32  tceoi;
 138 } /*__attribute__((__packed__))*/ lh7a40x_timer_t;
 139
 140 typedef struct {
 141         lh7a40x_timer_t  timer1;
 142         volatile u32     rsvd1[4];
 143         lh7a40x_timer_t  timer2;
 144         volatile u32     unk1[4];
 145         volatile u32     bzcon;
 146         volatile u32     unk2[15];
 147         lh7a40x_timer_t  timer3;
 148         /*volatile u32     rsvd2;*/
 149 } /*__attribute__((__packed__))*/ lh7a40x_timers_t;
 150 #define LH7A40X_TIMERS_BASE    (0x80000C00)
 151 #define LH7A40X_TIMERS_PTR     ((lh7a40x_timers_t*) LH7A40X_TIMERS_BASE)
 152
 153 #define TIMER_EN        (0x00000080)
 154 #define TIMER_PER       (0x00000040)
 155 #define TIMER_FREE      (0x00000000)
 156 #define TIMER_CLK508K   (0x00000008)
 157 #define TIMER_CLK2K     (0x00000000)
 158
 159 /* (SSP) Sychronous Serial Ports (lh7a400 userguide 14.2.1, lh7a404 userguide 14.2.1) */
 160 typedef struct {
 161         volatile u32  cr0;
 162         volatile u32  cr1;
 163         volatile u32  irr_roeoi;
 164         volatile u32  dr;
 165         volatile u32  cpr;
 166         volatile u32  sr;
 167         /*volatile u32  rsvd1[58];*/
 168 } /*__attribute__((__packed__))*/ lh7a40x_ssp_t;
 169 #define LH7A40X_SSP_BASE    (0x80000B00)
 170 #define LH7A40X_SSP_PTR     ((lh7a40x_ssp_t*) LH7A40X_SSP_BASE)
 171
 172 /* (UART) Universal Asychronous Receiver/Transmitter (lh7a400 userguide 15.2.1, lh7a404 userguide 15.2.1) */
 173 typedef struct {
 174         volatile u32  data;
 175         volatile u32  fcon;
 176         volatile u32  brcon;
 177         volatile u32  con;
 178         volatile u32  status;
 179         volatile u32  rawisr;
 180         volatile u32  inten;
 181         volatile u32  isr;
 182         volatile u32  rsvd1[56];
 183 } /*__attribute__((__packed__))*/ lh7a40x_uart_t;
 184 #define LH7A40X_UART_BASE    (0x80000600)
 185 #define LH7A40X_UART_PTR(n) \
 186         ((lh7a40x_uart_t*) (LH7A40X_UART_BASE + ((n-1) * sizeof(lh7a40x_uart_t))))
 187
 188 #define UART_BE         (0x00000800)      /* the rx error bits */
 189 #define UART_OE         (0x00000400)
 190 #define UART_PE         (0x00000200)
 191 #define UART_FE         (0x00000100)
 192
 193 #define UART_WLEN       (0x00000060)    /* fcon bits */
 194 #define UART_WLEN_8     (0x00000060)
 195 #define UART_WLEN_7     (0x00000040)
 196 #define UART_WLEN_6     (0x00000020)
 197 #define UART_WLEN_5     (0x00000000)
 198 #define UART_FEN        (0x00000010)
 199 #define UART_STP2       (0x00000008)
 200 #define UART_STP2_2     (0x00000008)
 201 #define UART_STP2_1     (0x00000000)
 202 #define UART_EPS        (0x00000004)
 203 #define UART_EPS_EVEN   (0x00000004)
 204 #define UART_EPS_ODD    (0x00000000)
 205 #define UART_PEN        (0x00000002)
 206 #define UART_BRK        (0x00000001)
 207
 208 #define UART_BAUDDIV    (0x0000ffff)    /* brcon bits */
 209
 210 #define UART_SIRBD      (0x00000080)    /* con bits */
 211 #define UART_LBE        (0x00000040)
 212 #define UART_MXP        (0x00000020)
 213 #define UART_TXP        (0x00000010)
 214 #define UART_RXP        (0x00000008)
 215 #define UART_SIRLP      (0x00000004)
 216 #define UART_SIRD       (0x00000002)
 217 #define UART_EN         (0x00000001)
 218
 219 #define UART_TXFE       (0x00000080)    /* status bits */
 220 #define UART_RXFF       (0x00000040)
 221 #define UART_TXFF       (0x00000020)
 222 #define UART_RXFE       (0x00000010)
 223 #define UART_BUSY       (0x00000008)
 224 #define UART_DCD        (0x00000004)
 225 #define UART_DSR        (0x00000002)
 226 #define UART_CTS        (0x00000001)
 227
 228 #define UART_MSEOI      (0xfffffff0)    /* rawisr interrupt bits */
 229
 230 #define UART_RTI        (0x00000008)    /* generic interrupt bits */
 231 #define UART_MI         (0x00000004)
 232 #define UART_TI         (0x00000002)
 233 #define UART_RI         (0x00000001)
 234
 235 /* (GPIO) General Purpose IO and External Interrupts (userguide 16.2.1) */
 236 typedef struct {
 237         volatile u32  pad;
 238         volatile u32  pbd;
 239         volatile u32  pcd;
 240         volatile u32  pdd;
 241         volatile u32  padd;
 242         volatile u32  pbdd;
 243         volatile u32  pcdd;
 244         volatile u32  pddd;
 245         volatile u32  ped;
 246         volatile u32  pedd;
 247         volatile u32  kbdctl;
 248         volatile u32  pinmux;
 249         volatile u32  pfd;
 250         volatile u32  pfdd;
 251         volatile u32  pgd;
 252         volatile u32  pgdd;
 253         volatile u32  phd;
 254         volatile u32  phdd;
 255         volatile u32  rsvd1;
 256         volatile u32  inttype1;
 257         volatile u32  inttype2;
 258         volatile u32  gpiofeoi;
 259         volatile u32  gpiointen;
 260         volatile u32  intstatus;
 261         volatile u32  rawintstatus;
 262         volatile u32  gpiodb;
 263         volatile u32  papd;
 264         volatile u32  pbpd;
 265         volatile u32  pcpd;
 266         volatile u32  pdpd;
 267         volatile u32  pepd;
 268         volatile u32  pfpd;
 269         volatile u32  pgpd;
 270         volatile u32  phpd;
 271 } /*__attribute__((__packed__))*/ lh7a40x_gpioint_t;
 272 #define LH7A40X_GPIOINT_BASE    (0x80000E00)
 273 #define LH7A40X_GPIOINT_PTR     ((lh7a40x_gpioint_t*) LH7A40X_GPIOINT_BASE)
 274
 275 /* Embedded SRAM */
 276 #define CONFIG_SYS_SRAM_BASE    (0xB0000000)
 277 #define CONFIG_SYS_SRAM_SIZE    (80*1024)       /* 80kB */
 278
 279 #endif  /* __LH7A40X_H__ */