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rename CFG_ macros to CONFIG_SYS
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1 /*----------------------------------------------------------------------------+
2 |
3 | This source code has been made available to you by IBM on an AS-IS
4 | basis. Anyone receiving this source is licensed under IBM
5 | copyrights to use it in any way he or she deems fit, including
6 | copying it, modifying it, compiling it, and redistributing it either
7 | with or without modifications. No license under IBM patents or
8 | patent applications is to be implied by the copyright license.
9 |
10 | Any user of this software should understand that IBM cannot provide
11 | technical support for this software and will not be responsible for
12 | any consequences resulting from the use of this software.
13 |
14 | Any person who transfers this source code or any derivative work
15 | must include the IBM copyright notice, this paragraph, and the
16 | preceding two paragraphs in the transferred software.
17 |
18 | COPYRIGHT I B M CORPORATION 1999
19 | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 +----------------------------------------------------------------------------*/
21 /*----------------------------------------------------------------------------+
22 |
23 | File Name: miiphy.h
24 |
25 | Function: Include file defining PHY registers.
26 |
27 | Author: Mark Wisner
28 |
29 +----------------------------------------------------------------------------*/
30 #ifndef _miiphy_h_
31 #define _miiphy_h_
32
33 #include <net.h>
34
35 int miiphy_read (char *devname, unsigned char addr, unsigned char reg,
36 unsigned short *value);
37 int miiphy_write (char *devname, unsigned char addr, unsigned char reg,
38 unsigned short value);
39 int miiphy_info (char *devname, unsigned char addr, unsigned int *oui,
40 unsigned char *model, unsigned char *rev);
41 int miiphy_reset (char *devname, unsigned char addr);
42 int miiphy_speed (char *devname, unsigned char addr);
43 int miiphy_duplex (char *devname, unsigned char addr);
44 int miiphy_is_1000base_x (char *devname, unsigned char addr);
45 #ifdef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
46 int miiphy_link (char *devname, unsigned char addr);
47 #endif
48
49 void miiphy_init (void);
50
51 void miiphy_register (char *devname,
52 int (*read) (char *devname, unsigned char addr,
53 unsigned char reg, unsigned short *value),
54 int (*write) (char *devname, unsigned char addr,
55 unsigned char reg, unsigned short value));
56
57 int miiphy_set_current_dev (char *devname);
58 char *miiphy_get_current_dev (void);
59
60 void miiphy_listdev (void);
61
62 #define BB_MII_DEVNAME "bbmii"
63
64 int bb_miiphy_read (char *devname, unsigned char addr,
65 unsigned char reg, unsigned short *value);
66 int bb_miiphy_write (char *devname, unsigned char addr,
67 unsigned char reg, unsigned short value);
68
69 /* phy seed setup */
70 #define AUTO 99
71 #define _1000BASET 1000
72 #define _100BASET 100
73 #define _10BASET 10
74 #define HALF 22
75 #define FULL 44
76
77 /* phy register offsets */
78 #define PHY_BMCR 0x00
79 #define PHY_BMSR 0x01
80 #define PHY_PHYIDR1 0x02
81 #define PHY_PHYIDR2 0x03
82 #define PHY_ANAR 0x04
83 #define PHY_ANLPAR 0x05
84 #define PHY_ANER 0x06
85 #define PHY_ANNPTR 0x07
86 #define PHY_ANLPNP 0x08
87 #define PHY_1000BTCR 0x09
88 #define PHY_1000BTSR 0x0A
89 #define PHY_EXSR 0x0F
90 #define PHY_PHYSTS 0x10
91 #define PHY_MIPSCR 0x11
92 #define PHY_MIPGSR 0x12
93 #define PHY_DCR 0x13
94 #define PHY_FCSCR 0x14
95 #define PHY_RECR 0x15
96 #define PHY_PCSR 0x16
97 #define PHY_LBR 0x17
98 #define PHY_10BTSCR 0x18
99 #define PHY_PHYCTRL 0x19
100
101 /* PHY BMCR */
102 #define PHY_BMCR_RESET 0x8000
103 #define PHY_BMCR_LOOP 0x4000
104 #define PHY_BMCR_100MB 0x2000
105 #define PHY_BMCR_AUTON 0x1000
106 #define PHY_BMCR_POWD 0x0800
107 #define PHY_BMCR_ISO 0x0400
108 #define PHY_BMCR_RST_NEG 0x0200
109 #define PHY_BMCR_DPLX 0x0100
110 #define PHY_BMCR_COL_TST 0x0080
111
112 #define PHY_BMCR_SPEED_MASK 0x2040
113 #define PHY_BMCR_1000_MBPS 0x0040
114 #define PHY_BMCR_100_MBPS 0x2000
115 #define PHY_BMCR_10_MBPS 0x0000
116
117 /* phy BMSR */
118 #define PHY_BMSR_100T4 0x8000
119 #define PHY_BMSR_100TXF 0x4000
120 #define PHY_BMSR_100TXH 0x2000
121 #define PHY_BMSR_10TF 0x1000
122 #define PHY_BMSR_10TH 0x0800
123 #define PHY_BMSR_EXT_STAT 0x0100
124 #define PHY_BMSR_PRE_SUP 0x0040
125 #define PHY_BMSR_AUTN_COMP 0x0020
126 #define PHY_BMSR_RF 0x0010
127 #define PHY_BMSR_AUTN_ABLE 0x0008
128 #define PHY_BMSR_LS 0x0004
129 #define PHY_BMSR_JD 0x0002
130 #define PHY_BMSR_EXT 0x0001
131
132 /*phy ANLPAR */
133 #define PHY_ANLPAR_NP 0x8000
134 #define PHY_ANLPAR_ACK 0x4000
135 #define PHY_ANLPAR_RF 0x2000
136 #define PHY_ANLPAR_ASYMP 0x0800
137 #define PHY_ANLPAR_PAUSE 0x0400
138 #define PHY_ANLPAR_T4 0x0200
139 #define PHY_ANLPAR_TXFD 0x0100
140 #define PHY_ANLPAR_TX 0x0080
141 #define PHY_ANLPAR_10FD 0x0040
142 #define PHY_ANLPAR_10 0x0020
143 #define PHY_ANLPAR_100 0x0380 /* we can run at 100 */
144 /* phy ANLPAR 1000BASE-X */
145 #define PHY_X_ANLPAR_NP 0x8000
146 #define PHY_X_ANLPAR_ACK 0x4000
147 #define PHY_X_ANLPAR_RF_MASK 0x3000
148 #define PHY_X_ANLPAR_PAUSE_MASK 0x0180
149 #define PHY_X_ANLPAR_HD 0x0040
150 #define PHY_X_ANLPAR_FD 0x0020
151
152 #define PHY_ANLPAR_PSB_MASK 0x001f
153 #define PHY_ANLPAR_PSB_802_3 0x0001
154 #define PHY_ANLPAR_PSB_802_9 0x0002
155
156 /* phy 1000BTCR */
157 #define PHY_1000BTCR_1000FD 0x0200
158 #define PHY_1000BTCR_1000HD 0x0100
159
160 /* phy 1000BTSR */
161 #define PHY_1000BTSR_MSCF 0x8000
162 #define PHY_1000BTSR_MSCR 0x4000
163 #define PHY_1000BTSR_LRS 0x2000
164 #define PHY_1000BTSR_RRS 0x1000
165 #define PHY_1000BTSR_1000FD 0x0800
166 #define PHY_1000BTSR_1000HD 0x0400
167
168 /* phy EXSR */
169 #define PHY_EXSR_1000XF 0x8000
170 #define PHY_EXSR_1000XH 0x4000
171 #define PHY_EXSR_1000TF 0x2000
172 #define PHY_EXSR_1000TH 0x1000
173
174 #endif