include/opcode/ChangeLog

   1 2006-03-10  Paul Brook  <paul@codesourcery.com>
   2
   3         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
   4
   5 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
   6
   7         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
   8         first.  Correct mask of bb "B" opcode.
   9
  10 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
  11
  12         * i386.h (i386_optab): Support Intel Merom New Instructions.
  13
  14 2006-02-24  Paul Brook  <paul@codesourcery.com>
  15
  16         * arm.h: Add V7 feature bits.
  17
  18 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
  19
  20         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
  21
  22 2006-01-31  Paul Brook  <paul@codesourcery.com>
  23         Richard Earnshaw <rearnsha@arm.com>
  24
  25         * arm.h: Use ARM_CPU_FEATURE.
  26         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
  27         (arm_feature_set): Change to a structure.
  28         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
  29         ARM_FEATURE): New macros.
  30
  31 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
  32
  33         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
  34         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
  35         (ADD_PC_INCR_OPCODE): Don't define.
  36
  37 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
  38
  39         PR gas/1874
  40         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
  41
  42 2005-11-14  David Ung  <davidu@mips.com>
  43
  44         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
  45         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
  46         save/restore encoding of the args field.
  47
  48 2005-10-28  Dave Brolley  <brolley@redhat.com>
  49
  50         Contribute the following changes:
  51         2005-02-16  Dave Brolley  <brolley@redhat.com>
  52
  53         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
  54         cgen_isa_mask_* to cgen_bitset_*.
  55         * cgen.h: Likewise.
  56
  57         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
  58
  59         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
  60         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
  61         (CGEN_CPU_TABLE): Make isas a ponter.
  62
  63         2003-09-29  Dave Brolley  <brolley@redhat.com>
  64
  65         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
  66         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
  67         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
  68
  69         2002-12-13  Dave Brolley  <brolley@redhat.com>
  70
  71         * cgen.h (symcat.h): #include it.
  72         (cgen-bitset.h): #include it.
  73         (CGEN_ATTR_VALUE_TYPE): Now a union.
  74         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
  75         (CGEN_ATTR_ENTRY): 'value' now unsigned.
  76         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
  77         * cgen-bitset.h: New file.
  78
  79 2005-09-30  Catherine Moore  <clm@cm00re.com>
  80
  81         * bfin.h: New file.
  82
  83 2005-10-24  Jan Beulich  <jbeulich@novell.com>
  84
  85         * ia64.h (enum ia64_opnd): Move memory operand out of set of
  86         indirect operands.
  87
  88 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  89
  90         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
  91         Add FLAG_STRICT to pa10 ftest opcode.
  92
  93 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  94
  95         * hppa.h (pa_opcodes): Remove lha entries.
  96
  97 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  98
  99         * hppa.h (FLAG_STRICT): Revise comment.
 100         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 101         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 102         entries for "fdc".
 103
 104 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 105
 106         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 107
 108 2005-09-06  Chao-ying Fu  <fu@mips.com>
 109
 110         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 111         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 112         define.
 113         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 114         (INSN_ASE_MASK): Update to include INSN_MT.
 115         (INSN_MT): New define for MT ASE.
 116
 117 2005-08-25  Chao-ying Fu  <fu@mips.com>
 118
 119         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 120         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 121         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 122         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 123         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 124         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 125         instructions.
 126         (INSN_DSP): New define for DSP ASE.
 127
 128 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 129
 130         * a29k.h: Delete.
 131
 132 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 133
 134         * ppc.h (PPC_OPCODE_E300): Define.
 135
 136 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 137
 138         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 139
 140 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 141
 142         PR gas/336
 143         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 144         and pitlb.
 145
 146 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 147
 148         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 149         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 150         Add movq-s as 64-bit variants of movd-s.
 151
 152 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 153
 154         * hppa.h: Fix punctuation in comment.
 155
 156         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 157         implicit space-register addressing.  Set space-register bits on opcodes
 158         using implicit space-register addressing.  Add various missing pa20
 159         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 160         space-register addressing.  Use "fE" instead of "fe" in various
 161         fstw opcodes.
 162
 163 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 164
 165         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 166
 167 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 168
 169         * i386.h (i386_optab): Support Intel VMX Instructions.
 170
 171 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 172
 173         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 174
 175 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 176
 177         * i386.h (i386_optab): Add new insns.
 178
 179 2005-07-01  Nick Clifton  <nickc@redhat.com>
 180
 181         * sparc.h: Add typedefs to structure declarations.
 182
 183 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 184
 185         PR 1013
 186         * i386.h (i386_optab): Update comments for 64bit addressing on
 187         mov. Allow 64bit addressing for mov and movq.
 188
 189 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 190
 191         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 192         respectively, in various floating-point load and store patterns.
 193
 194 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 195
 196         * hppa.h (FLAG_STRICT): Correct comment.
 197         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 198         PA 2.0 mneumonics when equivalent.  Entries with cache control
 199         completers now require PA 1.1.  Adjust whitespace.
 200
 201 2005-05-19  Anton Blanchard  <anton@samba.org>
 202
 203         * ppc.h (PPC_OPCODE_POWER5): Define.
 204
 205 2005-05-10  Nick Clifton  <nickc@redhat.com>
 206
 207         * Update the address and phone number of the FSF organization in
 208         the GPL notices in the following files:
 209         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 210         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 211         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 212         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 213         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 214         tic54x.h, tic80.h, v850.h, vax.h
 215
 216 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 217
 218         * i386.h (i386_optab): Add ht and hnt.
 219
 220 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 221
 222         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 223         Add xcrypt-ctr.  Provide aliases without hyphens.
 224
 225 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 226
 227         Moved from ../ChangeLog
 228
 229         2005-04-12  Paul Brook  <paul@codesourcery.com>
 230         * m88k.h: Rename psr macros to avoid conflicts.
 231
 232         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 233         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 234         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 235         and ARM_ARCH_V6ZKT2.
 236
 237         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 238         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 239         Remove redundant instruction types.
 240         (struct argument): X_op - new field.
 241         (struct cst4_entry): Remove.
 242         (no_op_insn): Declare.
 243
 244         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 245         * crx.h (enum argtype): Rename types, remove unused types.
 246
 247         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 248         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 249         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 250         (enum operand_type): Rearrange operands, edit comments.
 251         replace us<N> with ui<N> for unsigned immediate.
 252         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 253         displacements (respectively).
 254         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 255         (instruction type): Add NO_TYPE_INS.
 256         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 257         (operand_entry): New field - 'flags'.
 258         (operand flags): New.
 259
 260         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 261         * crx.h (operand_type): Remove redundant types i3, i4,
 262         i5, i8, i12.
 263         Add new unsigned immediate types us3, us4, us5, us16.
 264
 265 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 266
 267         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 268         adjust them accordingly.
 269
 270 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 271
 272         * i386.h (i386_optab): Add rdtscp.
 273
 274 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 275
 276         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 277         between memory and segment register. Allow movq for moving between
 278         general-purpose register and segment register.
 279
 280 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 281
 282         PR gas/707
 283         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 284         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 285         fnstsw.
 286
 287 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 288
 289         * m68k.h (m68008, m68ec030, m68882): Remove.
 290         (m68k_mask): New.
 291         (cpu_m68k, cpu_cf): New.
 292         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 293         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 294
 295 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 296
 297         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 298         * cgen.h (enum cgen_parse_operand_type): Add
 299         CGEN_PARSE_OPERAND_SYMBOLIC.
 300
 301 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 302
 303         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 304         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 305         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 306
 307 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 308
 309         * mips.h (struct mips_opcode): Add new pinfo2 member.
 310         (INSN_ALIAS): New define for opcode table entries that are
 311         specific instances of another entry, such as 'move' for an 'or'
 312         with a zero operand.
 313         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 314         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 315
 316 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 317
 318         * mips.h (CPU_RM9000): Define.
 319         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 320
 321 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 322
 323         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 324         to/from test registers are illegal in 64-bit mode. Add missing
 325         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 326         (previously one had to explicitly encode a rex64 prefix). Re-enable
 327         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 328         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 329
 330 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 331
 332         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 333         available only with SSE2. Change the MMX additions introduced by SSE
 334         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 335         instructions by their now designated identifier (since combining i686
 336         and 3DNow! does not really imply 3DNow!A).
 337
 338 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 339
 340         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 341         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 342
 343 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 344             Vineet Sharma      <vineets@noida.hcltech.com>
 345
 346         * maxq.h: New file: Disassembly information for the maxq port.
 347
 348 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 349
 350         * i386.h (i386_optab): Put back "movzb".
 351
 352 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 353
 354         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 355         comments.  Remove member cris_ver_sim.  Add members
 356         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 357         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 358         (struct cris_support_reg, struct cris_cond15): New types.
 359         (cris_conds15): Declare.
 360         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 361         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 362         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 363         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 364         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 365         SIZE_FIELD_UNSIGNED.
 366
 367 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 368
 369         * i386.h (sldx_Suf): Remove.
 370         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 371         (q_FP): Define, implying no REX64.
 372         (x_FP, sl_FP): Imply FloatMF.
 373         (i386_optab): Split reg and mem forms of moving from segment registers
 374         so that the memory forms can ignore the 16-/32-bit operand size
 375         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 376         all non-floating-point instructions. Unite 32- and 64-bit forms of
 377         movsx, movzx, and movd. Adjust floating point operations for the above
 378         changes to the *FP macros. Add DefaultSize to floating point control
 379         insns operating on larger memory ranges. Remove left over comments
 380         hinting at certain insns being Intel-syntax ones where the ones
 381         actually meant are already gone.
 382
 383 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 384
 385         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 386         instruction type.
 387
 388 2004-09-30  Paul Brook  <paul@codesourcery.com>
 389
 390         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 391         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 392
 393 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 394
 395         * avr.h: Add support for
 396         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 397
 398 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 399
 400         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 401
 402 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 403
 404         * msp430.h (msp430_opc): Add new instructions.
 405         (msp430_rcodes): Declare new instructions.
 406         (msp430_hcodes): Likewise..
 407
 408 2004-08-13  Nick Clifton  <nickc@redhat.com>
 409
 410         PR/301
 411         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 412         processors.
 413
 414 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 415
 416         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 417
 418 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 419
 420         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 421
 422 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 423
 424         * i386.h: Adjust instruction descriptions to better match the
 425         specification.
 426
 427 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 428
 429         * arm.h: Remove all old content.  Replace with architecture defines
 430         from gas/config/tc-arm.c.
 431
 432 2004-07-09  Andreas Schwab  <schwab@suse.de>
 433
 434         * m68k.h: Fix comment.
 435
 436 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 437
 438         * crx.h: New file.
 439
 440 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 441
 442         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 443
 444 2004-05-24  Peter Barada  <peter@the-baradas.com>
 445
 446         * m68k.h: Add 'size' to m68k_opcode.
 447
 448 2004-05-05  Peter Barada  <peter@the-baradas.com>
 449
 450         * m68k.h: Switch from ColdFire chip name to core variant.
 451
 452 2004-04-22  Peter Barada  <peter@the-baradas.com>
 453
 454         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 455         descriptions for new EMAC cases.
 456         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 457         handle Motorola MAC syntax.
 458         Allow disassembly of ColdFire V4e object files.
 459
 460 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 461
 462         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 463
 464 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 465
 466         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 467
 468 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 469
 470         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 471
 472 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 473
 474         * i386.h (i386_optab): Added xstore/xcrypt insns.
 475
 476 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 477
 478         * h8300.h (32bit ldc/stc): Add relaxing support.
 479
 480 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 481
 482         * h8300.h (BITOP): Pass MEMRELAX flag.
 483
 484 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 485
 486         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 487         except for the H8S.
 488
 489 For older changes see ChangeLog-9103
 490 \f
 491 Local Variables:
 492 mode: change-log
 493 left-margin: 8
 494 fill-column: 74
 495 version-control: never
 496 End: