1 2005-11-14 David Ung <davidu@mips.com>
3 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
4 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
5 save/restore encoding of the args field.
7 2005-10-28 Dave Brolley <brolley@redhat.com>
9 Contribute the following changes:
10 2005-02-16 Dave Brolley <brolley@redhat.com>
12 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
13 cgen_isa_mask_* to cgen_bitset_*.
16 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
18 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
19 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
20 (CGEN_CPU_TABLE): Make isas a ponter.
22 2003-09-29 Dave Brolley <brolley@redhat.com>
24 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
25 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
26 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
28 2002-12-13 Dave Brolley <brolley@redhat.com>
30 * cgen.h (symcat.h): #include it.
31 (cgen-bitset.h): #include it.
32 (CGEN_ATTR_VALUE_TYPE): Now a union.
33 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
34 (CGEN_ATTR_ENTRY): 'value' now unsigned.
35 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
36 * cgen-bitset.h: New file.
38 2005-09-30 Catherine Moore <clm@cm00re.com>
42 2005-10-24 Jan Beulich <jbeulich@novell.com>
44 * ia64.h (enum ia64_opnd): Move memory operand out of set of
47 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
49 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
50 Add FLAG_STRICT to pa10 ftest opcode.
52 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
54 * hppa.h (pa_opcodes): Remove lha entries.
56 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
58 * hppa.h (FLAG_STRICT): Revise comment.
59 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
60 before corresponding pa11 opcodes. Add strict pa10 register-immediate
63 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
65 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
67 2005-09-06 Chao-ying Fu <fu@mips.com>
69 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
70 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
72 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
73 (INSN_ASE_MASK): Update to include INSN_MT.
74 (INSN_MT): New define for MT ASE.
76 2005-08-25 Chao-ying Fu <fu@mips.com>
78 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
79 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
80 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
81 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
82 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
83 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
85 (INSN_DSP): New define for DSP ASE.
87 2005-08-18 Alan Modra <amodra@bigpond.net.au>
91 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
93 * ppc.h (PPC_OPCODE_E300): Define.
95 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
97 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
99 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
102 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
105 2005-07-27 Jan Beulich <jbeulich@novell.com>
107 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
108 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
109 Add movq-s as 64-bit variants of movd-s.
111 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
113 * hppa.h: Fix punctuation in comment.
115 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
116 implicit space-register addressing. Set space-register bits on opcodes
117 using implicit space-register addressing. Add various missing pa20
118 long-immediate opcodes. Remove various opcodes using implicit 3-bit
119 space-register addressing. Use "fE" instead of "fe" in various
122 2005-07-18 Jan Beulich <jbeulich@novell.com>
124 * i386.h (i386_optab): Operands of aam and aad are unsigned.
126 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
128 * i386.h (i386_optab): Support Intel VMX Instructions.
130 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
132 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
134 2005-07-05 Jan Beulich <jbeulich@novell.com>
136 * i386.h (i386_optab): Add new insns.
138 2005-07-01 Nick Clifton <nickc@redhat.com>
140 * sparc.h: Add typedefs to structure declarations.
142 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
145 * i386.h (i386_optab): Update comments for 64bit addressing on
146 mov. Allow 64bit addressing for mov and movq.
148 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
150 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
151 respectively, in various floating-point load and store patterns.
153 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
155 * hppa.h (FLAG_STRICT): Correct comment.
156 (pa_opcodes): Update load and store entries to allow both PA 1.X and
157 PA 2.0 mneumonics when equivalent. Entries with cache control
158 completers now require PA 1.1. Adjust whitespace.
160 2005-05-19 Anton Blanchard <anton@samba.org>
162 * ppc.h (PPC_OPCODE_POWER5): Define.
164 2005-05-10 Nick Clifton <nickc@redhat.com>
166 * Update the address and phone number of the FSF organization in
167 the GPL notices in the following files:
168 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
169 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
170 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
171 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
172 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
173 tic54x.h, tic80.h, v850.h, vax.h
175 2005-05-09 Jan Beulich <jbeulich@novell.com>
177 * i386.h (i386_optab): Add ht and hnt.
179 2005-04-18 Mark Kettenis <kettenis@gnu.org>
181 * i386.h: Insert hyphens into selected VIA PadLock extensions.
182 Add xcrypt-ctr. Provide aliases without hyphens.
184 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
186 Moved from ../ChangeLog
188 2005-04-12 Paul Brook <paul@codesourcery.com>
189 * m88k.h: Rename psr macros to avoid conflicts.
191 2005-03-12 Zack Weinberg <zack@codesourcery.com>
192 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
193 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
196 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
197 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
198 Remove redundant instruction types.
199 (struct argument): X_op - new field.
200 (struct cst4_entry): Remove.
201 (no_op_insn): Declare.
203 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
204 * crx.h (enum argtype): Rename types, remove unused types.
206 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
207 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
208 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
209 (enum operand_type): Rearrange operands, edit comments.
210 replace us<N> with ui<N> for unsigned immediate.
211 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
212 displacements (respectively).
213 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
214 (instruction type): Add NO_TYPE_INS.
215 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
216 (operand_entry): New field - 'flags'.
217 (operand flags): New.
219 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
220 * crx.h (operand_type): Remove redundant types i3, i4,
222 Add new unsigned immediate types us3, us4, us5, us16.
224 2005-04-12 Mark Kettenis <kettenis@gnu.org>
226 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
227 adjust them accordingly.
229 2005-04-01 Jan Beulich <jbeulich@novell.com>
231 * i386.h (i386_optab): Add rdtscp.
233 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
235 * i386.h (i386_optab): Don't allow the `l' suffix for moving
236 between memory and segment register. Allow movq for moving between
237 general-purpose register and segment register.
239 2005-02-09 Jan Beulich <jbeulich@novell.com>
242 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
243 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
246 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
248 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
249 * cgen.h (enum cgen_parse_operand_type): Add
250 CGEN_PARSE_OPERAND_SYMBOLIC.
252 2005-01-21 Fred Fish <fnf@specifixinc.com>
254 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
255 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
256 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
258 2005-01-19 Fred Fish <fnf@specifixinc.com>
260 * mips.h (struct mips_opcode): Add new pinfo2 member.
261 (INSN_ALIAS): New define for opcode table entries that are
262 specific instances of another entry, such as 'move' for an 'or'
264 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
265 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
267 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
269 * mips.h (CPU_RM9000): Define.
270 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
272 2004-11-25 Jan Beulich <jbeulich@novell.com>
274 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
275 to/from test registers are illegal in 64-bit mode. Add missing
276 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
277 (previously one had to explicitly encode a rex64 prefix). Re-enable
278 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
279 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
281 2004-11-23 Jan Beulich <jbeulich@novell.com>
283 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
284 available only with SSE2. Change the MMX additions introduced by SSE
285 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
286 instructions by their now designated identifier (since combining i686
287 and 3DNow! does not really imply 3DNow!A).
289 2004-11-19 Alan Modra <amodra@bigpond.net.au>
291 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
292 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
294 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
295 Vineet Sharma <vineets@noida.hcltech.com>
297 * maxq.h: New file: Disassembly information for the maxq port.
299 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
301 * i386.h (i386_optab): Put back "movzb".
303 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
305 * cris.h (enum cris_insn_version_usage): Tweak formatting and
306 comments. Remove member cris_ver_sim. Add members
307 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
308 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
309 (struct cris_support_reg, struct cris_cond15): New types.
310 (cris_conds15): Declare.
311 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
312 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
313 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
314 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
315 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
318 2004-11-04 Jan Beulich <jbeulich@novell.com>
320 * i386.h (sldx_Suf): Remove.
321 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
322 (q_FP): Define, implying no REX64.
323 (x_FP, sl_FP): Imply FloatMF.
324 (i386_optab): Split reg and mem forms of moving from segment registers
325 so that the memory forms can ignore the 16-/32-bit operand size
326 distinction. Adjust a few others for Intel mode. Remove *FP uses from
327 all non-floating-point instructions. Unite 32- and 64-bit forms of
328 movsx, movzx, and movd. Adjust floating point operations for the above
329 changes to the *FP macros. Add DefaultSize to floating point control
330 insns operating on larger memory ranges. Remove left over comments
331 hinting at certain insns being Intel-syntax ones where the ones
332 actually meant are already gone.
334 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
336 * crx.h: Add COPS_REG_INS - Coprocessor Special register
339 2004-09-30 Paul Brook <paul@codesourcery.com>
341 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
342 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
344 2004-09-11 Theodore A. Roth <troth@openavr.org>
346 * avr.h: Add support for
347 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
349 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
351 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
353 2004-08-24 Dmitry Diky <diwil@spec.ru>
355 * msp430.h (msp430_opc): Add new instructions.
356 (msp430_rcodes): Declare new instructions.
357 (msp430_hcodes): Likewise..
359 2004-08-13 Nick Clifton <nickc@redhat.com>
362 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
365 2004-08-30 Michal Ludvig <mludvig@suse.cz>
367 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
369 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
371 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
373 2004-07-21 Jan Beulich <jbeulich@novell.com>
375 * i386.h: Adjust instruction descriptions to better match the
378 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
380 * arm.h: Remove all old content. Replace with architecture defines
381 from gas/config/tc-arm.c.
383 2004-07-09 Andreas Schwab <schwab@suse.de>
385 * m68k.h: Fix comment.
387 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
391 2004-06-24 Alan Modra <amodra@bigpond.net.au>
393 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
395 2004-05-24 Peter Barada <peter@the-baradas.com>
397 * m68k.h: Add 'size' to m68k_opcode.
399 2004-05-05 Peter Barada <peter@the-baradas.com>
401 * m68k.h: Switch from ColdFire chip name to core variant.
403 2004-04-22 Peter Barada <peter@the-baradas.com>
405 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
406 descriptions for new EMAC cases.
407 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
408 handle Motorola MAC syntax.
409 Allow disassembly of ColdFire V4e object files.
411 2004-03-16 Alan Modra <amodra@bigpond.net.au>
413 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
415 2004-03-12 Jakub Jelinek <jakub@redhat.com>
417 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
419 2004-03-12 Michal Ludvig <mludvig@suse.cz>
421 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
423 2004-03-12 Michal Ludvig <mludvig@suse.cz>
425 * i386.h (i386_optab): Added xstore/xcrypt insns.
427 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
429 * h8300.h (32bit ldc/stc): Add relaxing support.
431 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
433 * h8300.h (BITOP): Pass MEMRELAX flag.
435 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
437 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
440 For older changes see ChangeLog-9103
446 version-control: never