include/opcode/ChangeLog

   1 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         * i386.h: Add entries from config/tc-i386.h and move tables
   4         to opcodes/i386-opc.h.
   5
   6 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
   7
   8         * i386.h (FloatDR): Removed.
   9         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
  10
  11 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
  12
  13         * spu-insns.h: Add soma double-float insns.
  14
  15 2007-02-20  Thiemo Seufer  <ths@mips.com>
  16             Chao-Ying Fu  <fu@mips.com>
  17
  18         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
  19         (INSN_DSPR2): Add flag for DSP R2 instructions.
  20         (M_BALIGN): New macro.
  21
  22 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
  23
  24         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
  25         and Seg3ShortFrom with Shortform.
  26
  27 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
  28
  29         PR gas/4027
  30         * i386.h (i386_optab): Put the real "test" before the pseudo
  31         one.
  32
  33 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
  34
  35         * m68k.h (m68010up): OR fido_a.
  36
  37 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
  38
  39         * m68k.h (fido_a): New.
  40
  41 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
  42
  43         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
  44         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
  45         values.
  46
  47 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
  48
  49         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
  50
  51 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
  52
  53         * score-inst.h (enum score_insn_type): Add Insn_internal.
  54
  55 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
  56             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
  57             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
  58             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
  59             Alan Modra  <amodra@bigpond.net.au>
  60
  61         * spu-insns.h: New file.
  62         * spu.h: New file.
  63
  64 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
  65
  66         * ppc.h (PPC_OPCODE_CELL): Define.
  67
  68 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
  69
  70         * i386.h :  Modify opcode to support for the change in POPCNT opcode
  71         in amdfam10 architecture.
  72
  73 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
  74
  75         * i386.h: Replace CpuMNI with CpuSSSE3.
  76
  77 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
  78             Joseph Myers  <joseph@codesourcery.com>
  79             Ian Lance Taylor  <ian@wasabisystems.com>
  80             Ben Elliston  <bje@wasabisystems.com>
  81
  82         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
  83
  84 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
  85
  86         * score-datadep.h: New file.
  87         * score-inst.h: New file.
  88
  89 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
  90
  91         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
  92         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
  93         movdq2q and movq2dq.
  94
  95 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
  96            Michael Meissner             <michael.meissner@amd.com>
  97
  98         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
  99
 100 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 101
 102         * i386.h (i386_optab): Add "nop" with memory reference.
 103
 104 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 105
 106         * i386.h (i386_optab): Update comment for 64bit NOP.
 107
 108 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 109             Anton Blanchard  <anton@samba.org>
 110
 111         * ppc.h (PPC_OPCODE_POWER6): Define.
 112         Adjust whitespace.
 113
 114 2006-06-05  Thiemo Seufer  <ths@mips.com>
 115
 116         * mips.h: Improve description of MT flags.
 117
 118 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 119
 120         * m68k.h (mcf_mask): Define.
 121
 122 2006-05-05  Thiemo Seufer  <ths@mips.com>
 123             David Ung  <davidu@mips.com>
 124
 125         * mips.h (enum): Add macro M_CACHE_AB.
 126
 127 2006-05-04  Thiemo Seufer  <ths@mips.com>
 128             Nigel Stephens  <nigel@mips.com>
 129             David Ung  <davidu@mips.com>
 130
 131         * mips.h: Add INSN_SMARTMIPS define.
 132
 133 2006-04-30  Thiemo Seufer  <ths@mips.com>
 134             David Ung  <davidu@mips.com>
 135
 136         * mips.h: Defines udi bits and masks.  Add description of
 137         characters which may appear in the args field of udi
 138         instructions.
 139
 140 2006-04-26  Thiemo Seufer  <ths@networkno.de>
 141
 142         * mips.h: Improve comments describing the bitfield instruction
 143         fields.
 144
 145 2006-04-26  Julian Brown  <julian@codesourcery.com>
 146
 147         * arm.h (FPU_VFP_EXT_V3): Define constant.
 148         (FPU_NEON_EXT_V1): Likewise.
 149         (FPU_VFP_HARD): Update.
 150         (FPU_VFP_V3): Define macro.
 151         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 152
 153 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 154
 155         * avr.h (AVR_ISA_PWMx): New.
 156
 157 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 158
 159         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 160         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 161         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 162         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 163         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 164
 165 2006-03-10  Paul Brook  <paul@codesourcery.com>
 166
 167         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 168
 169 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 170
 171         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 172         first.  Correct mask of bb "B" opcode.
 173
 174 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 175
 176         * i386.h (i386_optab): Support Intel Merom New Instructions.
 177
 178 2006-02-24  Paul Brook  <paul@codesourcery.com>
 179
 180         * arm.h: Add V7 feature bits.
 181
 182 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 183
 184         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 185
 186 2006-01-31  Paul Brook  <paul@codesourcery.com>
 187         Richard Earnshaw <rearnsha@arm.com>
 188
 189         * arm.h: Use ARM_CPU_FEATURE.
 190         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 191         (arm_feature_set): Change to a structure.
 192         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 193         ARM_FEATURE): New macros.
 194
 195 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 196
 197         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 198         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 199         (ADD_PC_INCR_OPCODE): Don't define.
 200
 201 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 202
 203         PR gas/1874
 204         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 205
 206 2005-11-14  David Ung  <davidu@mips.com>
 207
 208         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 209         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 210         save/restore encoding of the args field.
 211
 212 2005-10-28  Dave Brolley  <brolley@redhat.com>
 213
 214         Contribute the following changes:
 215         2005-02-16  Dave Brolley  <brolley@redhat.com>
 216
 217         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 218         cgen_isa_mask_* to cgen_bitset_*.
 219         * cgen.h: Likewise.
 220
 221         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 222
 223         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 224         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 225         (CGEN_CPU_TABLE): Make isas a ponter.
 226
 227         2003-09-29  Dave Brolley  <brolley@redhat.com>
 228
 229         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 230         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 231         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 232
 233         2002-12-13  Dave Brolley  <brolley@redhat.com>
 234
 235         * cgen.h (symcat.h): #include it.
 236         (cgen-bitset.h): #include it.
 237         (CGEN_ATTR_VALUE_TYPE): Now a union.
 238         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 239         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 240         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 241         * cgen-bitset.h: New file.
 242
 243 2005-09-30  Catherine Moore  <clm@cm00re.com>
 244
 245         * bfin.h: New file.
 246
 247 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 248
 249         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 250         indirect operands.
 251
 252 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 253
 254         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 255         Add FLAG_STRICT to pa10 ftest opcode.
 256
 257 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 258
 259         * hppa.h (pa_opcodes): Remove lha entries.
 260
 261 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 262
 263         * hppa.h (FLAG_STRICT): Revise comment.
 264         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 265         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 266         entries for "fdc".
 267
 268 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 269
 270         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 271
 272 2005-09-06  Chao-ying Fu  <fu@mips.com>
 273
 274         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 275         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 276         define.
 277         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 278         (INSN_ASE_MASK): Update to include INSN_MT.
 279         (INSN_MT): New define for MT ASE.
 280
 281 2005-08-25  Chao-ying Fu  <fu@mips.com>
 282
 283         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 284         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 285         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 286         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 287         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 288         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 289         instructions.
 290         (INSN_DSP): New define for DSP ASE.
 291
 292 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 293
 294         * a29k.h: Delete.
 295
 296 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 297
 298         * ppc.h (PPC_OPCODE_E300): Define.
 299
 300 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 301
 302         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 303
 304 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 305
 306         PR gas/336
 307         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 308         and pitlb.
 309
 310 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 311
 312         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 313         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 314         Add movq-s as 64-bit variants of movd-s.
 315
 316 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 317
 318         * hppa.h: Fix punctuation in comment.
 319
 320         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 321         implicit space-register addressing.  Set space-register bits on opcodes
 322         using implicit space-register addressing.  Add various missing pa20
 323         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 324         space-register addressing.  Use "fE" instead of "fe" in various
 325         fstw opcodes.
 326
 327 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 328
 329         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 330
 331 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 332
 333         * i386.h (i386_optab): Support Intel VMX Instructions.
 334
 335 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 336
 337         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 338
 339 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 340
 341         * i386.h (i386_optab): Add new insns.
 342
 343 2005-07-01  Nick Clifton  <nickc@redhat.com>
 344
 345         * sparc.h: Add typedefs to structure declarations.
 346
 347 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 348
 349         PR 1013
 350         * i386.h (i386_optab): Update comments for 64bit addressing on
 351         mov. Allow 64bit addressing for mov and movq.
 352
 353 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 354
 355         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 356         respectively, in various floating-point load and store patterns.
 357
 358 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 359
 360         * hppa.h (FLAG_STRICT): Correct comment.
 361         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 362         PA 2.0 mneumonics when equivalent.  Entries with cache control
 363         completers now require PA 1.1.  Adjust whitespace.
 364
 365 2005-05-19  Anton Blanchard  <anton@samba.org>
 366
 367         * ppc.h (PPC_OPCODE_POWER5): Define.
 368
 369 2005-05-10  Nick Clifton  <nickc@redhat.com>
 370
 371         * Update the address and phone number of the FSF organization in
 372         the GPL notices in the following files:
 373         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 374         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 375         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 376         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 377         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 378         tic54x.h, tic80.h, v850.h, vax.h
 379
 380 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 381
 382         * i386.h (i386_optab): Add ht and hnt.
 383
 384 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 385
 386         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 387         Add xcrypt-ctr.  Provide aliases without hyphens.
 388
 389 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 390
 391         Moved from ../ChangeLog
 392
 393         2005-04-12  Paul Brook  <paul@codesourcery.com>
 394         * m88k.h: Rename psr macros to avoid conflicts.
 395
 396         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 397         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 398         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 399         and ARM_ARCH_V6ZKT2.
 400
 401         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 402         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 403         Remove redundant instruction types.
 404         (struct argument): X_op - new field.
 405         (struct cst4_entry): Remove.
 406         (no_op_insn): Declare.
 407
 408         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 409         * crx.h (enum argtype): Rename types, remove unused types.
 410
 411         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 412         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 413         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 414         (enum operand_type): Rearrange operands, edit comments.
 415         replace us<N> with ui<N> for unsigned immediate.
 416         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 417         displacements (respectively).
 418         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 419         (instruction type): Add NO_TYPE_INS.
 420         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 421         (operand_entry): New field - 'flags'.
 422         (operand flags): New.
 423
 424         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 425         * crx.h (operand_type): Remove redundant types i3, i4,
 426         i5, i8, i12.
 427         Add new unsigned immediate types us3, us4, us5, us16.
 428
 429 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 430
 431         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 432         adjust them accordingly.
 433
 434 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 435
 436         * i386.h (i386_optab): Add rdtscp.
 437
 438 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 439
 440         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 441         between memory and segment register. Allow movq for moving between
 442         general-purpose register and segment register.
 443
 444 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 445
 446         PR gas/707
 447         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 448         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 449         fnstsw.
 450
 451 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 452
 453         * m68k.h (m68008, m68ec030, m68882): Remove.
 454         (m68k_mask): New.
 455         (cpu_m68k, cpu_cf): New.
 456         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 457         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 458
 459 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 460
 461         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 462         * cgen.h (enum cgen_parse_operand_type): Add
 463         CGEN_PARSE_OPERAND_SYMBOLIC.
 464
 465 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 466
 467         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 468         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 469         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 470
 471 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 472
 473         * mips.h (struct mips_opcode): Add new pinfo2 member.
 474         (INSN_ALIAS): New define for opcode table entries that are
 475         specific instances of another entry, such as 'move' for an 'or'
 476         with a zero operand.
 477         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 478         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 479
 480 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 481
 482         * mips.h (CPU_RM9000): Define.
 483         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 484
 485 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 486
 487         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 488         to/from test registers are illegal in 64-bit mode. Add missing
 489         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 490         (previously one had to explicitly encode a rex64 prefix). Re-enable
 491         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 492         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 493
 494 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 495
 496         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 497         available only with SSE2. Change the MMX additions introduced by SSE
 498         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 499         instructions by their now designated identifier (since combining i686
 500         and 3DNow! does not really imply 3DNow!A).
 501
 502 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 503
 504         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 505         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 506
 507 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 508             Vineet Sharma      <vineets@noida.hcltech.com>
 509
 510         * maxq.h: New file: Disassembly information for the maxq port.
 511
 512 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 513
 514         * i386.h (i386_optab): Put back "movzb".
 515
 516 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 517
 518         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 519         comments.  Remove member cris_ver_sim.  Add members
 520         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 521         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 522         (struct cris_support_reg, struct cris_cond15): New types.
 523         (cris_conds15): Declare.
 524         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 525         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 526         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 527         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 528         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 529         SIZE_FIELD_UNSIGNED.
 530
 531 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 532
 533         * i386.h (sldx_Suf): Remove.
 534         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 535         (q_FP): Define, implying no REX64.
 536         (x_FP, sl_FP): Imply FloatMF.
 537         (i386_optab): Split reg and mem forms of moving from segment registers
 538         so that the memory forms can ignore the 16-/32-bit operand size
 539         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 540         all non-floating-point instructions. Unite 32- and 64-bit forms of
 541         movsx, movzx, and movd. Adjust floating point operations for the above
 542         changes to the *FP macros. Add DefaultSize to floating point control
 543         insns operating on larger memory ranges. Remove left over comments
 544         hinting at certain insns being Intel-syntax ones where the ones
 545         actually meant are already gone.
 546
 547 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 548
 549         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 550         instruction type.
 551
 552 2004-09-30  Paul Brook  <paul@codesourcery.com>
 553
 554         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 555         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 556
 557 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 558
 559         * avr.h: Add support for
 560         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 561
 562 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 563
 564         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 565
 566 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 567
 568         * msp430.h (msp430_opc): Add new instructions.
 569         (msp430_rcodes): Declare new instructions.
 570         (msp430_hcodes): Likewise..
 571
 572 2004-08-13  Nick Clifton  <nickc@redhat.com>
 573
 574         PR/301
 575         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 576         processors.
 577
 578 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 579
 580         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 581
 582 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 583
 584         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 585
 586 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 587
 588         * i386.h: Adjust instruction descriptions to better match the
 589         specification.
 590
 591 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 592
 593         * arm.h: Remove all old content.  Replace with architecture defines
 594         from gas/config/tc-arm.c.
 595
 596 2004-07-09  Andreas Schwab  <schwab@suse.de>
 597
 598         * m68k.h: Fix comment.
 599
 600 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 601
 602         * crx.h: New file.
 603
 604 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 605
 606         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 607
 608 2004-05-24  Peter Barada  <peter@the-baradas.com>
 609
 610         * m68k.h: Add 'size' to m68k_opcode.
 611
 612 2004-05-05  Peter Barada  <peter@the-baradas.com>
 613
 614         * m68k.h: Switch from ColdFire chip name to core variant.
 615
 616 2004-04-22  Peter Barada  <peter@the-baradas.com>
 617
 618         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 619         descriptions for new EMAC cases.
 620         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 621         handle Motorola MAC syntax.
 622         Allow disassembly of ColdFire V4e object files.
 623
 624 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 625
 626         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 627
 628 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 629
 630         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 631
 632 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 633
 634         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 635
 636 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 637
 638         * i386.h (i386_optab): Added xstore/xcrypt insns.
 639
 640 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 641
 642         * h8300.h (32bit ldc/stc): Add relaxing support.
 643
 644 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 645
 646         * h8300.h (BITOP): Pass MEMRELAX flag.
 647
 648 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 649
 650         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 651         except for the H8S.
 652
 653 For older changes see ChangeLog-9103
 654 \f
 655 Local Variables:
 656 mode: change-log
 657 left-margin: 8
 658 fill-column: 74
 659 version-control: never
 660 End: