include/opcode/ChangeLog

   1 2005-10-28  Dave Brolley  <brolley@redhat.com>
   2
   3         Contribute the following changes:
   4         2005-02-16  Dave Brolley  <brolley@redhat.com>
   5
   6         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
   7         cgen_isa_mask_* to cgen_bitset_*.
   8         * cgen.h: Likewise.
   9
  10         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
  11
  12         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
  13         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
  14         (CGEN_CPU_TABLE): Make isas a ponter.
  15
  16         2003-09-29  Dave Brolley  <brolley@redhat.com>
  17
  18         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
  19         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
  20         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
  21
  22         2002-12-13  Dave Brolley  <brolley@redhat.com>
  23
  24         * cgen.h (symcat.h): #include it.
  25         (cgen-bitset.h): #include it.
  26         (CGEN_ATTR_VALUE_TYPE): Now a union.
  27         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
  28         (CGEN_ATTR_ENTRY): 'value' now unsigned.
  29         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
  30         * cgen-bitset.h: New file.
  31
  32 2005-09-30  Catherine Moore  <clm@cm00re.com>
  33
  34         * bfin.h: New file.
  35
  36 2005-10-24  Jan Beulich  <jbeulich@novell.com>
  37
  38         * ia64.h (enum ia64_opnd): Move memory operand out of set of
  39         indirect operands.
  40
  41 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  42
  43         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
  44         Add FLAG_STRICT to pa10 ftest opcode.
  45
  46 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  47
  48         * hppa.h (pa_opcodes): Remove lha entries.
  49
  50 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  51
  52         * hppa.h (FLAG_STRICT): Revise comment.
  53         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
  54         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
  55         entries for "fdc".
  56
  57 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  58
  59         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
  60
  61 2005-09-06  Chao-ying Fu  <fu@mips.com>
  62
  63         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
  64         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
  65         define.
  66         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
  67         (INSN_ASE_MASK): Update to include INSN_MT.
  68         (INSN_MT): New define for MT ASE.
  69
  70 2005-08-25  Chao-ying Fu  <fu@mips.com>
  71
  72         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
  73         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
  74         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
  75         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
  76         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
  77         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
  78         instructions.
  79         (INSN_DSP): New define for DSP ASE.
  80
  81 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
  82
  83         * a29k.h: Delete.
  84
  85 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
  86
  87         * ppc.h (PPC_OPCODE_E300): Define.
  88
  89 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
  90
  91         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
  92
  93 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  94
  95         PR gas/336
  96         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
  97         and pitlb.
  98
  99 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 100
 101         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 102         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 103         Add movq-s as 64-bit variants of movd-s.
 104
 105 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 106
 107         * hppa.h: Fix punctuation in comment.
 108
 109         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 110         implicit space-register addressing.  Set space-register bits on opcodes
 111         using implicit space-register addressing.  Add various missing pa20
 112         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 113         space-register addressing.  Use "fE" instead of "fe" in various
 114         fstw opcodes.
 115
 116 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 117
 118         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 119
 120 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 121
 122         * i386.h (i386_optab): Support Intel VMX Instructions.
 123
 124 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 125
 126         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 127
 128 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 129
 130         * i386.h (i386_optab): Add new insns.
 131
 132 2005-07-01  Nick Clifton  <nickc@redhat.com>
 133
 134         * sparc.h: Add typedefs to structure declarations.
 135
 136 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 137
 138         PR 1013
 139         * i386.h (i386_optab): Update comments for 64bit addressing on
 140         mov. Allow 64bit addressing for mov and movq.
 141
 142 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 143
 144         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 145         respectively, in various floating-point load and store patterns.
 146
 147 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 148
 149         * hppa.h (FLAG_STRICT): Correct comment.
 150         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 151         PA 2.0 mneumonics when equivalent.  Entries with cache control
 152         completers now require PA 1.1.  Adjust whitespace.
 153
 154 2005-05-19  Anton Blanchard  <anton@samba.org>
 155
 156         * ppc.h (PPC_OPCODE_POWER5): Define.
 157
 158 2005-05-10  Nick Clifton  <nickc@redhat.com>
 159
 160         * Update the address and phone number of the FSF organization in
 161         the GPL notices in the following files:
 162         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 163         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 164         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 165         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 166         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 167         tic54x.h, tic80.h, v850.h, vax.h
 168
 169 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 170
 171         * i386.h (i386_optab): Add ht and hnt.
 172
 173 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 174
 175         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 176         Add xcrypt-ctr.  Provide aliases without hyphens.
 177
 178 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 179
 180         Moved from ../ChangeLog
 181
 182         2005-04-12  Paul Brook  <paul@codesourcery.com>
 183         * m88k.h: Rename psr macros to avoid conflicts.
 184
 185         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 186         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 187         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 188         and ARM_ARCH_V6ZKT2.
 189
 190         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 191         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 192         Remove redundant instruction types.
 193         (struct argument): X_op - new field.
 194         (struct cst4_entry): Remove.
 195         (no_op_insn): Declare.
 196
 197         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 198         * crx.h (enum argtype): Rename types, remove unused types.
 199
 200         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 201         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 202         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 203         (enum operand_type): Rearrange operands, edit comments.
 204         replace us<N> with ui<N> for unsigned immediate.
 205         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 206         displacements (respectively).
 207         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 208         (instruction type): Add NO_TYPE_INS.
 209         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 210         (operand_entry): New field - 'flags'.
 211         (operand flags): New.
 212
 213         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 214         * crx.h (operand_type): Remove redundant types i3, i4,
 215         i5, i8, i12.
 216         Add new unsigned immediate types us3, us4, us5, us16.
 217
 218 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 219
 220         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 221         adjust them accordingly.
 222
 223 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 224
 225         * i386.h (i386_optab): Add rdtscp.
 226
 227 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 228
 229         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 230         between memory and segment register. Allow movq for moving between
 231         general-purpose register and segment register.
 232
 233 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 234
 235         PR gas/707
 236         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 237         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 238         fnstsw.
 239
 240 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 241
 242         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 243         * cgen.h (enum cgen_parse_operand_type): Add
 244         CGEN_PARSE_OPERAND_SYMBOLIC.
 245
 246 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 247
 248         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 249         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 250         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 251
 252 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 253
 254         * mips.h (struct mips_opcode): Add new pinfo2 member.
 255         (INSN_ALIAS): New define for opcode table entries that are
 256         specific instances of another entry, such as 'move' for an 'or'
 257         with a zero operand.
 258         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 259         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 260
 261 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 262
 263         * mips.h (CPU_RM9000): Define.
 264         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 265
 266 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 267
 268         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 269         to/from test registers are illegal in 64-bit mode. Add missing
 270         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 271         (previously one had to explicitly encode a rex64 prefix). Re-enable
 272         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 273         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 274
 275 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 276
 277         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 278         available only with SSE2. Change the MMX additions introduced by SSE
 279         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 280         instructions by their now designated identifier (since combining i686
 281         and 3DNow! does not really imply 3DNow!A).
 282
 283 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 284
 285         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 286         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 287
 288 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 289             Vineet Sharma      <vineets@noida.hcltech.com>
 290
 291         * maxq.h: New file: Disassembly information for the maxq port.
 292
 293 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 294
 295         * i386.h (i386_optab): Put back "movzb".
 296
 297 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 298
 299         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 300         comments.  Remove member cris_ver_sim.  Add members
 301         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 302         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 303         (struct cris_support_reg, struct cris_cond15): New types.
 304         (cris_conds15): Declare.
 305         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 306         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 307         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 308         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 309         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 310         SIZE_FIELD_UNSIGNED.
 311
 312 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 313
 314         * i386.h (sldx_Suf): Remove.
 315         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 316         (q_FP): Define, implying no REX64.
 317         (x_FP, sl_FP): Imply FloatMF.
 318         (i386_optab): Split reg and mem forms of moving from segment registers
 319         so that the memory forms can ignore the 16-/32-bit operand size
 320         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 321         all non-floating-point instructions. Unite 32- and 64-bit forms of
 322         movsx, movzx, and movd. Adjust floating point operations for the above
 323         changes to the *FP macros. Add DefaultSize to floating point control
 324         insns operating on larger memory ranges. Remove left over comments
 325         hinting at certain insns being Intel-syntax ones where the ones
 326         actually meant are already gone.
 327
 328 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 329
 330         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 331         instruction type.
 332
 333 2004-09-30  Paul Brook  <paul@codesourcery.com>
 334
 335         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 336         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 337
 338 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 339
 340         * avr.h: Add support for
 341         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 342
 343 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 344
 345         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 346
 347 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 348
 349         * msp430.h (msp430_opc): Add new instructions.
 350         (msp430_rcodes): Declare new instructions.
 351         (msp430_hcodes): Likewise..
 352
 353 2004-08-13  Nick Clifton  <nickc@redhat.com>
 354
 355         PR/301
 356         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 357         processors.
 358
 359 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 360
 361         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 362
 363 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 364
 365         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 366
 367 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 368
 369         * i386.h: Adjust instruction descriptions to better match the
 370         specification.
 371
 372 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 373
 374         * arm.h: Remove all old content.  Replace with architecture defines
 375         from gas/config/tc-arm.c.
 376
 377 2004-07-09  Andreas Schwab  <schwab@suse.de>
 378
 379         * m68k.h: Fix comment.
 380
 381 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 382
 383         * crx.h: New file.
 384
 385 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 386
 387         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 388
 389 2004-05-24  Peter Barada  <peter@the-baradas.com>
 390
 391         * m68k.h: Add 'size' to m68k_opcode.
 392
 393 2004-05-05  Peter Barada  <peter@the-baradas.com>
 394
 395         * m68k.h: Switch from ColdFire chip name to core variant.
 396
 397 2004-04-22  Peter Barada  <peter@the-baradas.com>
 398
 399         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 400         descriptions for new EMAC cases.
 401         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 402         handle Motorola MAC syntax.
 403         Allow disassembly of ColdFire V4e object files.
 404
 405 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 406
 407         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 408
 409 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 410
 411         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 412
 413 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 414
 415         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 416
 417 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 418
 419         * i386.h (i386_optab): Added xstore/xcrypt insns.
 420
 421 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 422
 423         * h8300.h (32bit ldc/stc): Add relaxing support.
 424
 425 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 426
 427         * h8300.h (BITOP): Pass MEMRELAX flag.
 428
 429 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 430
 431         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 432         except for the H8S.
 433
 434 For older changes see ChangeLog-9103
 435 \f
 436 Local Variables:
 437 mode: change-log
 438 left-margin: 8
 439 fill-column: 74
 440 version-control: never
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