include/opcode/ChangeLog

   1 2005-07-05  Jan Beulich  <jbeulich@novell.com>
   2
   3         * i386.h (i386_optab): Add new insns.
   4
   5 2005-07-01  Nick Clifton  <nickc@redhat.com>
   6
   7         * sparc.h: Add typedefs to structure declarations.
   8
   9 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
  10
  11         PR 1013
  12         * i386.h (i386_optab): Update comments for 64bit addressing on
  13         mov. Allow 64bit addressing for mov and movq.
  14
  15 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  16
  17         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
  18         respectively, in various floating-point load and store patterns.
  19
  20 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  21
  22         * hppa.h (FLAG_STRICT): Correct comment.
  23         (pa_opcodes): Update load and store entries to allow both PA 1.X and
  24         PA 2.0 mneumonics when equivalent.  Entries with cache control
  25         completers now require PA 1.1.  Adjust whitespace.
  26
  27 2005-05-19  Anton Blanchard  <anton@samba.org>
  28
  29         * ppc.h (PPC_OPCODE_POWER5): Define.
  30
  31 2005-05-10  Nick Clifton  <nickc@redhat.com>
  32
  33         * Update the address and phone number of the FSF organization in
  34         the GPL notices in the following files:
  35         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
  36         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
  37         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
  38         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
  39         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
  40         tic54x.h, tic80.h, v850.h, vax.h
  41
  42 2005-05-09  Jan Beulich  <jbeulich@novell.com>
  43
  44         * i386.h (i386_optab): Add ht and hnt.
  45
  46 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
  47
  48         * i386.h: Insert hyphens into selected VIA PadLock extensions.
  49         Add xcrypt-ctr.  Provide aliases without hyphens.
  50
  51 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
  52
  53         Moved from ../ChangeLog
  54
  55         2005-04-12  Paul Brook  <paul@codesourcery.com>
  56         * m88k.h: Rename psr macros to avoid conflicts.
  57
  58         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
  59         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
  60         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
  61         and ARM_ARCH_V6ZKT2.
  62
  63         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
  64         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
  65         Remove redundant instruction types.
  66         (struct argument): X_op - new field.
  67         (struct cst4_entry): Remove.
  68         (no_op_insn): Declare.
  69
  70         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
  71         * crx.h (enum argtype): Rename types, remove unused types.
  72
  73         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
  74         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
  75         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
  76         (enum operand_type): Rearrange operands, edit comments.
  77         replace us<N> with ui<N> for unsigned immediate.
  78         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
  79         displacements (respectively).
  80         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
  81         (instruction type): Add NO_TYPE_INS.
  82         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
  83         (operand_entry): New field - 'flags'.
  84         (operand flags): New.
  85
  86         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
  87         * crx.h (operand_type): Remove redundant types i3, i4,
  88         i5, i8, i12.
  89         Add new unsigned immediate types us3, us4, us5, us16.
  90
  91 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
  92
  93         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
  94         adjust them accordingly.
  95
  96 2005-04-01  Jan Beulich  <jbeulich@novell.com>
  97
  98         * i386.h (i386_optab): Add rdtscp.
  99
 100 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 101
 102         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 103         between memory and segment register. Allow movq for moving between
 104         general-purpose register and segment register.
 105
 106 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 107
 108         PR gas/707
 109         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 110         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 111         fnstsw.
 112
 113 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 114
 115         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 116         * cgen.h (enum cgen_parse_operand_type): Add
 117         CGEN_PARSE_OPERAND_SYMBOLIC.
 118
 119 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 120
 121         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 122         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 123         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 124
 125 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 126
 127         * mips.h (struct mips_opcode): Add new pinfo2 member.
 128         (INSN_ALIAS): New define for opcode table entries that are
 129         specific instances of another entry, such as 'move' for an 'or'
 130         with a zero operand.
 131         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 132         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 133
 134 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 135
 136         * mips.h (CPU_RM9000): Define.
 137         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 138
 139 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 140
 141         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 142         to/from test registers are illegal in 64-bit mode. Add missing
 143         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 144         (previously one had to explicitly encode a rex64 prefix). Re-enable
 145         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 146         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 147
 148 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 149
 150         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 151         available only with SSE2. Change the MMX additions introduced by SSE
 152         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 153         instructions by their now designated identifier (since combining i686
 154         and 3DNow! does not really imply 3DNow!A).
 155
 156 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 157
 158         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 159         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 160
 161 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 162             Vineet Sharma      <vineets@noida.hcltech.com>
 163
 164         * maxq.h: New file: Disassembly information for the maxq port.
 165
 166 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 167
 168         * i386.h (i386_optab): Put back "movzb".
 169
 170 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 171
 172         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 173         comments.  Remove member cris_ver_sim.  Add members
 174         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 175         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 176         (struct cris_support_reg, struct cris_cond15): New types.
 177         (cris_conds15): Declare.
 178         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 179         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 180         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 181         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 182         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 183         SIZE_FIELD_UNSIGNED.
 184
 185 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 186
 187         * i386.h (sldx_Suf): Remove.
 188         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 189         (q_FP): Define, implying no REX64.
 190         (x_FP, sl_FP): Imply FloatMF.
 191         (i386_optab): Split reg and mem forms of moving from segment registers
 192         so that the memory forms can ignore the 16-/32-bit operand size
 193         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 194         all non-floating-point instructions. Unite 32- and 64-bit forms of
 195         movsx, movzx, and movd. Adjust floating point operations for the above
 196         changes to the *FP macros. Add DefaultSize to floating point control
 197         insns operating on larger memory ranges. Remove left over comments
 198         hinting at certain insns being Intel-syntax ones where the ones
 199         actually meant are already gone.
 200
 201 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 202
 203         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 204         instruction type.
 205
 206 2004-09-30  Paul Brook  <paul@codesourcery.com>
 207
 208         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 209         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 210
 211 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 212
 213         * avr.h: Add support for
 214         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 215
 216 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 217
 218         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 219
 220 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 221
 222         * msp430.h (msp430_opc): Add new instructions.
 223         (msp430_rcodes): Declare new instructions.
 224         (msp430_hcodes): Likewise..
 225
 226 2004-08-13  Nick Clifton  <nickc@redhat.com>
 227
 228         PR/301
 229         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 230         processors.
 231
 232 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 233
 234         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 235
 236 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 237
 238         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 239
 240 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 241
 242         * i386.h: Adjust instruction descriptions to better match the
 243         specification.
 244
 245 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 246
 247         * arm.h: Remove all old content.  Replace with architecture defines
 248         from gas/config/tc-arm.c.
 249
 250 2004-07-09  Andreas Schwab  <schwab@suse.de>
 251
 252         * m68k.h: Fix comment.
 253
 254 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 255
 256         * crx.h: New file.
 257
 258 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 259
 260         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 261
 262 2004-05-24  Peter Barada  <peter@the-baradas.com>
 263
 264         * m68k.h: Add 'size' to m68k_opcode.
 265
 266 2004-05-05  Peter Barada  <peter@the-baradas.com>
 267
 268         * m68k.h: Switch from ColdFire chip name to core variant.
 269
 270 2004-04-22  Peter Barada  <peter@the-baradas.com>
 271
 272         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 273         descriptions for new EMAC cases.
 274         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 275         handle Motorola MAC syntax.
 276         Allow disassembly of ColdFire V4e object files.
 277
 278 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 279
 280         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 281
 282 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 283
 284         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 285
 286 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 287
 288         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 289
 290 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 291
 292         * i386.h (i386_optab): Added xstore/xcrypt insns.
 293
 294 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 295
 296         * h8300.h (32bit ldc/stc): Add relaxing support.
 297
 298 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 299
 300         * h8300.h (BITOP): Pass MEMRELAX flag.
 301
 302 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 303
 304         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 305         except for the H8S.
 306
 307 For older changes see ChangeLog-9103
 308 \f
 309 Local Variables:
 310 mode: change-log
 311 left-margin: 8
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 313 version-control: never
 314 End: