include/opcode/ChangeLog

   1 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
   2
   3         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
   4         first.  Correct mask of bb "B" opcode.
   5
   6 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
   7
   8         * i386.h (i386_optab): Support Intel Merom New Instructions.
   9
  10 2006-02-24  Paul Brook  <paul@codesourcery.com>
  11
  12         * arm.h: Add V7 feature bits.
  13
  14 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
  15
  16         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
  17
  18 2006-01-31  Paul Brook  <paul@codesourcery.com>
  19         Richard Earnshaw <rearnsha@arm.com>
  20
  21         * arm.h: Use ARM_CPU_FEATURE.
  22         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
  23         (arm_feature_set): Change to a structure.
  24         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
  25         ARM_FEATURE): New macros.
  26
  27 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
  28
  29         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
  30         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
  31         (ADD_PC_INCR_OPCODE): Don't define.
  32
  33 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
  34
  35         PR gas/1874
  36         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
  37
  38 2005-11-14  David Ung  <davidu@mips.com>
  39
  40         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
  41         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
  42         save/restore encoding of the args field.
  43
  44 2005-10-28  Dave Brolley  <brolley@redhat.com>
  45
  46         Contribute the following changes:
  47         2005-02-16  Dave Brolley  <brolley@redhat.com>
  48
  49         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
  50         cgen_isa_mask_* to cgen_bitset_*.
  51         * cgen.h: Likewise.
  52
  53         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
  54
  55         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
  56         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
  57         (CGEN_CPU_TABLE): Make isas a ponter.
  58
  59         2003-09-29  Dave Brolley  <brolley@redhat.com>
  60
  61         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
  62         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
  63         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
  64
  65         2002-12-13  Dave Brolley  <brolley@redhat.com>
  66
  67         * cgen.h (symcat.h): #include it.
  68         (cgen-bitset.h): #include it.
  69         (CGEN_ATTR_VALUE_TYPE): Now a union.
  70         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
  71         (CGEN_ATTR_ENTRY): 'value' now unsigned.
  72         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
  73         * cgen-bitset.h: New file.
  74
  75 2005-09-30  Catherine Moore  <clm@cm00re.com>
  76
  77         * bfin.h: New file.
  78
  79 2005-10-24  Jan Beulich  <jbeulich@novell.com>
  80
  81         * ia64.h (enum ia64_opnd): Move memory operand out of set of
  82         indirect operands.
  83
  84 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  85
  86         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
  87         Add FLAG_STRICT to pa10 ftest opcode.
  88
  89 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  90
  91         * hppa.h (pa_opcodes): Remove lha entries.
  92
  93 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  94
  95         * hppa.h (FLAG_STRICT): Revise comment.
  96         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
  97         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
  98         entries for "fdc".
  99
 100 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 101
 102         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 103
 104 2005-09-06  Chao-ying Fu  <fu@mips.com>
 105
 106         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 107         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 108         define.
 109         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 110         (INSN_ASE_MASK): Update to include INSN_MT.
 111         (INSN_MT): New define for MT ASE.
 112
 113 2005-08-25  Chao-ying Fu  <fu@mips.com>
 114
 115         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 116         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 117         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 118         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 119         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 120         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 121         instructions.
 122         (INSN_DSP): New define for DSP ASE.
 123
 124 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 125
 126         * a29k.h: Delete.
 127
 128 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 129
 130         * ppc.h (PPC_OPCODE_E300): Define.
 131
 132 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 133
 134         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 135
 136 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 137
 138         PR gas/336
 139         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 140         and pitlb.
 141
 142 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 143
 144         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 145         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 146         Add movq-s as 64-bit variants of movd-s.
 147
 148 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 149
 150         * hppa.h: Fix punctuation in comment.
 151
 152         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 153         implicit space-register addressing.  Set space-register bits on opcodes
 154         using implicit space-register addressing.  Add various missing pa20
 155         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 156         space-register addressing.  Use "fE" instead of "fe" in various
 157         fstw opcodes.
 158
 159 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 160
 161         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 162
 163 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 164
 165         * i386.h (i386_optab): Support Intel VMX Instructions.
 166
 167 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 168
 169         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 170
 171 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 172
 173         * i386.h (i386_optab): Add new insns.
 174
 175 2005-07-01  Nick Clifton  <nickc@redhat.com>
 176
 177         * sparc.h: Add typedefs to structure declarations.
 178
 179 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 180
 181         PR 1013
 182         * i386.h (i386_optab): Update comments for 64bit addressing on
 183         mov. Allow 64bit addressing for mov and movq.
 184
 185 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 186
 187         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 188         respectively, in various floating-point load and store patterns.
 189
 190 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 191
 192         * hppa.h (FLAG_STRICT): Correct comment.
 193         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 194         PA 2.0 mneumonics when equivalent.  Entries with cache control
 195         completers now require PA 1.1.  Adjust whitespace.
 196
 197 2005-05-19  Anton Blanchard  <anton@samba.org>
 198
 199         * ppc.h (PPC_OPCODE_POWER5): Define.
 200
 201 2005-05-10  Nick Clifton  <nickc@redhat.com>
 202
 203         * Update the address and phone number of the FSF organization in
 204         the GPL notices in the following files:
 205         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 206         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 207         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 208         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 209         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 210         tic54x.h, tic80.h, v850.h, vax.h
 211
 212 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 213
 214         * i386.h (i386_optab): Add ht and hnt.
 215
 216 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 217
 218         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 219         Add xcrypt-ctr.  Provide aliases without hyphens.
 220
 221 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 222
 223         Moved from ../ChangeLog
 224
 225         2005-04-12  Paul Brook  <paul@codesourcery.com>
 226         * m88k.h: Rename psr macros to avoid conflicts.
 227
 228         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 229         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 230         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 231         and ARM_ARCH_V6ZKT2.
 232
 233         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 234         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 235         Remove redundant instruction types.
 236         (struct argument): X_op - new field.
 237         (struct cst4_entry): Remove.
 238         (no_op_insn): Declare.
 239
 240         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 241         * crx.h (enum argtype): Rename types, remove unused types.
 242
 243         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 244         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 245         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 246         (enum operand_type): Rearrange operands, edit comments.
 247         replace us<N> with ui<N> for unsigned immediate.
 248         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 249         displacements (respectively).
 250         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 251         (instruction type): Add NO_TYPE_INS.
 252         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 253         (operand_entry): New field - 'flags'.
 254         (operand flags): New.
 255
 256         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 257         * crx.h (operand_type): Remove redundant types i3, i4,
 258         i5, i8, i12.
 259         Add new unsigned immediate types us3, us4, us5, us16.
 260
 261 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 262
 263         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 264         adjust them accordingly.
 265
 266 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 267
 268         * i386.h (i386_optab): Add rdtscp.
 269
 270 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 271
 272         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 273         between memory and segment register. Allow movq for moving between
 274         general-purpose register and segment register.
 275
 276 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 277
 278         PR gas/707
 279         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 280         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 281         fnstsw.
 282
 283 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 284
 285         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 286         * cgen.h (enum cgen_parse_operand_type): Add
 287         CGEN_PARSE_OPERAND_SYMBOLIC.
 288
 289 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 290
 291         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 292         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 293         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 294
 295 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 296
 297         * mips.h (struct mips_opcode): Add new pinfo2 member.
 298         (INSN_ALIAS): New define for opcode table entries that are
 299         specific instances of another entry, such as 'move' for an 'or'
 300         with a zero operand.
 301         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 302         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 303
 304 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 305
 306         * mips.h (CPU_RM9000): Define.
 307         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 308
 309 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 310
 311         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 312         to/from test registers are illegal in 64-bit mode. Add missing
 313         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 314         (previously one had to explicitly encode a rex64 prefix). Re-enable
 315         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 316         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 317
 318 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 319
 320         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 321         available only with SSE2. Change the MMX additions introduced by SSE
 322         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 323         instructions by their now designated identifier (since combining i686
 324         and 3DNow! does not really imply 3DNow!A).
 325
 326 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 327
 328         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 329         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 330
 331 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 332             Vineet Sharma      <vineets@noida.hcltech.com>
 333
 334         * maxq.h: New file: Disassembly information for the maxq port.
 335
 336 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 337
 338         * i386.h (i386_optab): Put back "movzb".
 339
 340 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 341
 342         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 343         comments.  Remove member cris_ver_sim.  Add members
 344         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 345         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 346         (struct cris_support_reg, struct cris_cond15): New types.
 347         (cris_conds15): Declare.
 348         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 349         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 350         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 351         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 352         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 353         SIZE_FIELD_UNSIGNED.
 354
 355 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 356
 357         * i386.h (sldx_Suf): Remove.
 358         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 359         (q_FP): Define, implying no REX64.
 360         (x_FP, sl_FP): Imply FloatMF.
 361         (i386_optab): Split reg and mem forms of moving from segment registers
 362         so that the memory forms can ignore the 16-/32-bit operand size
 363         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 364         all non-floating-point instructions. Unite 32- and 64-bit forms of
 365         movsx, movzx, and movd. Adjust floating point operations for the above
 366         changes to the *FP macros. Add DefaultSize to floating point control
 367         insns operating on larger memory ranges. Remove left over comments
 368         hinting at certain insns being Intel-syntax ones where the ones
 369         actually meant are already gone.
 370
 371 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 372
 373         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 374         instruction type.
 375
 376 2004-09-30  Paul Brook  <paul@codesourcery.com>
 377
 378         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 379         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 380
 381 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 382
 383         * avr.h: Add support for
 384         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 385
 386 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 387
 388         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 389
 390 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 391
 392         * msp430.h (msp430_opc): Add new instructions.
 393         (msp430_rcodes): Declare new instructions.
 394         (msp430_hcodes): Likewise..
 395
 396 2004-08-13  Nick Clifton  <nickc@redhat.com>
 397
 398         PR/301
 399         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 400         processors.
 401
 402 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 403
 404         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 405
 406 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 407
 408         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 409
 410 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 411
 412         * i386.h: Adjust instruction descriptions to better match the
 413         specification.
 414
 415 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 416
 417         * arm.h: Remove all old content.  Replace with architecture defines
 418         from gas/config/tc-arm.c.
 419
 420 2004-07-09  Andreas Schwab  <schwab@suse.de>
 421
 422         * m68k.h: Fix comment.
 423
 424 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 425
 426         * crx.h: New file.
 427
 428 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 429
 430         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 431
 432 2004-05-24  Peter Barada  <peter@the-baradas.com>
 433
 434         * m68k.h: Add 'size' to m68k_opcode.
 435
 436 2004-05-05  Peter Barada  <peter@the-baradas.com>
 437
 438         * m68k.h: Switch from ColdFire chip name to core variant.
 439
 440 2004-04-22  Peter Barada  <peter@the-baradas.com>
 441
 442         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 443         descriptions for new EMAC cases.
 444         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 445         handle Motorola MAC syntax.
 446         Allow disassembly of ColdFire V4e object files.
 447
 448 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 449
 450         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 451
 452 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 453
 454         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 455
 456 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 457
 458         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 459
 460 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 461
 462         * i386.h (i386_optab): Added xstore/xcrypt insns.
 463
 464 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 465
 466         * h8300.h (32bit ldc/stc): Add relaxing support.
 467
 468 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 469
 470         * h8300.h (BITOP): Pass MEMRELAX flag.
 471
 472 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 473
 474         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 475         except for the H8S.
 476
 477 For older changes see ChangeLog-9103
 478 \f
 479 Local Variables:
 480 mode: change-log
 481 left-margin: 8
 482 fill-column: 74
 483 version-control: never
 484 End: