include/opcode/ChangeLog

   1 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
   2
   3         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
   4
   5 2005-07-05  Jan Beulich  <jbeulich@novell.com>
   6
   7         * i386.h (i386_optab): Add new insns.
   8
   9 2005-07-01  Nick Clifton  <nickc@redhat.com>
  10
  11         * sparc.h: Add typedefs to structure declarations.
  12
  13 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
  14
  15         PR 1013
  16         * i386.h (i386_optab): Update comments for 64bit addressing on
  17         mov. Allow 64bit addressing for mov and movq.
  18
  19 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  20
  21         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
  22         respectively, in various floating-point load and store patterns.
  23
  24 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  25
  26         * hppa.h (FLAG_STRICT): Correct comment.
  27         (pa_opcodes): Update load and store entries to allow both PA 1.X and
  28         PA 2.0 mneumonics when equivalent.  Entries with cache control
  29         completers now require PA 1.1.  Adjust whitespace.
  30
  31 2005-05-19  Anton Blanchard  <anton@samba.org>
  32
  33         * ppc.h (PPC_OPCODE_POWER5): Define.
  34
  35 2005-05-10  Nick Clifton  <nickc@redhat.com>
  36
  37         * Update the address and phone number of the FSF organization in
  38         the GPL notices in the following files:
  39         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
  40         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
  41         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
  42         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
  43         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
  44         tic54x.h, tic80.h, v850.h, vax.h
  45
  46 2005-05-09  Jan Beulich  <jbeulich@novell.com>
  47
  48         * i386.h (i386_optab): Add ht and hnt.
  49
  50 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
  51
  52         * i386.h: Insert hyphens into selected VIA PadLock extensions.
  53         Add xcrypt-ctr.  Provide aliases without hyphens.
  54
  55 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
  56
  57         Moved from ../ChangeLog
  58
  59         2005-04-12  Paul Brook  <paul@codesourcery.com>
  60         * m88k.h: Rename psr macros to avoid conflicts.
  61
  62         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
  63         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
  64         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
  65         and ARM_ARCH_V6ZKT2.
  66
  67         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
  68         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
  69         Remove redundant instruction types.
  70         (struct argument): X_op - new field.
  71         (struct cst4_entry): Remove.
  72         (no_op_insn): Declare.
  73
  74         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
  75         * crx.h (enum argtype): Rename types, remove unused types.
  76
  77         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
  78         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
  79         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
  80         (enum operand_type): Rearrange operands, edit comments.
  81         replace us<N> with ui<N> for unsigned immediate.
  82         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
  83         displacements (respectively).
  84         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
  85         (instruction type): Add NO_TYPE_INS.
  86         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
  87         (operand_entry): New field - 'flags'.
  88         (operand flags): New.
  89
  90         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
  91         * crx.h (operand_type): Remove redundant types i3, i4,
  92         i5, i8, i12.
  93         Add new unsigned immediate types us3, us4, us5, us16.
  94
  95 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
  96
  97         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
  98         adjust them accordingly.
  99
 100 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 101
 102         * i386.h (i386_optab): Add rdtscp.
 103
 104 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 105
 106         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 107         between memory and segment register. Allow movq for moving between
 108         general-purpose register and segment register.
 109
 110 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 111
 112         PR gas/707
 113         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 114         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 115         fnstsw.
 116
 117 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 118
 119         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 120         * cgen.h (enum cgen_parse_operand_type): Add
 121         CGEN_PARSE_OPERAND_SYMBOLIC.
 122
 123 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 124
 125         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 126         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 127         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 128
 129 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 130
 131         * mips.h (struct mips_opcode): Add new pinfo2 member.
 132         (INSN_ALIAS): New define for opcode table entries that are
 133         specific instances of another entry, such as 'move' for an 'or'
 134         with a zero operand.
 135         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 136         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 137
 138 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 139
 140         * mips.h (CPU_RM9000): Define.
 141         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 142
 143 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 144
 145         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 146         to/from test registers are illegal in 64-bit mode. Add missing
 147         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 148         (previously one had to explicitly encode a rex64 prefix). Re-enable
 149         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 150         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 151
 152 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 153
 154         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 155         available only with SSE2. Change the MMX additions introduced by SSE
 156         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 157         instructions by their now designated identifier (since combining i686
 158         and 3DNow! does not really imply 3DNow!A).
 159
 160 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 161
 162         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 163         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 164
 165 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 166             Vineet Sharma      <vineets@noida.hcltech.com>
 167
 168         * maxq.h: New file: Disassembly information for the maxq port.
 169
 170 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 171
 172         * i386.h (i386_optab): Put back "movzb".
 173
 174 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 175
 176         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 177         comments.  Remove member cris_ver_sim.  Add members
 178         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 179         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 180         (struct cris_support_reg, struct cris_cond15): New types.
 181         (cris_conds15): Declare.
 182         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 183         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 184         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 185         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 186         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 187         SIZE_FIELD_UNSIGNED.
 188
 189 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 190
 191         * i386.h (sldx_Suf): Remove.
 192         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 193         (q_FP): Define, implying no REX64.
 194         (x_FP, sl_FP): Imply FloatMF.
 195         (i386_optab): Split reg and mem forms of moving from segment registers
 196         so that the memory forms can ignore the 16-/32-bit operand size
 197         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 198         all non-floating-point instructions. Unite 32- and 64-bit forms of
 199         movsx, movzx, and movd. Adjust floating point operations for the above
 200         changes to the *FP macros. Add DefaultSize to floating point control
 201         insns operating on larger memory ranges. Remove left over comments
 202         hinting at certain insns being Intel-syntax ones where the ones
 203         actually meant are already gone.
 204
 205 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 206
 207         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 208         instruction type.
 209
 210 2004-09-30  Paul Brook  <paul@codesourcery.com>
 211
 212         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 213         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 214
 215 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 216
 217         * avr.h: Add support for
 218         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 219
 220 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 221
 222         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 223
 224 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 225
 226         * msp430.h (msp430_opc): Add new instructions.
 227         (msp430_rcodes): Declare new instructions.
 228         (msp430_hcodes): Likewise..
 229
 230 2004-08-13  Nick Clifton  <nickc@redhat.com>
 231
 232         PR/301
 233         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 234         processors.
 235
 236 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 237
 238         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 239
 240 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 241
 242         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 243
 244 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 245
 246         * i386.h: Adjust instruction descriptions to better match the
 247         specification.
 248
 249 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 250
 251         * arm.h: Remove all old content.  Replace with architecture defines
 252         from gas/config/tc-arm.c.
 253
 254 2004-07-09  Andreas Schwab  <schwab@suse.de>
 255
 256         * m68k.h: Fix comment.
 257
 258 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 259
 260         * crx.h: New file.
 261
 262 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 263
 264         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 265
 266 2004-05-24  Peter Barada  <peter@the-baradas.com>
 267
 268         * m68k.h: Add 'size' to m68k_opcode.
 269
 270 2004-05-05  Peter Barada  <peter@the-baradas.com>
 271
 272         * m68k.h: Switch from ColdFire chip name to core variant.
 273
 274 2004-04-22  Peter Barada  <peter@the-baradas.com>
 275
 276         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 277         descriptions for new EMAC cases.
 278         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 279         handle Motorola MAC syntax.
 280         Allow disassembly of ColdFire V4e object files.
 281
 282 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 283
 284         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 285
 286 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 287
 288         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 289
 290 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 291
 292         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 293
 294 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 295
 296         * i386.h (i386_optab): Added xstore/xcrypt insns.
 297
 298 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 299
 300         * h8300.h (32bit ldc/stc): Add relaxing support.
 301
 302 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 303
 304         * h8300.h (BITOP): Pass MEMRELAX flag.
 305
 306 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 307
 308         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 309         except for the H8S.
 310
 311 For older changes see ChangeLog-9103
 312 \f
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