include/opcode/ChangeLog

   1 2013-07-24  Anna Tikhonova  <anna.tikhonova@intel.com>
   2             Kirill Yukhin  <kirill.yukhin@intel.com>
   3             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
   4
   5         * i386.h (BND_PREFIX_OPCODE): New.
   6
   7 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
   8
   9         * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
  10         OP_SAVE_RESTORE_LIST.
  11         (decode_mips16_operand): Declare.
  12
  13 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
  14
  15         * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
  16         (mips_operand, mips_int_operand, mips_mapped_int_operand)
  17         (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
  18         (mips_pcrel_operand): New structures.
  19         (mips_insert_operand, mips_extract_operand, mips_signed_operand)
  20         (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
  21         (decode_mips_operand, decode_micromips_operand): Declare.
  22
  23 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
  24
  25         * mips.h: Document MIPS16 "I" opcode.
  26
  27 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  28
  29         * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
  30         (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
  31         (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
  32         (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
  33         (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
  34         (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
  35         (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
  36         (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
  37         (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
  38         (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
  39         (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
  40         (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
  41         (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
  42         Rename to...
  43         (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
  44         (M_USD_AB): ...these.
  45
  46 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  47
  48         * mips.h: Remove documentation of "[" and "]".  Update documentation
  49         of "k" and the MDMX formats.
  50
  51 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  52
  53         * mips.h: Update documentation of "+s" and "+S".
  54
  55 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  56
  57         * mips.h: Document "+i".
  58
  59 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  60
  61         * mips.h: Remove "mi" documentation.  Update "mh" documentation.
  62         (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
  63         Delete.
  64         (INSN2_WRITE_GPR_MHI): Rename to...
  65         (INSN2_WRITE_GPR_MH): ...this.
  66
  67 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  68
  69         * mips.h: Remove documentation of "+D" and "+T".
  70
  71 2013-06-26  Richard Sandiford  <rdsandiford@googlemail.com>
  72
  73         * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
  74         Use "source" rather than "destination" for microMIPS "G".
  75
  76 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
  77
  78         * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
  79         values.
  80
  81 2013-06-23  Richard Sandiford  <rdsandiford@googlemail.com>
  82
  83         * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
  84
  85 2013-06-17  Catherine Moore  <clm@codesourcery.com>
  86             Maciej W. Rozycki  <macro@codesourcery.com>
  87             Chao-Ying Fu  <fu@mips.com>
  88
  89         * mips.h (OP_SH_EVAOFFSET): Define.
  90         (OP_MASK_EVAOFFSET): Define.
  91         (INSN_ASE_MASK): Delete.
  92         (ASE_EVA): Define.
  93         (M_CACHEE_AB, M_CACHEE_OB): New.
  94         (M_LBE_OB, M_LBE_AB): New.
  95         (M_LBUE_OB, M_LBUE_AB): New.
  96         (M_LHE_OB, M_LHE_AB): New.
  97         (M_LHUE_OB, M_LHUE_AB): New.
  98         (M_LLE_AB, M_LLE_OB): New.
  99         (M_LWE_OB, M_LWE_AB): New.
 100         (M_LWLE_AB, M_LWLE_OB): New.
 101         (M_LWRE_AB, M_LWRE_OB): New.
 102         (M_PREFE_AB, M_PREFE_OB): New.
 103         (M_SCE_AB, M_SCE_OB): New.
 104         (M_SBE_OB, M_SBE_AB): New.
 105         (M_SHE_OB, M_SHE_AB): New.
 106         (M_SWE_OB, M_SWE_AB): New.
 107         (M_SWLE_AB, M_SWLE_OB): New.
 108         (M_SWRE_AB, M_SWRE_OB): New.
 109         (MICROMIPSOP_SH_EVAOFFSET): Define.
 110         (MICROMIPSOP_MASK_EVAOFFSET): Define.
 111
 112 2013-06-12  Sandra Loosemore  <sandra@codesourcery.com>
 113
 114         * nios2.h (OP_MATCH_ERET): Correct eret encoding.
 115
 116 2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
 117
 118         * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
 119
 120 2013-05-09  Andrew Pinski  <apinski@cavium.com>
 121
 122         * mips.h (OP_MASK_CODE10): Correct definition.
 123         (OP_SH_CODE10): Likewise.
 124         Add a comment that "+J" is used now for OP_*CODE10.
 125         (INSN_ASE_MASK): Update.
 126         (INSN_VIRT): New macro.
 127         (INSN_VIRT64): New macro
 128
 129 2013-05-02  Nick Clifton  <nickc@redhat.com>
 130
 131         * msp430.h: Add patterns for MSP430X instructions.
 132
 133 2013-04-06  David S. Miller  <davem@davemloft.net>
 134
 135         * sparc.h (F_PREFERRED): Define.
 136         (F_PREF_ALIAS): Define.
 137
 138 2013-04-03  Nick Clifton  <nickc@redhat.com>
 139
 140         * v850.h (V850_INVERSE_PCREL): Define.
 141
 142 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 143
 144         PR binutils/15068
 145         * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
 146
 147 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 148
 149         PR binutils/15068
 150         * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
 151         Add 16-bit opcodes.
 152         * tic6xc-opcode-table.h: Add 16-bit insns.
 153         * tic6x.h: Add support for 16-bit insns.
 154
 155 2013-03-21  Michael Schewe  <michael.schewe@gmx.net>
 156
 157         * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
 158         and mov.b/w/l Rs,@(d:32,ERd).
 159
 160 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 161
 162         PR gas/15082
 163         * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
 164         from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
 165         tic6x_operand_xregpair operand coding type.
 166         Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
 167         opcode field, usu ORXREGD1324 for the src2 operand and remove the
 168         TIC6X_FLAG_NO_CROSS.
 169
 170 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 171
 172         PR gas/15095
 173         * tic6x.h (enum tic6x_coding_method): Add
 174         tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
 175         separately the msb and lsb of a register pair.  This is needed to
 176         encode the opcodes in the same way as TI assembler does.
 177         * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
 178         and rsqrdp opcodes to use the new field coding types.
 179
 180 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 181
 182         * arm.h (CRC_EXT_ARMV8): New constant.
 183         (ARCH_CRC_ARMV8): New macro.
 184
 185 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
 186
 187         * aarch64.h (AARCH64_FEATURE_CRC): New macro.
 188
 189 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
 190             Andrew Jenner <andrew@codesourcery.com>
 191
 192         Based on patches from Altera Corporation.
 193
 194         * nios2.h: New file.
 195
 196 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
 197
 198         * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
 199
 200 2013-01-28  Alexis Deruelle  <alexis.deruelle@gmail.com>
 201
 202         PR gas/15069
 203         * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
 204
 205 2013-01-24  Nick Clifton  <nickc@redhat.com>
 206
 207         * v850.h: Add e3v5 support.
 208
 209 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
 210
 211         * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
 212
 213 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
 214
 215         * ppc.h (PPC_OPCODE_POWER8): New define.
 216         (PPC_OPCODE_HTM): Likewise.
 217
 218 2013-01-10  Will Newton <will.newton@imgtec.com>
 219
 220         * metag.h: New file.
 221
 222 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 223
 224         * cr16.h (make_instruction): Rename to cr16_make_instruction.
 225         (match_opcode): Rename to cr16_match_opcode.
 226
 227 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
 228
 229         * mips.h: Add support for r5900 instructions including lq and sq.
 230
 231 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 232
 233         * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
 234         (make_instruction,match_opcode): Added function prototypes.
 235         (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
 236
 237 2012-11-23  Alan Modra  <amodra@gmail.com>
 238
 239         * ppc.h (ppc_parse_cpu): Update prototype.
 240
 241 2012-10-14  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 242
 243         * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
 244         opcodes.  Likewise, use "cM" instead of "cm" in fstqs opcodes.
 245
 246 2012-10-04  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 247
 248         * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
 249
 250 2012-09-04  Sergey A. Guriev <sergey.a.guriev@intel.com>
 251
 252         * ia64.h (ia64_opnd): Add new operand types.
 253
 254 2012-08-21  David S. Miller  <davem@davemloft.net>
 255
 256         * sparc.h (F3F4): New macro.
 257
 258 2012-08-13  Ian Bolton  <ian.bolton@arm.com>
 259             Laurent Desnogues  <laurent.desnogues@arm.com>
 260             Jim MacArthur  <jim.macarthur@arm.com>
 261             Marcus Shawcroft  <marcus.shawcroft@arm.com>
 262             Nigel Stephens  <nigel.stephens@arm.com>
 263             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 264             Richard Earnshaw  <rearnsha@arm.com>
 265             Sofiane Naci  <sofiane.naci@arm.com>
 266             Tejas Belagod  <tejas.belagod@arm.com>
 267             Yufeng Zhang  <yufeng.zhang@arm.com>
 268
 269         * aarch64.h: New file.
 270
 271 2012-08-13  Richard Sandiford  <rdsandiford@googlemail.com>
 272             Maciej W. Rozycki  <macro@codesourcery.com>
 273
 274         * mips.h (mips_opcode): Add the exclusions field.
 275         (OPCODE_IS_MEMBER): Remove macro.
 276         (cpu_is_member): New inline function.
 277         (opcode_is_member): Likewise.
 278
 279 2012-07-31  Chao-Ying Fu  <fu@mips.com>
 280             Catherine Moore  <clm@codesourcery.com>
 281             Maciej W. Rozycki  <macro@codesourcery.com>
 282
 283         * mips.h: Document microMIPS DSP ASE usage.
 284         (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
 285         microMIPS DSP ASE support.
 286         (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
 287         (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
 288         (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
 289         (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
 290         (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
 291         (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
 292         (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
 293
 294 2012-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 295
 296         * mips.h: Fix a typo in description.
 297
 298 2012-06-07  Georg-Johann Lay  <avr@gjlay.de>
 299
 300         * avr.h: (AVR_ISA_XCH): New define.
 301         (AVR_ISA_XMEGA): Use it.
 302         (XCH, LAS, LAT, LAC): New XMEGA opcodes.
 303
 304 2012-05-15  James Murray <jsm@jsm-net.demon.co.uk>
 305
 306         * m68hc11.h: Add XGate definitions.
 307         (struct m68hc11_opcode): Add xg_mask field.
 308
 309 2012-05-14  Catherine Moore  <clm@codesourcery.com>
 310             Maciej W. Rozycki  <macro@codesourcery.com>
 311             Rhonda Wittels  <rhonda@codesourcery.com>
 312
 313         * ppc.h (PPC_OPCODE_VLE): New definition.
 314         (PPC_OP_SA): New macro.
 315         (PPC_OP_SE_VLE): New macro.
 316         (PPC_OP): Use a variable shift amount.
 317         (powerpc_operand): Update comments.
 318         (PPC_OPSHIFT_INV): New macro.
 319         (PPC_OPERAND_CR): Replace with...
 320         (PPC_OPERAND_CR_BIT): ...this and
 321         (PPC_OPERAND_CR_REG): ...this.
 322
 323
 324 2012-05-03  Sean Keys  <skeys@ipdatasys.com>
 325
 326         * xgate.h: Header file for XGATE assembler.
 327
 328 2012-04-27  David S. Miller  <davem@davemloft.net>
 329
 330         * sparc.h: Document new arg code' )' for crypto RS3
 331         immediates.
 332
 333         * sparc.h (struct sparc_opcode): New field 'hwcaps'.
 334         F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
 335         F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
 336         F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
 337         (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
 338         HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
 339         HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
 340         HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
 341         HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
 342         HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
 343         HWCAP_CBCOND, HWCAP_CRC32): New defines.
 344
 345 2012-03-10  Edmar Wienskoski  <edmar@freescale.com>
 346
 347         * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
 348
 349 2012-02-27  Alan Modra  <amodra@gmail.com>
 350
 351         * crx.h (cst4_map): Update declaration.
 352
 353 2012-02-25  Walter Lee  <walt@tilera.com>
 354
 355         * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
 356         TILEGX_OPC_LD_TLS.
 357         * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
 358         TILEPRO_OPC_LW_TLS_SN.
 359
 360 2012-02-08  H.J. Lu  <hongjiu.lu@intel.com>
 361
 362         * i386.h (XACQUIRE_PREFIX_OPCODE): New.
 363         (XRELEASE_PREFIX_OPCODE): Likewise.
 364
 365 2011-12-08  Andrew Pinski  <apinski@cavium.com>
 366             Adam Nemet  <anemet@caviumnetworks.com>
 367
 368         * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
 369         (INSN_OCTEON2): New macro.
 370         (CPU_OCTEON2): New macro.
 371         (OPCODE_IS_MEMBER): Add Octeon2.
 372
 373 2011-11-29  Andrew Pinski  <apinski@cavium.com>
 374
 375         * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
 376         (INSN_OCTEONP): New macro.
 377         (CPU_OCTEONP): New macro.
 378         (OPCODE_IS_MEMBER): Add Octeon+.
 379         (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
 380
 381 2011-11-01  DJ Delorie  <dj@redhat.com>
 382
 383         * rl78.h: New file.
 384
 385 2011-10-24  Maciej W. Rozycki  <macro@codesourcery.com>
 386
 387         * mips.h: Fix a typo in description.
 388
 389 2011-09-21  David S. Miller  <davem@davemloft.net>
 390
 391         * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
 392         (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
 393         F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
 394         F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
 395
 396 2011-08-09  Chao-ying Fu  <fu@mips.com>
 397             Maciej W. Rozycki  <macro@codesourcery.com>
 398
 399         * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
 400         (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
 401         (INSN_ASE_MASK): Add the MCU bit.
 402         (INSN_MCU): New macro.
 403         (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
 404         (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
 405
 406 2011-08-09  Maciej W. Rozycki  <macro@codesourcery.com>
 407
 408         * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
 409         (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
 410         (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
 411         (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
 412         (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
 413         (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
 414         (INSN2_READ_GPR_MMN): Likewise.
 415         (INSN2_READ_FPR_D): Change the bit used.
 416         (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
 417         (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
 418         (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
 419         (INSN2_COND_BRANCH): Likewise.
 420         (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
 421         (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
 422         (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
 423         (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
 424         (INSN2_MOD_GPR_MN): Likewise.
 425
 426 2011-08-05  David S. Miller  <davem@davemloft.net>
 427
 428         * sparc.h: Document new format codes '4', '5', and '('.
 429         (OPF_LOW4, RS3): New macros.
 430
 431 2011-08-03  Maciej W. Rozycki  <macro@codesourcery.com>
 432
 433         * mips.h: Document the use of FP_D in MIPS16 mode.  Adjust the
 434         order of flags documented.
 435
 436 2011-07-29  Maciej W. Rozycki  <macro@codesourcery.com>
 437
 438         * mips.h: Clarify the description of microMIPS instruction
 439         manipulation macros.
 440         (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
 441
 442 2011-07-24  Chao-ying Fu  <fu@mips.com>
 443             Maciej W. Rozycki  <macro@codesourcery.com>
 444
 445         * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
 446         (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
 447         (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
 448         (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
 449         (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
 450         (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
 451         (OP_MASK_RS3, OP_SH_RS3): Likewise.
 452         (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
 453         (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
 454         (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
 455         (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
 456         (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
 457         (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
 458         (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
 459         (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
 460         (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
 461         (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
 462         (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
 463         (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
 464         (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
 465         (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
 466         (INSN_WRITE_GPR_S): New macro.
 467         (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
 468         (INSN2_READ_FPR_D): Likewise.
 469         (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
 470         (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
 471         (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
 472         (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
 473         (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
 474         (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
 475         (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
 476         (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
 477         (CPU_MICROMIPS): New macro.
 478         (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
 479         (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
 480         (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
 481         (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
 482         (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
 483         (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
 484         (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
 485         (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
 486         (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
 487         (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
 488         (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
 489         (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
 490         (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
 491         (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
 492         (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
 493         (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
 494         (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
 495         (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
 496         (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
 497         (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
 498         (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
 499         (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
 500         (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
 501         (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
 502         (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
 503         (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
 504         (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
 505         (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
 506         (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
 507         (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
 508         (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
 509         (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
 510         (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
 511         (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
 512         (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
 513         (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
 514         (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
 515         (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
 516         (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
 517         (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
 518         (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
 519         (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
 520         (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
 521         (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
 522         (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
 523         (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
 524         (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
 525         (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
 526         (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
 527         (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
 528         (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
 529         (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
 530         (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
 531         (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
 532         (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
 533         (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
 534         (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
 535         (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
 536         (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
 537         (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
 538         (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
 539         (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
 540         (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
 541         (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
 542         (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
 543         (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
 544         (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
 545         (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
 546         (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
 547         (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
 548         (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
 549         (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
 550         (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
 551         (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
 552         (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
 553         (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
 554         (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
 555         (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
 556         (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
 557         (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
 558         (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
 559         (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
 560         (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
 561         (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
 562         (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
 563         (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
 564         (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
 565         (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
 566         (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
 567         (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
 568         (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
 569         (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
 570         (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
 571         (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
 572         (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
 573         (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
 574         (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
 575         (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
 576         (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
 577         (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
 578         (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
 579         (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
 580         (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
 581         (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
 582         (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
 583         (micromips_opcodes): New declaration.
 584         (bfd_micromips_num_opcodes): Likewise.
 585
 586 2011-07-24  Maciej W. Rozycki  <macro@codesourcery.com>
 587
 588         * mips.h (INSN_TRAP): Rename to...
 589         (INSN_NO_DELAY_SLOT): ... this.
 590         (INSN_SYNC): Remove macro.
 591
 592 2011-07-01  Eric B. Weddington  <eric.weddington@atmel.com>
 593
 594         * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
 595         a duplicate of AVR_ISA_SPM.
 596
 597 2011-07-01  Nick Clifton  <nickc@redhat.com>
 598
 599         * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
 600
 601 2011-06-18  Robin Getz  <robin.getz@analog.com>
 602
 603         * bfin.h (is_macmod_signed): New func
 604
 605 2011-06-18  Mike Frysinger  <vapier@gentoo.org>
 606
 607         * bfin.h (is_macmod_pmove): Add missing space before func args.
 608         (is_macmod_hmove): Likewise.
 609
 610 2011-06-13  Walter Lee  <walt@tilera.com>
 611
 612         * tilegx.h: New file.
 613         * tilepro.h: New file.
 614
 615 2011-05-31  Paul Brook  <paul@codesourcery.com>
 616
 617         * arm.h (ARM_ARCH_V7R_IDIV): Define.
 618
 619 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 620
 621         * s390.h: Replace S390_OPERAND_REG_EVEN with
 622         S390_OPERAND_REG_PAIR.
 623
 624 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 625
 626         * s390.h: Add S390_OPCODE_REG_EVEN flag.
 627
 628 2011-04-18  Julian Brown  <julian@codesourcery.com>
 629
 630         * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
 631
 632 2011-04-11  Dan McDonald  <dan@wellkeeper.com>
 633
 634         PR gas/12296
 635         * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
 636
 637 2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>
 638
 639         * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
 640         New instruction set flags.
 641         (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
 642
 643 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 644
 645         * mips.h (M_PREF_AB): New enum value.
 646
 647 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 648
 649         * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
 650         M_IU): Define.
 651         (is_macmod_pmove, is_macmod_hmove): New functions.
 652
 653 2011-02-11  Mike Frysinger  <vapier@gentoo.org>
 654
 655         * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
 656
 657 2011-02-04  Bernd Schmidt  <bernds@codesourcery.com>
 658
 659         * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
 660         * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
 661
 662 2010-12-31  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 663
 664         PR gas/11395
 665         * hppa.h (pa_opcodes): Revert last change.  Exchange 32 and 64-bit
 666         "bb" entries.
 667
 668 2010-12-26  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 669
 670         PR gas/11395
 671         * hppa.h: Clear "d" bit in "add" and "sub" patterns.
 672
 673 2010-12-18  Richard Sandiford  <rdsandiford@googlemail.com>
 674
 675         * mips.h: Update commentary after last commit.
 676
 677 2010-12-18  Mingjie Xing  <mingjie.xing@gmail.com>
 678
 679         * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
 680         (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
 681         (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
 682
 683 2010-11-25  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 684
 685         * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
 686
 687 2010-11-23  Richard Sandiford  <rdsandiford@googlemail.com>
 688
 689         * mips.h: Fix previous commit.
 690
 691 2010-11-23  Maciej W. Rozycki  <macro@linux-mips.org>
 692
 693         * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
 694         (INSN_LOONGSON_3A): Clear bit 31.
 695
 696 2010-11-15  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 697
 698         PR gas/12198
 699         * arm.h (ARM_AEXT_V6M_ONLY): New define.
 700         (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
 701         (ARM_ARCH_V6M_ONLY): New define.
 702
 703 2010-11-11  Mingming Sun  <mingm.sun@gmail.com>
 704
 705         * mips.h (INSN_LOONGSON_3A): Defined.
 706         (CPU_LOONGSON_3A): Defined.
 707         (OPCODE_IS_MEMBER): Add LOONGSON_3A.
 708
 709 2010-10-09  Matt Rice  <ratmice@gmail.com>
 710
 711         * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
 712         (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
 713
 714 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 715
 716         * arm.h (ARM_EXT_VIRT): New define.
 717         (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
 718         (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
 719         Extensions.
 720
 721 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 722
 723         * arm.h (ARM_AEXT_ADIV): New define.
 724         (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
 725
 726 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 727
 728         * arm.h (ARM_EXT_OS): New define.
 729         (ARM_AEXT_V6SM): Likewise.
 730         (ARM_ARCH_V6SM): Likewise.
 731
 732 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 733
 734         * arm.h (ARM_EXT_MP): Add.
 735         (ARM_ARCH_V7A_MP): Likewise.
 736
 737 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 738
 739         * bfin.h: Declare pseudoChr structs/defines.
 740
 741 2010-09-21  Mike Frysinger  <vapier@gentoo.org>
 742
 743         * bfin.h: Strip trailing whitespace.
 744
 745 2010-07-29  DJ Delorie  <dj@redhat.com>
 746
 747         * rx.h (RX_Operand_Type): Add TwoReg.
 748         (RX_Opcode_ID): Remove ediv and ediv2.
 749
 750 2010-07-27  DJ Delorie  <dj@redhat.com>
 751
 752         * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
 753
 754 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
 755             Ina Pandit  <ina.pandit@kpitcummins.com>
 756
 757         * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
 758         PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
 759         PROCESSOR_V850E2_ALL.
 760         Remove PROCESSOR_V850EA support.
 761         (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
 762         V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
 763         V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
 764         V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
 765         V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
 766         V850_OPERAND_PERCENT.
 767         Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
 768         V850_NOT_R0.
 769         Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
 770         and V850E_PUSH_POP
 771
 772 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 773
 774         * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
 775         (MIPS16_INSN_BRANCH): Rename to...
 776         (MIPS16_INSN_COND_BRANCH): ... this.
 777
 778 2010-07-03  Alan Modra  <amodra@gmail.com>
 779
 780         * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
 781         Renumber other PPC_OPCODE defines.
 782
 783 2010-07-03  Alan Modra  <amodra@gmail.com>
 784
 785         * ppc.h (PPC_OPCODE_COMMON): Expand comment.
 786
 787 2010-06-29  Alan Modra  <amodra@gmail.com>
 788
 789         * maxq.h: Delete file.
 790
 791 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 792
 793         * ppc.h (PPC_OPCODE_E500): Define.
 794
 795 2010-05-26  Catherine Moore  <clm@codesourcery.com>
 796
 797         * opcode/mips.h (INSN_MIPS16): Remove.
 798
 799 2010-04-21  Joseph Myers  <joseph@codesourcery.com>
 800
 801         * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
 802
 803 2010-04-15  Nick Clifton  <nickc@redhat.com>
 804
 805         * alpha.h: Update copyright notice to use GPLv3.
 806         * arc.h: Likewise.
 807         * arm.h: Likewise.
 808         * avr.h: Likewise.
 809         * bfin.h: Likewise.
 810         * cgen.h: Likewise.
 811         * convex.h: Likewise.
 812         * cr16.h: Likewise.
 813         * cris.h: Likewise.
 814         * crx.h: Likewise.
 815         * d10v.h: Likewise.
 816         * d30v.h: Likewise.
 817         * dlx.h: Likewise.
 818         * h8300.h: Likewise.
 819         * hppa.h: Likewise.
 820         * i370.h: Likewise.
 821         * i386.h: Likewise.
 822         * i860.h: Likewise.
 823         * i960.h: Likewise.
 824         * ia64.h: Likewise.
 825         * m68hc11.h: Likewise.
 826         * m68k.h: Likewise.
 827         * m88k.h: Likewise.
 828         * maxq.h: Likewise.
 829         * mips.h: Likewise.
 830         * mmix.h: Likewise.
 831         * mn10200.h: Likewise.
 832         * mn10300.h: Likewise.
 833         * msp430.h: Likewise.
 834         * np1.h: Likewise.
 835         * ns32k.h: Likewise.
 836         * or32.h: Likewise.
 837         * pdp11.h: Likewise.
 838         * pj.h: Likewise.
 839         * pn.h: Likewise.
 840         * ppc.h: Likewise.
 841         * pyr.h: Likewise.
 842         * rx.h: Likewise.
 843         * s390.h: Likewise.
 844         * score-datadep.h: Likewise.
 845         * score-inst.h: Likewise.
 846         * sparc.h: Likewise.
 847         * spu-insns.h: Likewise.
 848         * spu.h: Likewise.
 849         * tic30.h: Likewise.
 850         * tic4x.h: Likewise.
 851         * tic54x.h: Likewise.
 852         * tic80.h: Likewise.
 853         * v850.h: Likewise.
 854         * vax.h: Likewise.
 855
 856 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
 857
 858         * tic6x-control-registers.h, tic6x-insn-formats.h,
 859         tic6x-opcode-table.h, tic6x.h: New.
 860
 861 2010-02-25  Wu Zhangjin  <wuzhangjin@gmail.com>
 862
 863         * mips.h: (LOONGSON2F_NOP_INSN): New macro.
 864
 865 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
 866
 867         * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
 868
 869 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 870
 871         * ia64.h (ia64_find_opcode): Remove argument name.
 872         (ia64_find_next_opcode): Likewise.
 873         (ia64_dis_opcode): Likewise.
 874         (ia64_free_opcode): Likewise.
 875         (ia64_find_dependency): Likewise.
 876
 877 2009-11-22  Doug Evans  <dje@sebabeach.org>
 878
 879         * cgen.h: Include bfd_stdint.h.
 880         (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
 881
 882 2009-11-18  Paul Brook  <paul@codesourcery.com>
 883
 884         * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
 885
 886 2009-11-17  Paul Brook  <paul@codesourcery.com>
 887         Daniel Jacobowitz  <dan@codesourcery.com>
 888
 889         * arm.h (ARM_EXT_V6_DSP): Define.
 890         (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
 891         (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
 892
 893 2009-11-04  DJ Delorie  <dj@redhat.com>
 894
 895         * rx.h (rx_decode_opcode) (mvtipl): Add.
 896         (mvtcp, mvfcp, opecp): Remove.
 897
 898 2009-11-02  Paul Brook  <paul@codesourcery.com>
 899
 900         * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
 901         FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
 902         (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
 903         FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
 904         FPU_ARCH_NEON_VFP_V4): Define.
 905
 906 2009-10-23  Doug Evans  <dje@sebabeach.org>
 907
 908         * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
 909         * cgen.h: Update.  Improve multi-inclusion macro name.
 910
 911 2009-10-02  Peter Bergner  <bergner@vnet.ibm.com>
 912
 913         * ppc.h (PPC_OPCODE_476): Define.
 914
 915 2009-10-01  Peter Bergner  <bergner@vnet.ibm.com>
 916
 917         * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
 918
 919 2009-09-29  DJ Delorie  <dj@redhat.com>
 920
 921         * rx.h: New file.
 922
 923 2009-09-22  Peter Bergner  <bergner@vnet.ibm.com>
 924
 925         * ppc.h (ppc_cpu_t): Typedef to uint64_t.
 926
 927 2009-09-21  Ben Elliston  <bje@au.ibm.com>
 928
 929         * ppc.h (PPC_OPCODE_PPCA2): New.
 930
 931 2009-09-05  Martin Thuresson  <martin@mtme.org>
 932
 933         * ia64.h (struct ia64_operand): Renamed member class to op_class.
 934
 935 2009-08-29  Martin Thuresson  <martin@mtme.org>
 936
 937         * tic30.h (template): Rename type template to
 938         insn_template. Updated code to use new name.
 939         * tic54x.h (template): Rename type template to
 940         insn_template.
 941
 942 2009-08-20  Nick Hudson  <nick.hudson@gmx.co.uk>
 943
 944         * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
 945
 946 2009-06-11  Anthony Green  <green@moxielogic.com>
 947
 948         * moxie.h (MOXIE_F3_PCREL): Define.
 949         (moxie_form3_opc_info): Grow.
 950
 951 2009-06-06  Anthony Green  <green@moxielogic.com>
 952
 953         * moxie.h (MOXIE_F1_M): Define.
 954
 955 2009-04-15  Anthony Green  <green@moxielogic.com>
 956
 957         * moxie.h: Created.
 958
 959 2009-04-06  DJ Delorie  <dj@redhat.com>
 960
 961         * h8300.h: Add relaxation attributes to MOVA opcodes.
 962
 963 2009-03-10  Alan Modra  <amodra@bigpond.net.au>
 964
 965         * ppc.h (ppc_parse_cpu): Declare.
 966
 967 2009-03-02  Qinwei  <qinwei@sunnorth.com.cn>
 968
 969         * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
 970         and _IMM11 for mbitclr and mbitset.
 971         * score-datadep.h: Update dependency information.
 972
 973 2009-02-26  Peter Bergner  <bergner@vnet.ibm.com>
 974
 975         * ppc.h (PPC_OPCODE_POWER7): New.
 976
 977 2009-02-06  Doug Evans  <dje@google.com>
 978
 979         * i386.h: Add comment regarding sse* insns and prefixes.
 980
 981 2009-02-03  Sandip Matte  <sandip@rmicorp.com>
 982
 983         * mips.h (INSN_XLR): Define.
 984         (INSN_CHIP_MASK): Update.
 985         (CPU_XLR): Define.
 986         (OPCODE_IS_MEMBER): Update.
 987         (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
 988
 989 2009-01-28  Doug Evans  <dje@google.com>
 990
 991         * opcode/i386.h: Add multiple inclusion protection.
 992         (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
 993         (EDI_REG_NUM): New macros.
 994         (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
 995         (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
 996         (REX_PREFIX_P): New macro.
 997
 998 2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
 999
1000         * ppc.h (struct powerpc_opcode): New field "deprecated".
1001         (PPC_OPCODE_NOPOWER4): Delete.
1002
1003 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
1004
1005         * mips.h: Define CPU_R14000, CPU_R16000.
1006         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1007
1008 2008-11-18  Catherine Moore  <clm@codesourcery.com>
1009
1010         * arm.h (FPU_NEON_FP16): New.
1011         (FPU_ARCH_NEON_FP16): New.
1012
1013 2008-11-06  Chao-ying Fu  <fu@mips.com>
1014
1015         * mips.h: Doucument '1' for 5-bit sync type.
1016
1017 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
1018
1019         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
1020         IA64_RS_CR.
1021
1022 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
1023
1024         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1025
1026 2008-07-30  Michael J. Eager  <eager@eagercon.com>
1027
1028         * ppc.h (PPC_OPCODE_405): Define.
1029         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1030
1031 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
1032
1033         * ppc.h (ppc_cpu_t): New typedef.
1034         (struct powerpc_opcode <flags>): Use it.
1035         (struct powerpc_operand <insert, extract>): Likewise.
1036         (struct powerpc_macro <flags>): Likewise.
1037
1038 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
1039
1040         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1041         Update comment before MIPS16 field descriptors to mention MIPS16.
1042         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1043         BBIT.
1044         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1045         New bit masks and shift counts for cins and exts.
1046
1047         * mips.h: Document new field descriptors +Q.
1048         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1049
1050 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
1051
1052         * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
1053         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1054
1055 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
1056
1057         * ppc.h: (PPC_OPCODE_E500MC): New.
1058
1059 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
1060
1061         * i386.h (MAX_OPERANDS): Set to 5.
1062         (MAX_MNEM_SIZE): Changed to 20.
1063
1064 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
1065
1066         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1067
1068 2008-03-09  Paul Brook  <paul@codesourcery.com>
1069
1070         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1071
1072 2008-03-04  Paul Brook  <paul@codesourcery.com>
1073
1074         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1075         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1076         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1077
1078 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
1079             Nick Clifton  <nickc@redhat.com>
1080
1081         PR 3134
1082         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1083         with a 32-bit displacement but without the top bit of the 4th byte
1084         set.
1085
1086 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1087
1088         * cr16.h (cr16_num_optab): Declared.
1089
1090 2008-02-14  Hakan Ardo  <hakan@debian.org>
1091
1092         PR gas/2626
1093         * avr.h (AVR_ISA_2xxe): Define.
1094
1095 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
1096
1097         * mips.h: Update copyright.
1098         (INSN_CHIP_MASK): New macro.
1099         (INSN_OCTEON): New macro.
1100         (CPU_OCTEON): New macro.
1101         (OPCODE_IS_MEMBER): Handle Octeon instructions.
1102
1103 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
1104
1105         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1106
1107 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
1108
1109         * avr.h (AVR_ISA_USB162): Add new opcode set.
1110         (AVR_ISA_AVR3): Likewise.
1111
1112 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
1113
1114         * mips.h (INSN_LOONGSON_2E): New.
1115         (INSN_LOONGSON_2F): New.
1116         (CPU_LOONGSON_2E): New.
1117         (CPU_LOONGSON_2F): New.
1118         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1119
1120 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
1121
1122         * mips.h (INSN_ISA*): Redefine certain values as an
1123         enumeration.  Update comments.
1124         (mips_isa_table): New.
1125         (ISA_MIPS*): Redefine to match enumeration.
1126         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1127         values.
1128
1129 2007-08-08  Ben Elliston  <bje@au.ibm.com>
1130
1131         * ppc.h (PPC_OPCODE_PPCPS): New.
1132
1133 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
1134
1135         * m68k.h: Document j K & E.
1136
1137 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
1138
1139         * cr16.h: New file for CR16 target.
1140
1141 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
1142
1143         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1144
1145 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
1146
1147         * m68k.h (mcfisa_c): New.
1148         (mcfusp, mcf_mask): Adjust.
1149
1150 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
1151
1152         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1153         (num_powerpc_operands): Declare.
1154         (PPC_OPERAND_SIGNED et al): Redefine as hex.
1155         (PPC_OPERAND_PLUS1): Define.
1156
1157 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
1158
1159         * i386.h (REX_MODE64): Renamed to ...
1160         (REX_W): This.
1161         (REX_EXTX): Renamed to ...
1162         (REX_R): This.
1163         (REX_EXTY): Renamed to ...
1164         (REX_X): This.
1165         (REX_EXTZ): Renamed to ...
1166         (REX_B): This.
1167
1168 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
1169
1170         * i386.h: Add entries from config/tc-i386.h and move tables
1171         to opcodes/i386-opc.h.
1172
1173 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
1174
1175         * i386.h (FloatDR): Removed.
1176         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1177
1178 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
1179
1180         * spu-insns.h: Add soma double-float insns.
1181
1182 2007-02-20  Thiemo Seufer  <ths@mips.com>
1183             Chao-Ying Fu  <fu@mips.com>
1184
1185         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1186         (INSN_DSPR2): Add flag for DSP R2 instructions.
1187         (M_BALIGN): New macro.
1188
1189 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
1190
1191         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1192         and Seg3ShortFrom with Shortform.
1193
1194 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
1195
1196         PR gas/4027
1197         * i386.h (i386_optab): Put the real "test" before the pseudo
1198         one.
1199
1200 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
1201
1202         * m68k.h (m68010up): OR fido_a.
1203
1204 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
1205
1206         * m68k.h (fido_a): New.
1207
1208 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
1209
1210         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1211         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1212         values.
1213
1214 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
1215
1216         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1217
1218 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
1219
1220         * score-inst.h (enum score_insn_type): Add Insn_internal.
1221
1222 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
1223             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
1224             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
1225             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
1226             Alan Modra  <amodra@bigpond.net.au>
1227
1228         * spu-insns.h: New file.
1229         * spu.h: New file.
1230
1231 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
1232
1233         * ppc.h (PPC_OPCODE_CELL): Define.
1234
1235 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
1236
1237         * i386.h :  Modify opcode to support for the change in POPCNT opcode
1238         in amdfam10 architecture.
1239
1240 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
1241
1242         * i386.h: Replace CpuMNI with CpuSSSE3.
1243
1244 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
1245             Joseph Myers  <joseph@codesourcery.com>
1246             Ian Lance Taylor  <ian@wasabisystems.com>
1247             Ben Elliston  <bje@wasabisystems.com>
1248
1249         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1250
1251 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
1252
1253         * score-datadep.h: New file.
1254         * score-inst.h: New file.
1255
1256 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
1257
1258         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1259         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1260         movdq2q and movq2dq.
1261
1262 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
1263            Michael Meissner             <michael.meissner@amd.com>
1264
1265         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1266
1267 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
1268
1269         * i386.h (i386_optab): Add "nop" with memory reference.
1270
1271 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
1272
1273         * i386.h (i386_optab): Update comment for 64bit NOP.
1274
1275 2006-06-06  Ben Elliston  <bje@au.ibm.com>
1276             Anton Blanchard  <anton@samba.org>
1277
1278         * ppc.h (PPC_OPCODE_POWER6): Define.
1279         Adjust whitespace.
1280
1281 2006-06-05  Thiemo Seufer  <ths@mips.com>
1282
1283         * mips.h: Improve description of MT flags.
1284
1285 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
1286
1287         * m68k.h (mcf_mask): Define.
1288
1289 2006-05-05  Thiemo Seufer  <ths@mips.com>
1290             David Ung  <davidu@mips.com>
1291
1292         * mips.h (enum): Add macro M_CACHE_AB.
1293
1294 2006-05-04  Thiemo Seufer  <ths@mips.com>
1295             Nigel Stephens  <nigel@mips.com>
1296             David Ung  <davidu@mips.com>
1297
1298         * mips.h: Add INSN_SMARTMIPS define.
1299
1300 2006-04-30  Thiemo Seufer  <ths@mips.com>
1301             David Ung  <davidu@mips.com>
1302
1303         * mips.h: Defines udi bits and masks.  Add description of
1304         characters which may appear in the args field of udi
1305         instructions.
1306
1307 2006-04-26  Thiemo Seufer  <ths@networkno.de>
1308
1309         * mips.h: Improve comments describing the bitfield instruction
1310         fields.
1311
1312 2006-04-26  Julian Brown  <julian@codesourcery.com>
1313
1314         * arm.h (FPU_VFP_EXT_V3): Define constant.
1315         (FPU_NEON_EXT_V1): Likewise.
1316         (FPU_VFP_HARD): Update.
1317         (FPU_VFP_V3): Define macro.
1318         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1319
1320 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
1321
1322         * avr.h (AVR_ISA_PWMx): New.
1323
1324 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
1325
1326         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1327         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1328         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1329         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1330         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1331
1332 2006-03-10  Paul Brook  <paul@codesourcery.com>
1333
1334         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1335
1336 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1337
1338         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1339         first.  Correct mask of bb "B" opcode.
1340
1341 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
1342
1343         * i386.h (i386_optab): Support Intel Merom New Instructions.
1344
1345 2006-02-24  Paul Brook  <paul@codesourcery.com>
1346
1347         * arm.h: Add V7 feature bits.
1348
1349 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
1350
1351         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1352
1353 2006-01-31  Paul Brook  <paul@codesourcery.com>
1354         Richard Earnshaw <rearnsha@arm.com>
1355
1356         * arm.h: Use ARM_CPU_FEATURE.
1357         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1358         (arm_feature_set): Change to a structure.
1359         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1360         ARM_FEATURE): New macros.
1361
1362 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
1363
1364         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1365         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1366         (ADD_PC_INCR_OPCODE): Don't define.
1367
1368 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
1369
1370         PR gas/1874
1371         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1372
1373 2005-11-14  David Ung  <davidu@mips.com>
1374
1375         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1376         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1377         save/restore encoding of the args field.
1378
1379 2005-10-28  Dave Brolley  <brolley@redhat.com>
1380
1381         Contribute the following changes:
1382         2005-02-16  Dave Brolley  <brolley@redhat.com>
1383
1384         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1385         cgen_isa_mask_* to cgen_bitset_*.
1386         * cgen.h: Likewise.
1387
1388         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
1389
1390         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1391         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1392         (CGEN_CPU_TABLE): Make isas a ponter.
1393
1394         2003-09-29  Dave Brolley  <brolley@redhat.com>
1395
1396         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1397         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1398         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1399
1400         2002-12-13  Dave Brolley  <brolley@redhat.com>
1401
1402         * cgen.h (symcat.h): #include it.
1403         (cgen-bitset.h): #include it.
1404         (CGEN_ATTR_VALUE_TYPE): Now a union.
1405         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1406         (CGEN_ATTR_ENTRY): 'value' now unsigned.
1407         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1408         * cgen-bitset.h: New file.
1409
1410 2005-09-30  Catherine Moore  <clm@cm00re.com>
1411
1412         * bfin.h: New file.
1413
1414 2005-10-24  Jan Beulich  <jbeulich@novell.com>
1415
1416         * ia64.h (enum ia64_opnd): Move memory operand out of set of
1417         indirect operands.
1418
1419 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1420
1421         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
1422         Add FLAG_STRICT to pa10 ftest opcode.
1423
1424 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1425
1426         * hppa.h (pa_opcodes): Remove lha entries.
1427
1428 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1429
1430         * hppa.h (FLAG_STRICT): Revise comment.
1431         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
1432         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
1433         entries for "fdc".
1434
1435 2005-09-30  Catherine Moore  <clm@cm00re.com>
1436
1437         * bfin.h: New file.
1438
1439 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1440
1441         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1442
1443 2005-09-06  Chao-ying Fu  <fu@mips.com>
1444
1445         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1446         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1447         define.
1448         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1449         (INSN_ASE_MASK): Update to include INSN_MT.
1450         (INSN_MT): New define for MT ASE.
1451
1452 2005-08-25  Chao-ying Fu  <fu@mips.com>
1453
1454         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1455         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1456         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1457         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1458         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1459         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1460         instructions.
1461         (INSN_DSP): New define for DSP ASE.
1462
1463 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
1464
1465         * a29k.h: Delete.
1466
1467 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
1468
1469         * ppc.h (PPC_OPCODE_E300): Define.
1470
1471 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
1472
1473         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1474
1475 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1476
1477         PR gas/336
1478         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1479         and pitlb.
1480
1481 2005-07-27  Jan Beulich  <jbeulich@novell.com>
1482
1483         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1484         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1485         Add movq-s as 64-bit variants of movd-s.
1486
1487 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1488
1489         * hppa.h: Fix punctuation in comment.
1490
1491         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
1492         implicit space-register addressing.  Set space-register bits on opcodes
1493         using implicit space-register addressing.  Add various missing pa20
1494         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
1495         space-register addressing.  Use "fE" instead of "fe" in various
1496         fstw opcodes.
1497
1498 2005-07-18  Jan Beulich  <jbeulich@novell.com>
1499
1500         * i386.h (i386_optab): Operands of aam and aad are unsigned.
1501
1502 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
1503
1504         * i386.h (i386_optab): Support Intel VMX Instructions.
1505
1506 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1507
1508         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1509
1510 2005-07-05  Jan Beulich  <jbeulich@novell.com>
1511
1512         * i386.h (i386_optab): Add new insns.
1513
1514 2005-07-01  Nick Clifton  <nickc@redhat.com>
1515
1516         * sparc.h: Add typedefs to structure declarations.
1517
1518 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
1519
1520         PR 1013
1521         * i386.h (i386_optab): Update comments for 64bit addressing on
1522         mov. Allow 64bit addressing for mov and movq.
1523
1524 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1525
1526         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1527         respectively, in various floating-point load and store patterns.
1528
1529 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1530
1531         * hppa.h (FLAG_STRICT): Correct comment.
1532         (pa_opcodes): Update load and store entries to allow both PA 1.X and
1533         PA 2.0 mneumonics when equivalent.  Entries with cache control
1534         completers now require PA 1.1.  Adjust whitespace.
1535
1536 2005-05-19  Anton Blanchard  <anton@samba.org>
1537
1538         * ppc.h (PPC_OPCODE_POWER5): Define.
1539
1540 2005-05-10  Nick Clifton  <nickc@redhat.com>
1541
1542         * Update the address and phone number of the FSF organization in
1543         the GPL notices in the following files:
1544         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1545         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1546         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1547         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1548         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1549         tic54x.h, tic80.h, v850.h, vax.h
1550
1551 2005-05-09  Jan Beulich  <jbeulich@novell.com>
1552
1553         * i386.h (i386_optab): Add ht and hnt.
1554
1555 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
1556
1557         * i386.h: Insert hyphens into selected VIA PadLock extensions.
1558         Add xcrypt-ctr.  Provide aliases without hyphens.
1559
1560 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
1561
1562         Moved from ../ChangeLog
1563
1564         2005-04-12  Paul Brook  <paul@codesourcery.com>
1565         * m88k.h: Rename psr macros to avoid conflicts.
1566
1567         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
1568         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1569         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1570         and ARM_ARCH_V6ZKT2.
1571
1572         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
1573         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1574         Remove redundant instruction types.
1575         (struct argument): X_op - new field.
1576         (struct cst4_entry): Remove.
1577         (no_op_insn): Declare.
1578
1579         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
1580         * crx.h (enum argtype): Rename types, remove unused types.
1581
1582         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
1583         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1584         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1585         (enum operand_type): Rearrange operands, edit comments.
1586         replace us<N> with ui<N> for unsigned immediate.
1587         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1588         displacements (respectively).
1589         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1590         (instruction type): Add NO_TYPE_INS.
1591         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1592         (operand_entry): New field - 'flags'.
1593         (operand flags): New.
1594
1595         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
1596         * crx.h (operand_type): Remove redundant types i3, i4,
1597         i5, i8, i12.
1598         Add new unsigned immediate types us3, us4, us5, us16.
1599
1600 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
1601
1602         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1603         adjust them accordingly.
1604
1605 2005-04-01  Jan Beulich  <jbeulich@novell.com>
1606
1607         * i386.h (i386_optab): Add rdtscp.
1608
1609 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
1610
1611         * i386.h (i386_optab): Don't allow the `l' suffix for moving
1612         between memory and segment register. Allow movq for moving between
1613         general-purpose register and segment register.
1614
1615 2005-02-09  Jan Beulich  <jbeulich@novell.com>
1616
1617         PR gas/707
1618         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1619         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1620         fnstsw.
1621
1622 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
1623
1624         * m68k.h (m68008, m68ec030, m68882): Remove.
1625         (m68k_mask): New.
1626         (cpu_m68k, cpu_cf): New.
1627         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1628         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1629
1630 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
1631
1632         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
1633         * cgen.h (enum cgen_parse_operand_type): Add
1634         CGEN_PARSE_OPERAND_SYMBOLIC.
1635
1636 2005-01-21  Fred Fish  <fnf@specifixinc.com>
1637
1638         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1639         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1640         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1641
1642 2005-01-19  Fred Fish  <fnf@specifixinc.com>
1643
1644         * mips.h (struct mips_opcode): Add new pinfo2 member.
1645         (INSN_ALIAS): New define for opcode table entries that are
1646         specific instances of another entry, such as 'move' for an 'or'
1647         with a zero operand.
1648         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1649         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1650
1651 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
1652
1653         * mips.h (CPU_RM9000): Define.
1654         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1655
1656 2004-11-25 Jan Beulich  <jbeulich@novell.com>
1657
1658         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1659         to/from test registers are illegal in 64-bit mode. Add missing
1660         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1661         (previously one had to explicitly encode a rex64 prefix). Re-enable
1662         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1663         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1664
1665 2004-11-23 Jan Beulich  <jbeulich@novell.com>
1666
1667         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1668         available only with SSE2. Change the MMX additions introduced by SSE
1669         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1670         instructions by their now designated identifier (since combining i686
1671         and 3DNow! does not really imply 3DNow!A).
1672
1673 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
1674
1675         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1676         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1677
1678 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
1679             Vineet Sharma      <vineets@noida.hcltech.com>
1680
1681         * maxq.h: New file: Disassembly information for the maxq port.
1682
1683 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
1684
1685         * i386.h (i386_optab): Put back "movzb".
1686
1687 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
1688
1689         * cris.h (enum cris_insn_version_usage): Tweak formatting and
1690         comments.  Remove member cris_ver_sim.  Add members
1691         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1692         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1693         (struct cris_support_reg, struct cris_cond15): New types.
1694         (cris_conds15): Declare.
1695         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1696         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1697         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1698         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1699         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1700         SIZE_FIELD_UNSIGNED.
1701
1702 2004-11-04 Jan Beulich  <jbeulich@novell.com>
1703
1704         * i386.h (sldx_Suf): Remove.
1705         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1706         (q_FP): Define, implying no REX64.
1707         (x_FP, sl_FP): Imply FloatMF.
1708         (i386_optab): Split reg and mem forms of moving from segment registers
1709         so that the memory forms can ignore the 16-/32-bit operand size
1710         distinction. Adjust a few others for Intel mode. Remove *FP uses from
1711         all non-floating-point instructions. Unite 32- and 64-bit forms of
1712         movsx, movzx, and movd. Adjust floating point operations for the above
1713         changes to the *FP macros. Add DefaultSize to floating point control
1714         insns operating on larger memory ranges. Remove left over comments
1715         hinting at certain insns being Intel-syntax ones where the ones
1716         actually meant are already gone.
1717
1718 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
1719
1720         * crx.h: Add COPS_REG_INS - Coprocessor Special register
1721         instruction type.
1722
1723 2004-09-30  Paul Brook  <paul@codesourcery.com>
1724
1725         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1726         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1727
1728 2004-09-11  Theodore A. Roth  <troth@openavr.org>
1729
1730         * avr.h: Add support for
1731         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1732
1733 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
1734
1735         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1736
1737 2004-08-24  Dmitry Diky  <diwil@spec.ru>
1738
1739         * msp430.h (msp430_opc): Add new instructions.
1740         (msp430_rcodes): Declare new instructions.
1741         (msp430_hcodes): Likewise..
1742
1743 2004-08-13  Nick Clifton  <nickc@redhat.com>
1744
1745         PR/301
1746         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1747         processors.
1748
1749 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
1750
1751         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1752
1753 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
1754
1755         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1756
1757 2004-07-21  Jan Beulich  <jbeulich@novell.com>
1758
1759         * i386.h: Adjust instruction descriptions to better match the
1760         specification.
1761
1762 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
1763
1764         * arm.h: Remove all old content.  Replace with architecture defines
1765         from gas/config/tc-arm.c.
1766
1767 2004-07-09  Andreas Schwab  <schwab@suse.de>
1768
1769         * m68k.h: Fix comment.
1770
1771 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
1772
1773         * crx.h: New file.
1774
1775 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
1776
1777         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1778
1779 2004-05-24  Peter Barada  <peter@the-baradas.com>
1780
1781         * m68k.h: Add 'size' to m68k_opcode.
1782
1783 2004-05-05  Peter Barada  <peter@the-baradas.com>
1784
1785         * m68k.h: Switch from ColdFire chip name to core variant.
1786
1787 2004-04-22  Peter Barada  <peter@the-baradas.com>
1788
1789         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
1790         descriptions for new EMAC cases.
1791         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1792         handle Motorola MAC syntax.
1793         Allow disassembly of ColdFire V4e object files.
1794
1795 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
1796
1797         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
1798
1799 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
1800
1801         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1802
1803 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1804
1805         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1806
1807 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1808
1809         * i386.h (i386_optab): Added xstore/xcrypt insns.
1810
1811 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1812
1813         * h8300.h (32bit ldc/stc): Add relaxing support.
1814
1815 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
1816
1817         * h8300.h (BITOP): Pass MEMRELAX flag.
1818
1819 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1820
1821         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1822         except for the H8S.
1823
1824 For older changes see ChangeLog-9103
1825 \f
1826 Copyright (C) 2004-2012 Free Software Foundation, Inc.
1827
1828 Copying and distribution of this file, with or without modification,
1829 are permitted in any medium without royalty provided the copyright
1830 notice and this notice are preserved.
1831
1832 Local Variables:
1833 mode: change-log
1834 left-margin: 8
1835 fill-column: 74
1836 version-control: never
1837 End: