include/opcode/ChangeLog

   1 2013-11-20  Yufeng Zhang  <yufeng.zhang@arm.com>
   2
   3         * aarch64.h (aarch64_pstatefields): Change element type to
   4         aarch64_sys_reg.
   5
   6 2013-11-18  Renlin Li  <Renlin.Li@arm.com>
   7
   8         * arm.h (ARM_AEXT_V7VE): New define.
   9         (ARM_ARCH_V7VE): New define.
  10         (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
  11
  12 2013-11-18  Yufeng Zhang  <yufeng.zhang@arm.com>
  13
  14         Revert
  15
  16         2013-11-15  Yufeng Zhang  <yufeng.zhang@arm.com>
  17
  18         * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
  19         (aarch64_sys_reg_writeonly_p): Ditto.
  20
  21 2013-11-15  Yufeng Zhang  <yufeng.zhang@arm.com>
  22
  23         * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
  24         (aarch64_sys_reg_writeonly_p): Ditto.
  25
  26 2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
  27
  28         * aarch64.h (aarch64_sys_reg): New typedef.
  29         (aarch64_sys_regs): Change to define with the new type.
  30         (aarch64_sys_reg_deprecated_p): Declare.
  31
  32 2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
  33
  34         * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
  35         (enum aarch64_opnd): Add AARCH64_OPND_COND1.
  36
  37 2013-10-14  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
  38
  39         * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
  40         (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
  41         For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
  42         +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
  43         For MIPS, update extension character sequences after +.
  44         (ASE_MSA): New define.
  45         (ASE_MSA64): New define.
  46         For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
  47         +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
  48         For microMIPS, update extension character sequences after +.
  49
  50 2013-08-23  Yuri Chornoivan  <yurchor@ukr.net>
  51
  52         PR binutils/15834
  53         * i960.h: Fix typos.
  54
  55 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
  56
  57         * mips.h: Remove references to "+I" and imm2_expr.
  58
  59 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
  60
  61         * mips.h (M_DEXT, M_DINS): Delete.
  62
  63 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
  64
  65         * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
  66         (mips_optional_operand_p): New function.
  67
  68 2013-08-04  Jürgen Urban  <JuergenUrban@gmx.de>
  69             Richard Sandiford  <rdsandiford@googlemail.com>
  70
  71         * mips.h: Document new VU0 operand characters.
  72         (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
  73         (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
  74         (OP_REG_R5900_ACC): New mips_reg_operand_types.
  75         (INSN2_VU0_CHANNEL_SUFFIX): New macro.
  76         (mips_vu0_channel_mask): Declare.
  77
  78 2013-08-03  Richard Sandiford  <rdsandiford@googlemail.com>
  79
  80         * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
  81         (mips_int_operand_min, mips_int_operand_max): New functions.
  82         (mips_decode_pcrel_operand): Use mips_decode_int_operand.
  83
  84 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
  85
  86         * mips.h (mips_decode_reg_operand): New function.
  87         (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
  88         (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
  89         (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
  90         New macros.
  91         (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
  92         (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
  93         (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
  94         (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
  95         (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
  96         (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
  97         (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
  98         (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
  99         (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
 100         (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete.  Renumber other
 101         macros to cover the gaps.
 102         (INSN2_MOD_SP): Replace with...
 103         (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
 104         (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
 105         (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
 106         (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
 107         (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
 108         Delete.
 109
 110 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 111
 112         * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
 113         (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
 114         (MIPS16_INSN_COND_BRANCH): Delete.
 115
 116 2013-07-24  Anna Tikhonova  <anna.tikhonova@intel.com>
 117             Kirill Yukhin  <kirill.yukhin@intel.com>
 118             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 119
 120         * i386.h (BND_PREFIX_OPCODE): New.
 121
 122 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 123
 124         * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
 125         OP_SAVE_RESTORE_LIST.
 126         (decode_mips16_operand): Declare.
 127
 128 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 129
 130         * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
 131         (mips_operand, mips_int_operand, mips_mapped_int_operand)
 132         (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
 133         (mips_pcrel_operand): New structures.
 134         (mips_insert_operand, mips_extract_operand, mips_signed_operand)
 135         (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
 136         (decode_mips_operand, decode_micromips_operand): Declare.
 137
 138 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 139
 140         * mips.h: Document MIPS16 "I" opcode.
 141
 142 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 143
 144         * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
 145         (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
 146         (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
 147         (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
 148         (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
 149         (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
 150         (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
 151         (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
 152         (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
 153         (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
 154         (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
 155         (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
 156         (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
 157         Rename to...
 158         (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
 159         (M_USD_AB): ...these.
 160
 161 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 162
 163         * mips.h: Remove documentation of "[" and "]".  Update documentation
 164         of "k" and the MDMX formats.
 165
 166 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 167
 168         * mips.h: Update documentation of "+s" and "+S".
 169
 170 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 171
 172         * mips.h: Document "+i".
 173
 174 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 175
 176         * mips.h: Remove "mi" documentation.  Update "mh" documentation.
 177         (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
 178         Delete.
 179         (INSN2_WRITE_GPR_MHI): Rename to...
 180         (INSN2_WRITE_GPR_MH): ...this.
 181
 182 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 183
 184         * mips.h: Remove documentation of "+D" and "+T".
 185
 186 2013-06-26  Richard Sandiford  <rdsandiford@googlemail.com>
 187
 188         * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
 189         Use "source" rather than "destination" for microMIPS "G".
 190
 191 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
 192
 193         * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
 194         values.
 195
 196 2013-06-23  Richard Sandiford  <rdsandiford@googlemail.com>
 197
 198         * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
 199
 200 2013-06-17  Catherine Moore  <clm@codesourcery.com>
 201             Maciej W. Rozycki  <macro@codesourcery.com>
 202             Chao-Ying Fu  <fu@mips.com>
 203
 204         * mips.h (OP_SH_EVAOFFSET): Define.
 205         (OP_MASK_EVAOFFSET): Define.
 206         (INSN_ASE_MASK): Delete.
 207         (ASE_EVA): Define.
 208         (M_CACHEE_AB, M_CACHEE_OB): New.
 209         (M_LBE_OB, M_LBE_AB): New.
 210         (M_LBUE_OB, M_LBUE_AB): New.
 211         (M_LHE_OB, M_LHE_AB): New.
 212         (M_LHUE_OB, M_LHUE_AB): New.
 213         (M_LLE_AB, M_LLE_OB): New.
 214         (M_LWE_OB, M_LWE_AB): New.
 215         (M_LWLE_AB, M_LWLE_OB): New.
 216         (M_LWRE_AB, M_LWRE_OB): New.
 217         (M_PREFE_AB, M_PREFE_OB): New.
 218         (M_SCE_AB, M_SCE_OB): New.
 219         (M_SBE_OB, M_SBE_AB): New.
 220         (M_SHE_OB, M_SHE_AB): New.
 221         (M_SWE_OB, M_SWE_AB): New.
 222         (M_SWLE_AB, M_SWLE_OB): New.
 223         (M_SWRE_AB, M_SWRE_OB): New.
 224         (MICROMIPSOP_SH_EVAOFFSET): Define.
 225         (MICROMIPSOP_MASK_EVAOFFSET): Define.
 226
 227 2013-06-12  Sandra Loosemore  <sandra@codesourcery.com>
 228
 229         * nios2.h (OP_MATCH_ERET): Correct eret encoding.
 230
 231 2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
 232
 233         * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
 234
 235 2013-05-09  Andrew Pinski  <apinski@cavium.com>
 236
 237         * mips.h (OP_MASK_CODE10): Correct definition.
 238         (OP_SH_CODE10): Likewise.
 239         Add a comment that "+J" is used now for OP_*CODE10.
 240         (INSN_ASE_MASK): Update.
 241         (INSN_VIRT): New macro.
 242         (INSN_VIRT64): New macro
 243
 244 2013-05-02  Nick Clifton  <nickc@redhat.com>
 245
 246         * msp430.h: Add patterns for MSP430X instructions.
 247
 248 2013-04-06  David S. Miller  <davem@davemloft.net>
 249
 250         * sparc.h (F_PREFERRED): Define.
 251         (F_PREF_ALIAS): Define.
 252
 253 2013-04-03  Nick Clifton  <nickc@redhat.com>
 254
 255         * v850.h (V850_INVERSE_PCREL): Define.
 256
 257 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 258
 259         PR binutils/15068
 260         * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
 261
 262 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 263
 264         PR binutils/15068
 265         * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
 266         Add 16-bit opcodes.
 267         * tic6xc-opcode-table.h: Add 16-bit insns.
 268         * tic6x.h: Add support for 16-bit insns.
 269
 270 2013-03-21  Michael Schewe  <michael.schewe@gmx.net>
 271
 272         * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
 273         and mov.b/w/l Rs,@(d:32,ERd).
 274
 275 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 276
 277         PR gas/15082
 278         * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
 279         from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
 280         tic6x_operand_xregpair operand coding type.
 281         Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
 282         opcode field, usu ORXREGD1324 for the src2 operand and remove the
 283         TIC6X_FLAG_NO_CROSS.
 284
 285 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 286
 287         PR gas/15095
 288         * tic6x.h (enum tic6x_coding_method): Add
 289         tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
 290         separately the msb and lsb of a register pair.  This is needed to
 291         encode the opcodes in the same way as TI assembler does.
 292         * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
 293         and rsqrdp opcodes to use the new field coding types.
 294
 295 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 296
 297         * arm.h (CRC_EXT_ARMV8): New constant.
 298         (ARCH_CRC_ARMV8): New macro.
 299
 300 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
 301
 302         * aarch64.h (AARCH64_FEATURE_CRC): New macro.
 303
 304 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
 305             Andrew Jenner <andrew@codesourcery.com>
 306
 307         Based on patches from Altera Corporation.
 308
 309         * nios2.h: New file.
 310
 311 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
 312
 313         * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
 314
 315 2013-01-28  Alexis Deruelle  <alexis.deruelle@gmail.com>
 316
 317         PR gas/15069
 318         * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
 319
 320 2013-01-24  Nick Clifton  <nickc@redhat.com>
 321
 322         * v850.h: Add e3v5 support.
 323
 324 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
 325
 326         * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
 327
 328 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
 329
 330         * ppc.h (PPC_OPCODE_POWER8): New define.
 331         (PPC_OPCODE_HTM): Likewise.
 332
 333 2013-01-10  Will Newton <will.newton@imgtec.com>
 334
 335         * metag.h: New file.
 336
 337 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 338
 339         * cr16.h (make_instruction): Rename to cr16_make_instruction.
 340         (match_opcode): Rename to cr16_match_opcode.
 341
 342 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
 343
 344         * mips.h: Add support for r5900 instructions including lq and sq.
 345
 346 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 347
 348         * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
 349         (make_instruction,match_opcode): Added function prototypes.
 350         (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
 351
 352 2012-11-23  Alan Modra  <amodra@gmail.com>
 353
 354         * ppc.h (ppc_parse_cpu): Update prototype.
 355
 356 2012-10-14  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 357
 358         * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
 359         opcodes.  Likewise, use "cM" instead of "cm" in fstqs opcodes.
 360
 361 2012-10-04  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 362
 363         * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
 364
 365 2012-09-04  Sergey A. Guriev <sergey.a.guriev@intel.com>
 366
 367         * ia64.h (ia64_opnd): Add new operand types.
 368
 369 2012-08-21  David S. Miller  <davem@davemloft.net>
 370
 371         * sparc.h (F3F4): New macro.
 372
 373 2012-08-13  Ian Bolton  <ian.bolton@arm.com>
 374             Laurent Desnogues  <laurent.desnogues@arm.com>
 375             Jim MacArthur  <jim.macarthur@arm.com>
 376             Marcus Shawcroft  <marcus.shawcroft@arm.com>
 377             Nigel Stephens  <nigel.stephens@arm.com>
 378             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 379             Richard Earnshaw  <rearnsha@arm.com>
 380             Sofiane Naci  <sofiane.naci@arm.com>
 381             Tejas Belagod  <tejas.belagod@arm.com>
 382             Yufeng Zhang  <yufeng.zhang@arm.com>
 383
 384         * aarch64.h: New file.
 385
 386 2012-08-13  Richard Sandiford  <rdsandiford@googlemail.com>
 387             Maciej W. Rozycki  <macro@codesourcery.com>
 388
 389         * mips.h (mips_opcode): Add the exclusions field.
 390         (OPCODE_IS_MEMBER): Remove macro.
 391         (cpu_is_member): New inline function.
 392         (opcode_is_member): Likewise.
 393
 394 2012-07-31  Chao-Ying Fu  <fu@mips.com>
 395             Catherine Moore  <clm@codesourcery.com>
 396             Maciej W. Rozycki  <macro@codesourcery.com>
 397
 398         * mips.h: Document microMIPS DSP ASE usage.
 399         (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
 400         microMIPS DSP ASE support.
 401         (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
 402         (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
 403         (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
 404         (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
 405         (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
 406         (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
 407         (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
 408
 409 2012-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 410
 411         * mips.h: Fix a typo in description.
 412
 413 2012-06-07  Georg-Johann Lay  <avr@gjlay.de>
 414
 415         * avr.h: (AVR_ISA_XCH): New define.
 416         (AVR_ISA_XMEGA): Use it.
 417         (XCH, LAS, LAT, LAC): New XMEGA opcodes.
 418
 419 2012-05-15  James Murray <jsm@jsm-net.demon.co.uk>
 420
 421         * m68hc11.h: Add XGate definitions.
 422         (struct m68hc11_opcode): Add xg_mask field.
 423
 424 2012-05-14  Catherine Moore  <clm@codesourcery.com>
 425             Maciej W. Rozycki  <macro@codesourcery.com>
 426             Rhonda Wittels  <rhonda@codesourcery.com>
 427
 428         * ppc.h (PPC_OPCODE_VLE): New definition.
 429         (PPC_OP_SA): New macro.
 430         (PPC_OP_SE_VLE): New macro.
 431         (PPC_OP): Use a variable shift amount.
 432         (powerpc_operand): Update comments.
 433         (PPC_OPSHIFT_INV): New macro.
 434         (PPC_OPERAND_CR): Replace with...
 435         (PPC_OPERAND_CR_BIT): ...this and
 436         (PPC_OPERAND_CR_REG): ...this.
 437
 438
 439 2012-05-03  Sean Keys  <skeys@ipdatasys.com>
 440
 441         * xgate.h: Header file for XGATE assembler.
 442
 443 2012-04-27  David S. Miller  <davem@davemloft.net>
 444
 445         * sparc.h: Document new arg code' )' for crypto RS3
 446         immediates.
 447
 448         * sparc.h (struct sparc_opcode): New field 'hwcaps'.
 449         F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
 450         F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
 451         F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
 452         (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
 453         HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
 454         HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
 455         HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
 456         HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
 457         HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
 458         HWCAP_CBCOND, HWCAP_CRC32): New defines.
 459
 460 2012-03-10  Edmar Wienskoski  <edmar@freescale.com>
 461
 462         * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
 463
 464 2012-02-27  Alan Modra  <amodra@gmail.com>
 465
 466         * crx.h (cst4_map): Update declaration.
 467
 468 2012-02-25  Walter Lee  <walt@tilera.com>
 469
 470         * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
 471         TILEGX_OPC_LD_TLS.
 472         * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
 473         TILEPRO_OPC_LW_TLS_SN.
 474
 475 2012-02-08  H.J. Lu  <hongjiu.lu@intel.com>
 476
 477         * i386.h (XACQUIRE_PREFIX_OPCODE): New.
 478         (XRELEASE_PREFIX_OPCODE): Likewise.
 479
 480 2011-12-08  Andrew Pinski  <apinski@cavium.com>
 481             Adam Nemet  <anemet@caviumnetworks.com>
 482
 483         * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
 484         (INSN_OCTEON2): New macro.
 485         (CPU_OCTEON2): New macro.
 486         (OPCODE_IS_MEMBER): Add Octeon2.
 487
 488 2011-11-29  Andrew Pinski  <apinski@cavium.com>
 489
 490         * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
 491         (INSN_OCTEONP): New macro.
 492         (CPU_OCTEONP): New macro.
 493         (OPCODE_IS_MEMBER): Add Octeon+.
 494         (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
 495
 496 2011-11-01  DJ Delorie  <dj@redhat.com>
 497
 498         * rl78.h: New file.
 499
 500 2011-10-24  Maciej W. Rozycki  <macro@codesourcery.com>
 501
 502         * mips.h: Fix a typo in description.
 503
 504 2011-09-21  David S. Miller  <davem@davemloft.net>
 505
 506         * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
 507         (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
 508         F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
 509         F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
 510
 511 2011-08-09  Chao-ying Fu  <fu@mips.com>
 512             Maciej W. Rozycki  <macro@codesourcery.com>
 513
 514         * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
 515         (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
 516         (INSN_ASE_MASK): Add the MCU bit.
 517         (INSN_MCU): New macro.
 518         (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
 519         (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
 520
 521 2011-08-09  Maciej W. Rozycki  <macro@codesourcery.com>
 522
 523         * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
 524         (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
 525         (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
 526         (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
 527         (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
 528         (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
 529         (INSN2_READ_GPR_MMN): Likewise.
 530         (INSN2_READ_FPR_D): Change the bit used.
 531         (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
 532         (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
 533         (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
 534         (INSN2_COND_BRANCH): Likewise.
 535         (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
 536         (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
 537         (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
 538         (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
 539         (INSN2_MOD_GPR_MN): Likewise.
 540
 541 2011-08-05  David S. Miller  <davem@davemloft.net>
 542
 543         * sparc.h: Document new format codes '4', '5', and '('.
 544         (OPF_LOW4, RS3): New macros.
 545
 546 2011-08-03  Maciej W. Rozycki  <macro@codesourcery.com>
 547
 548         * mips.h: Document the use of FP_D in MIPS16 mode.  Adjust the
 549         order of flags documented.
 550
 551 2011-07-29  Maciej W. Rozycki  <macro@codesourcery.com>
 552
 553         * mips.h: Clarify the description of microMIPS instruction
 554         manipulation macros.
 555         (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
 556
 557 2011-07-24  Chao-ying Fu  <fu@mips.com>
 558             Maciej W. Rozycki  <macro@codesourcery.com>
 559
 560         * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
 561         (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
 562         (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
 563         (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
 564         (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
 565         (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
 566         (OP_MASK_RS3, OP_SH_RS3): Likewise.
 567         (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
 568         (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
 569         (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
 570         (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
 571         (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
 572         (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
 573         (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
 574         (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
 575         (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
 576         (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
 577         (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
 578         (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
 579         (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
 580         (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
 581         (INSN_WRITE_GPR_S): New macro.
 582         (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
 583         (INSN2_READ_FPR_D): Likewise.
 584         (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
 585         (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
 586         (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
 587         (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
 588         (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
 589         (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
 590         (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
 591         (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
 592         (CPU_MICROMIPS): New macro.
 593         (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
 594         (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
 595         (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
 596         (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
 597         (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
 598         (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
 599         (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
 600         (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
 601         (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
 602         (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
 603         (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
 604         (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
 605         (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
 606         (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
 607         (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
 608         (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
 609         (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
 610         (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
 611         (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
 612         (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
 613         (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
 614         (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
 615         (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
 616         (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
 617         (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
 618         (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
 619         (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
 620         (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
 621         (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
 622         (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
 623         (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
 624         (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
 625         (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
 626         (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
 627         (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
 628         (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
 629         (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
 630         (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
 631         (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
 632         (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
 633         (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
 634         (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
 635         (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
 636         (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
 637         (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
 638         (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
 639         (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
 640         (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
 641         (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
 642         (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
 643         (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
 644         (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
 645         (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
 646         (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
 647         (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
 648         (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
 649         (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
 650         (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
 651         (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
 652         (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
 653         (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
 654         (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
 655         (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
 656         (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
 657         (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
 658         (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
 659         (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
 660         (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
 661         (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
 662         (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
 663         (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
 664         (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
 665         (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
 666         (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
 667         (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
 668         (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
 669         (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
 670         (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
 671         (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
 672         (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
 673         (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
 674         (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
 675         (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
 676         (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
 677         (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
 678         (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
 679         (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
 680         (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
 681         (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
 682         (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
 683         (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
 684         (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
 685         (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
 686         (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
 687         (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
 688         (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
 689         (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
 690         (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
 691         (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
 692         (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
 693         (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
 694         (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
 695         (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
 696         (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
 697         (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
 698         (micromips_opcodes): New declaration.
 699         (bfd_micromips_num_opcodes): Likewise.
 700
 701 2011-07-24  Maciej W. Rozycki  <macro@codesourcery.com>
 702
 703         * mips.h (INSN_TRAP): Rename to...
 704         (INSN_NO_DELAY_SLOT): ... this.
 705         (INSN_SYNC): Remove macro.
 706
 707 2011-07-01  Eric B. Weddington  <eric.weddington@atmel.com>
 708
 709         * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
 710         a duplicate of AVR_ISA_SPM.
 711
 712 2011-07-01  Nick Clifton  <nickc@redhat.com>
 713
 714         * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
 715
 716 2011-06-18  Robin Getz  <robin.getz@analog.com>
 717
 718         * bfin.h (is_macmod_signed): New func
 719
 720 2011-06-18  Mike Frysinger  <vapier@gentoo.org>
 721
 722         * bfin.h (is_macmod_pmove): Add missing space before func args.
 723         (is_macmod_hmove): Likewise.
 724
 725 2011-06-13  Walter Lee  <walt@tilera.com>
 726
 727         * tilegx.h: New file.
 728         * tilepro.h: New file.
 729
 730 2011-05-31  Paul Brook  <paul@codesourcery.com>
 731
 732         * arm.h (ARM_ARCH_V7R_IDIV): Define.
 733
 734 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 735
 736         * s390.h: Replace S390_OPERAND_REG_EVEN with
 737         S390_OPERAND_REG_PAIR.
 738
 739 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 740
 741         * s390.h: Add S390_OPCODE_REG_EVEN flag.
 742
 743 2011-04-18  Julian Brown  <julian@codesourcery.com>
 744
 745         * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
 746
 747 2011-04-11  Dan McDonald  <dan@wellkeeper.com>
 748
 749         PR gas/12296
 750         * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
 751
 752 2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>
 753
 754         * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
 755         New instruction set flags.
 756         (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
 757
 758 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 759
 760         * mips.h (M_PREF_AB): New enum value.
 761
 762 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 763
 764         * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
 765         M_IU): Define.
 766         (is_macmod_pmove, is_macmod_hmove): New functions.
 767
 768 2011-02-11  Mike Frysinger  <vapier@gentoo.org>
 769
 770         * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
 771
 772 2011-02-04  Bernd Schmidt  <bernds@codesourcery.com>
 773
 774         * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
 775         * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
 776
 777 2010-12-31  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 778
 779         PR gas/11395
 780         * hppa.h (pa_opcodes): Revert last change.  Exchange 32 and 64-bit
 781         "bb" entries.
 782
 783 2010-12-26  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 784
 785         PR gas/11395
 786         * hppa.h: Clear "d" bit in "add" and "sub" patterns.
 787
 788 2010-12-18  Richard Sandiford  <rdsandiford@googlemail.com>
 789
 790         * mips.h: Update commentary after last commit.
 791
 792 2010-12-18  Mingjie Xing  <mingjie.xing@gmail.com>
 793
 794         * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
 795         (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
 796         (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
 797
 798 2010-11-25  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 799
 800         * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
 801
 802 2010-11-23  Richard Sandiford  <rdsandiford@googlemail.com>
 803
 804         * mips.h: Fix previous commit.
 805
 806 2010-11-23  Maciej W. Rozycki  <macro@linux-mips.org>
 807
 808         * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
 809         (INSN_LOONGSON_3A): Clear bit 31.
 810
 811 2010-11-15  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 812
 813         PR gas/12198
 814         * arm.h (ARM_AEXT_V6M_ONLY): New define.
 815         (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
 816         (ARM_ARCH_V6M_ONLY): New define.
 817
 818 2010-11-11  Mingming Sun  <mingm.sun@gmail.com>
 819
 820         * mips.h (INSN_LOONGSON_3A): Defined.
 821         (CPU_LOONGSON_3A): Defined.
 822         (OPCODE_IS_MEMBER): Add LOONGSON_3A.
 823
 824 2010-10-09  Matt Rice  <ratmice@gmail.com>
 825
 826         * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
 827         (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
 828
 829 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 830
 831         * arm.h (ARM_EXT_VIRT): New define.
 832         (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
 833         (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
 834         Extensions.
 835
 836 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 837
 838         * arm.h (ARM_AEXT_ADIV): New define.
 839         (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
 840
 841 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 842
 843         * arm.h (ARM_EXT_OS): New define.
 844         (ARM_AEXT_V6SM): Likewise.
 845         (ARM_ARCH_V6SM): Likewise.
 846
 847 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 848
 849         * arm.h (ARM_EXT_MP): Add.
 850         (ARM_ARCH_V7A_MP): Likewise.
 851
 852 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 853
 854         * bfin.h: Declare pseudoChr structs/defines.
 855
 856 2010-09-21  Mike Frysinger  <vapier@gentoo.org>
 857
 858         * bfin.h: Strip trailing whitespace.
 859
 860 2010-07-29  DJ Delorie  <dj@redhat.com>
 861
 862         * rx.h (RX_Operand_Type): Add TwoReg.
 863         (RX_Opcode_ID): Remove ediv and ediv2.
 864
 865 2010-07-27  DJ Delorie  <dj@redhat.com>
 866
 867         * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
 868
 869 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
 870             Ina Pandit  <ina.pandit@kpitcummins.com>
 871
 872         * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
 873         PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
 874         PROCESSOR_V850E2_ALL.
 875         Remove PROCESSOR_V850EA support.
 876         (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
 877         V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
 878         V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
 879         V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
 880         V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
 881         V850_OPERAND_PERCENT.
 882         Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
 883         V850_NOT_R0.
 884         Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
 885         and V850E_PUSH_POP
 886
 887 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 888
 889         * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
 890         (MIPS16_INSN_BRANCH): Rename to...
 891         (MIPS16_INSN_COND_BRANCH): ... this.
 892
 893 2010-07-03  Alan Modra  <amodra@gmail.com>
 894
 895         * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
 896         Renumber other PPC_OPCODE defines.
 897
 898 2010-07-03  Alan Modra  <amodra@gmail.com>
 899
 900         * ppc.h (PPC_OPCODE_COMMON): Expand comment.
 901
 902 2010-06-29  Alan Modra  <amodra@gmail.com>
 903
 904         * maxq.h: Delete file.
 905
 906 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 907
 908         * ppc.h (PPC_OPCODE_E500): Define.
 909
 910 2010-05-26  Catherine Moore  <clm@codesourcery.com>
 911
 912         * opcode/mips.h (INSN_MIPS16): Remove.
 913
 914 2010-04-21  Joseph Myers  <joseph@codesourcery.com>
 915
 916         * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
 917
 918 2010-04-15  Nick Clifton  <nickc@redhat.com>
 919
 920         * alpha.h: Update copyright notice to use GPLv3.
 921         * arc.h: Likewise.
 922         * arm.h: Likewise.
 923         * avr.h: Likewise.
 924         * bfin.h: Likewise.
 925         * cgen.h: Likewise.
 926         * convex.h: Likewise.
 927         * cr16.h: Likewise.
 928         * cris.h: Likewise.
 929         * crx.h: Likewise.
 930         * d10v.h: Likewise.
 931         * d30v.h: Likewise.
 932         * dlx.h: Likewise.
 933         * h8300.h: Likewise.
 934         * hppa.h: Likewise.
 935         * i370.h: Likewise.
 936         * i386.h: Likewise.
 937         * i860.h: Likewise.
 938         * i960.h: Likewise.
 939         * ia64.h: Likewise.
 940         * m68hc11.h: Likewise.
 941         * m68k.h: Likewise.
 942         * m88k.h: Likewise.
 943         * maxq.h: Likewise.
 944         * mips.h: Likewise.
 945         * mmix.h: Likewise.
 946         * mn10200.h: Likewise.
 947         * mn10300.h: Likewise.
 948         * msp430.h: Likewise.
 949         * np1.h: Likewise.
 950         * ns32k.h: Likewise.
 951         * or32.h: Likewise.
 952         * pdp11.h: Likewise.
 953         * pj.h: Likewise.
 954         * pn.h: Likewise.
 955         * ppc.h: Likewise.
 956         * pyr.h: Likewise.
 957         * rx.h: Likewise.
 958         * s390.h: Likewise.
 959         * score-datadep.h: Likewise.
 960         * score-inst.h: Likewise.
 961         * sparc.h: Likewise.
 962         * spu-insns.h: Likewise.
 963         * spu.h: Likewise.
 964         * tic30.h: Likewise.
 965         * tic4x.h: Likewise.
 966         * tic54x.h: Likewise.
 967         * tic80.h: Likewise.
 968         * v850.h: Likewise.
 969         * vax.h: Likewise.
 970
 971 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
 972
 973         * tic6x-control-registers.h, tic6x-insn-formats.h,
 974         tic6x-opcode-table.h, tic6x.h: New.
 975
 976 2010-02-25  Wu Zhangjin  <wuzhangjin@gmail.com>
 977
 978         * mips.h: (LOONGSON2F_NOP_INSN): New macro.
 979
 980 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
 981
 982         * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
 983
 984 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 985
 986         * ia64.h (ia64_find_opcode): Remove argument name.
 987         (ia64_find_next_opcode): Likewise.
 988         (ia64_dis_opcode): Likewise.
 989         (ia64_free_opcode): Likewise.
 990         (ia64_find_dependency): Likewise.
 991
 992 2009-11-22  Doug Evans  <dje@sebabeach.org>
 993
 994         * cgen.h: Include bfd_stdint.h.
 995         (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
 996
 997 2009-11-18  Paul Brook  <paul@codesourcery.com>
 998
 999         * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1000
1001 2009-11-17  Paul Brook  <paul@codesourcery.com>
1002         Daniel Jacobowitz  <dan@codesourcery.com>
1003
1004         * arm.h (ARM_EXT_V6_DSP): Define.
1005         (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1006         (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1007
1008 2009-11-04  DJ Delorie  <dj@redhat.com>
1009
1010         * rx.h (rx_decode_opcode) (mvtipl): Add.
1011         (mvtcp, mvfcp, opecp): Remove.
1012
1013 2009-11-02  Paul Brook  <paul@codesourcery.com>
1014
1015         * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1016         FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1017         (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1018         FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1019         FPU_ARCH_NEON_VFP_V4): Define.
1020
1021 2009-10-23  Doug Evans  <dje@sebabeach.org>
1022
1023         * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1024         * cgen.h: Update.  Improve multi-inclusion macro name.
1025
1026 2009-10-02  Peter Bergner  <bergner@vnet.ibm.com>
1027
1028         * ppc.h (PPC_OPCODE_476): Define.
1029
1030 2009-10-01  Peter Bergner  <bergner@vnet.ibm.com>
1031
1032         * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1033
1034 2009-09-29  DJ Delorie  <dj@redhat.com>
1035
1036         * rx.h: New file.
1037
1038 2009-09-22  Peter Bergner  <bergner@vnet.ibm.com>
1039
1040         * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1041
1042 2009-09-21  Ben Elliston  <bje@au.ibm.com>
1043
1044         * ppc.h (PPC_OPCODE_PPCA2): New.
1045
1046 2009-09-05  Martin Thuresson  <martin@mtme.org>
1047
1048         * ia64.h (struct ia64_operand): Renamed member class to op_class.
1049
1050 2009-08-29  Martin Thuresson  <martin@mtme.org>
1051
1052         * tic30.h (template): Rename type template to
1053         insn_template. Updated code to use new name.
1054         * tic54x.h (template): Rename type template to
1055         insn_template.
1056
1057 2009-08-20  Nick Hudson  <nick.hudson@gmx.co.uk>
1058
1059         * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1060
1061 2009-06-11  Anthony Green  <green@moxielogic.com>
1062
1063         * moxie.h (MOXIE_F3_PCREL): Define.
1064         (moxie_form3_opc_info): Grow.
1065
1066 2009-06-06  Anthony Green  <green@moxielogic.com>
1067
1068         * moxie.h (MOXIE_F1_M): Define.
1069
1070 2009-04-15  Anthony Green  <green@moxielogic.com>
1071
1072         * moxie.h: Created.
1073
1074 2009-04-06  DJ Delorie  <dj@redhat.com>
1075
1076         * h8300.h: Add relaxation attributes to MOVA opcodes.
1077
1078 2009-03-10  Alan Modra  <amodra@bigpond.net.au>
1079
1080         * ppc.h (ppc_parse_cpu): Declare.
1081
1082 2009-03-02  Qinwei  <qinwei@sunnorth.com.cn>
1083
1084         * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1085         and _IMM11 for mbitclr and mbitset.
1086         * score-datadep.h: Update dependency information.
1087
1088 2009-02-26  Peter Bergner  <bergner@vnet.ibm.com>
1089
1090         * ppc.h (PPC_OPCODE_POWER7): New.
1091
1092 2009-02-06  Doug Evans  <dje@google.com>
1093
1094         * i386.h: Add comment regarding sse* insns and prefixes.
1095
1096 2009-02-03  Sandip Matte  <sandip@rmicorp.com>
1097
1098         * mips.h (INSN_XLR): Define.
1099         (INSN_CHIP_MASK): Update.
1100         (CPU_XLR): Define.
1101         (OPCODE_IS_MEMBER): Update.
1102         (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1103
1104 2009-01-28  Doug Evans  <dje@google.com>
1105
1106         * opcode/i386.h: Add multiple inclusion protection.
1107         (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1108         (EDI_REG_NUM): New macros.
1109         (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1110         (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1111         (REX_PREFIX_P): New macro.
1112
1113 2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
1114
1115         * ppc.h (struct powerpc_opcode): New field "deprecated".
1116         (PPC_OPCODE_NOPOWER4): Delete.
1117
1118 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
1119
1120         * mips.h: Define CPU_R14000, CPU_R16000.
1121         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1122
1123 2008-11-18  Catherine Moore  <clm@codesourcery.com>
1124
1125         * arm.h (FPU_NEON_FP16): New.
1126         (FPU_ARCH_NEON_FP16): New.
1127
1128 2008-11-06  Chao-ying Fu  <fu@mips.com>
1129
1130         * mips.h: Doucument '1' for 5-bit sync type.
1131
1132 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
1133
1134         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
1135         IA64_RS_CR.
1136
1137 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
1138
1139         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1140
1141 2008-07-30  Michael J. Eager  <eager@eagercon.com>
1142
1143         * ppc.h (PPC_OPCODE_405): Define.
1144         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1145
1146 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
1147
1148         * ppc.h (ppc_cpu_t): New typedef.
1149         (struct powerpc_opcode <flags>): Use it.
1150         (struct powerpc_operand <insert, extract>): Likewise.
1151         (struct powerpc_macro <flags>): Likewise.
1152
1153 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
1154
1155         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1156         Update comment before MIPS16 field descriptors to mention MIPS16.
1157         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1158         BBIT.
1159         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1160         New bit masks and shift counts for cins and exts.
1161
1162         * mips.h: Document new field descriptors +Q.
1163         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1164
1165 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
1166
1167         * mips.h (INSN_MACRO): Move it up to the pinfo macros.
1168         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1169
1170 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
1171
1172         * ppc.h: (PPC_OPCODE_E500MC): New.
1173
1174 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
1175
1176         * i386.h (MAX_OPERANDS): Set to 5.
1177         (MAX_MNEM_SIZE): Changed to 20.
1178
1179 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
1180
1181         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1182
1183 2008-03-09  Paul Brook  <paul@codesourcery.com>
1184
1185         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1186
1187 2008-03-04  Paul Brook  <paul@codesourcery.com>
1188
1189         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1190         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1191         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1192
1193 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
1194             Nick Clifton  <nickc@redhat.com>
1195
1196         PR 3134
1197         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1198         with a 32-bit displacement but without the top bit of the 4th byte
1199         set.
1200
1201 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1202
1203         * cr16.h (cr16_num_optab): Declared.
1204
1205 2008-02-14  Hakan Ardo  <hakan@debian.org>
1206
1207         PR gas/2626
1208         * avr.h (AVR_ISA_2xxe): Define.
1209
1210 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
1211
1212         * mips.h: Update copyright.
1213         (INSN_CHIP_MASK): New macro.
1214         (INSN_OCTEON): New macro.
1215         (CPU_OCTEON): New macro.
1216         (OPCODE_IS_MEMBER): Handle Octeon instructions.
1217
1218 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
1219
1220         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1221
1222 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
1223
1224         * avr.h (AVR_ISA_USB162): Add new opcode set.
1225         (AVR_ISA_AVR3): Likewise.
1226
1227 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
1228
1229         * mips.h (INSN_LOONGSON_2E): New.
1230         (INSN_LOONGSON_2F): New.
1231         (CPU_LOONGSON_2E): New.
1232         (CPU_LOONGSON_2F): New.
1233         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1234
1235 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
1236
1237         * mips.h (INSN_ISA*): Redefine certain values as an
1238         enumeration.  Update comments.
1239         (mips_isa_table): New.
1240         (ISA_MIPS*): Redefine to match enumeration.
1241         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1242         values.
1243
1244 2007-08-08  Ben Elliston  <bje@au.ibm.com>
1245
1246         * ppc.h (PPC_OPCODE_PPCPS): New.
1247
1248 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
1249
1250         * m68k.h: Document j K & E.
1251
1252 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
1253
1254         * cr16.h: New file for CR16 target.
1255
1256 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
1257
1258         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1259
1260 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
1261
1262         * m68k.h (mcfisa_c): New.
1263         (mcfusp, mcf_mask): Adjust.
1264
1265 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
1266
1267         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1268         (num_powerpc_operands): Declare.
1269         (PPC_OPERAND_SIGNED et al): Redefine as hex.
1270         (PPC_OPERAND_PLUS1): Define.
1271
1272 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
1273
1274         * i386.h (REX_MODE64): Renamed to ...
1275         (REX_W): This.
1276         (REX_EXTX): Renamed to ...
1277         (REX_R): This.
1278         (REX_EXTY): Renamed to ...
1279         (REX_X): This.
1280         (REX_EXTZ): Renamed to ...
1281         (REX_B): This.
1282
1283 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
1284
1285         * i386.h: Add entries from config/tc-i386.h and move tables
1286         to opcodes/i386-opc.h.
1287
1288 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
1289
1290         * i386.h (FloatDR): Removed.
1291         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1292
1293 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
1294
1295         * spu-insns.h: Add soma double-float insns.
1296
1297 2007-02-20  Thiemo Seufer  <ths@mips.com>
1298             Chao-Ying Fu  <fu@mips.com>
1299
1300         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1301         (INSN_DSPR2): Add flag for DSP R2 instructions.
1302         (M_BALIGN): New macro.
1303
1304 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
1305
1306         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1307         and Seg3ShortFrom with Shortform.
1308
1309 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
1310
1311         PR gas/4027
1312         * i386.h (i386_optab): Put the real "test" before the pseudo
1313         one.
1314
1315 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
1316
1317         * m68k.h (m68010up): OR fido_a.
1318
1319 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
1320
1321         * m68k.h (fido_a): New.
1322
1323 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
1324
1325         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1326         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1327         values.
1328
1329 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
1330
1331         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1332
1333 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
1334
1335         * score-inst.h (enum score_insn_type): Add Insn_internal.
1336
1337 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
1338             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
1339             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
1340             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
1341             Alan Modra  <amodra@bigpond.net.au>
1342
1343         * spu-insns.h: New file.
1344         * spu.h: New file.
1345
1346 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
1347
1348         * ppc.h (PPC_OPCODE_CELL): Define.
1349
1350 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
1351
1352         * i386.h :  Modify opcode to support for the change in POPCNT opcode
1353         in amdfam10 architecture.
1354
1355 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
1356
1357         * i386.h: Replace CpuMNI with CpuSSSE3.
1358
1359 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
1360             Joseph Myers  <joseph@codesourcery.com>
1361             Ian Lance Taylor  <ian@wasabisystems.com>
1362             Ben Elliston  <bje@wasabisystems.com>
1363
1364         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1365
1366 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
1367
1368         * score-datadep.h: New file.
1369         * score-inst.h: New file.
1370
1371 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
1372
1373         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1374         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1375         movdq2q and movq2dq.
1376
1377 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
1378            Michael Meissner             <michael.meissner@amd.com>
1379
1380         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1381
1382 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
1383
1384         * i386.h (i386_optab): Add "nop" with memory reference.
1385
1386 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
1387
1388         * i386.h (i386_optab): Update comment for 64bit NOP.
1389
1390 2006-06-06  Ben Elliston  <bje@au.ibm.com>
1391             Anton Blanchard  <anton@samba.org>
1392
1393         * ppc.h (PPC_OPCODE_POWER6): Define.
1394         Adjust whitespace.
1395
1396 2006-06-05  Thiemo Seufer  <ths@mips.com>
1397
1398         * mips.h: Improve description of MT flags.
1399
1400 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
1401
1402         * m68k.h (mcf_mask): Define.
1403
1404 2006-05-05  Thiemo Seufer  <ths@mips.com>
1405             David Ung  <davidu@mips.com>
1406
1407         * mips.h (enum): Add macro M_CACHE_AB.
1408
1409 2006-05-04  Thiemo Seufer  <ths@mips.com>
1410             Nigel Stephens  <nigel@mips.com>
1411             David Ung  <davidu@mips.com>
1412
1413         * mips.h: Add INSN_SMARTMIPS define.
1414
1415 2006-04-30  Thiemo Seufer  <ths@mips.com>
1416             David Ung  <davidu@mips.com>
1417
1418         * mips.h: Defines udi bits and masks.  Add description of
1419         characters which may appear in the args field of udi
1420         instructions.
1421
1422 2006-04-26  Thiemo Seufer  <ths@networkno.de>
1423
1424         * mips.h: Improve comments describing the bitfield instruction
1425         fields.
1426
1427 2006-04-26  Julian Brown  <julian@codesourcery.com>
1428
1429         * arm.h (FPU_VFP_EXT_V3): Define constant.
1430         (FPU_NEON_EXT_V1): Likewise.
1431         (FPU_VFP_HARD): Update.
1432         (FPU_VFP_V3): Define macro.
1433         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1434
1435 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
1436
1437         * avr.h (AVR_ISA_PWMx): New.
1438
1439 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
1440
1441         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1442         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1443         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1444         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1445         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1446
1447 2006-03-10  Paul Brook  <paul@codesourcery.com>
1448
1449         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1450
1451 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1452
1453         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1454         first.  Correct mask of bb "B" opcode.
1455
1456 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
1457
1458         * i386.h (i386_optab): Support Intel Merom New Instructions.
1459
1460 2006-02-24  Paul Brook  <paul@codesourcery.com>
1461
1462         * arm.h: Add V7 feature bits.
1463
1464 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
1465
1466         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1467
1468 2006-01-31  Paul Brook  <paul@codesourcery.com>
1469         Richard Earnshaw <rearnsha@arm.com>
1470
1471         * arm.h: Use ARM_CPU_FEATURE.
1472         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1473         (arm_feature_set): Change to a structure.
1474         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1475         ARM_FEATURE): New macros.
1476
1477 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
1478
1479         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1480         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1481         (ADD_PC_INCR_OPCODE): Don't define.
1482
1483 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
1484
1485         PR gas/1874
1486         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1487
1488 2005-11-14  David Ung  <davidu@mips.com>
1489
1490         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1491         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1492         save/restore encoding of the args field.
1493
1494 2005-10-28  Dave Brolley  <brolley@redhat.com>
1495
1496         Contribute the following changes:
1497         2005-02-16  Dave Brolley  <brolley@redhat.com>
1498
1499         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1500         cgen_isa_mask_* to cgen_bitset_*.
1501         * cgen.h: Likewise.
1502
1503         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
1504
1505         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1506         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1507         (CGEN_CPU_TABLE): Make isas a ponter.
1508
1509         2003-09-29  Dave Brolley  <brolley@redhat.com>
1510
1511         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1512         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1513         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1514
1515         2002-12-13  Dave Brolley  <brolley@redhat.com>
1516
1517         * cgen.h (symcat.h): #include it.
1518         (cgen-bitset.h): #include it.
1519         (CGEN_ATTR_VALUE_TYPE): Now a union.
1520         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1521         (CGEN_ATTR_ENTRY): 'value' now unsigned.
1522         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1523         * cgen-bitset.h: New file.
1524
1525 2005-09-30  Catherine Moore  <clm@cm00re.com>
1526
1527         * bfin.h: New file.
1528
1529 2005-10-24  Jan Beulich  <jbeulich@novell.com>
1530
1531         * ia64.h (enum ia64_opnd): Move memory operand out of set of
1532         indirect operands.
1533
1534 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1535
1536         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
1537         Add FLAG_STRICT to pa10 ftest opcode.
1538
1539 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1540
1541         * hppa.h (pa_opcodes): Remove lha entries.
1542
1543 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1544
1545         * hppa.h (FLAG_STRICT): Revise comment.
1546         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
1547         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
1548         entries for "fdc".
1549
1550 2005-09-30  Catherine Moore  <clm@cm00re.com>
1551
1552         * bfin.h: New file.
1553
1554 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1555
1556         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1557
1558 2005-09-06  Chao-ying Fu  <fu@mips.com>
1559
1560         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1561         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1562         define.
1563         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1564         (INSN_ASE_MASK): Update to include INSN_MT.
1565         (INSN_MT): New define for MT ASE.
1566
1567 2005-08-25  Chao-ying Fu  <fu@mips.com>
1568
1569         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1570         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1571         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1572         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1573         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1574         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1575         instructions.
1576         (INSN_DSP): New define for DSP ASE.
1577
1578 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
1579
1580         * a29k.h: Delete.
1581
1582 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
1583
1584         * ppc.h (PPC_OPCODE_E300): Define.
1585
1586 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
1587
1588         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1589
1590 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1591
1592         PR gas/336
1593         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1594         and pitlb.
1595
1596 2005-07-27  Jan Beulich  <jbeulich@novell.com>
1597
1598         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1599         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1600         Add movq-s as 64-bit variants of movd-s.
1601
1602 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1603
1604         * hppa.h: Fix punctuation in comment.
1605
1606         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
1607         implicit space-register addressing.  Set space-register bits on opcodes
1608         using implicit space-register addressing.  Add various missing pa20
1609         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
1610         space-register addressing.  Use "fE" instead of "fe" in various
1611         fstw opcodes.
1612
1613 2005-07-18  Jan Beulich  <jbeulich@novell.com>
1614
1615         * i386.h (i386_optab): Operands of aam and aad are unsigned.
1616
1617 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
1618
1619         * i386.h (i386_optab): Support Intel VMX Instructions.
1620
1621 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1622
1623         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1624
1625 2005-07-05  Jan Beulich  <jbeulich@novell.com>
1626
1627         * i386.h (i386_optab): Add new insns.
1628
1629 2005-07-01  Nick Clifton  <nickc@redhat.com>
1630
1631         * sparc.h: Add typedefs to structure declarations.
1632
1633 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
1634
1635         PR 1013
1636         * i386.h (i386_optab): Update comments for 64bit addressing on
1637         mov. Allow 64bit addressing for mov and movq.
1638
1639 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1640
1641         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1642         respectively, in various floating-point load and store patterns.
1643
1644 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1645
1646         * hppa.h (FLAG_STRICT): Correct comment.
1647         (pa_opcodes): Update load and store entries to allow both PA 1.X and
1648         PA 2.0 mneumonics when equivalent.  Entries with cache control
1649         completers now require PA 1.1.  Adjust whitespace.
1650
1651 2005-05-19  Anton Blanchard  <anton@samba.org>
1652
1653         * ppc.h (PPC_OPCODE_POWER5): Define.
1654
1655 2005-05-10  Nick Clifton  <nickc@redhat.com>
1656
1657         * Update the address and phone number of the FSF organization in
1658         the GPL notices in the following files:
1659         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1660         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1661         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1662         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1663         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1664         tic54x.h, tic80.h, v850.h, vax.h
1665
1666 2005-05-09  Jan Beulich  <jbeulich@novell.com>
1667
1668         * i386.h (i386_optab): Add ht and hnt.
1669
1670 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
1671
1672         * i386.h: Insert hyphens into selected VIA PadLock extensions.
1673         Add xcrypt-ctr.  Provide aliases without hyphens.
1674
1675 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
1676
1677         Moved from ../ChangeLog
1678
1679         2005-04-12  Paul Brook  <paul@codesourcery.com>
1680         * m88k.h: Rename psr macros to avoid conflicts.
1681
1682         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
1683         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1684         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1685         and ARM_ARCH_V6ZKT2.
1686
1687         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
1688         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1689         Remove redundant instruction types.
1690         (struct argument): X_op - new field.
1691         (struct cst4_entry): Remove.
1692         (no_op_insn): Declare.
1693
1694         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
1695         * crx.h (enum argtype): Rename types, remove unused types.
1696
1697         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
1698         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1699         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1700         (enum operand_type): Rearrange operands, edit comments.
1701         replace us<N> with ui<N> for unsigned immediate.
1702         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1703         displacements (respectively).
1704         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1705         (instruction type): Add NO_TYPE_INS.
1706         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1707         (operand_entry): New field - 'flags'.
1708         (operand flags): New.
1709
1710         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
1711         * crx.h (operand_type): Remove redundant types i3, i4,
1712         i5, i8, i12.
1713         Add new unsigned immediate types us3, us4, us5, us16.
1714
1715 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
1716
1717         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1718         adjust them accordingly.
1719
1720 2005-04-01  Jan Beulich  <jbeulich@novell.com>
1721
1722         * i386.h (i386_optab): Add rdtscp.
1723
1724 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
1725
1726         * i386.h (i386_optab): Don't allow the `l' suffix for moving
1727         between memory and segment register. Allow movq for moving between
1728         general-purpose register and segment register.
1729
1730 2005-02-09  Jan Beulich  <jbeulich@novell.com>
1731
1732         PR gas/707
1733         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1734         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1735         fnstsw.
1736
1737 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
1738
1739         * m68k.h (m68008, m68ec030, m68882): Remove.
1740         (m68k_mask): New.
1741         (cpu_m68k, cpu_cf): New.
1742         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1743         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1744
1745 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
1746
1747         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
1748         * cgen.h (enum cgen_parse_operand_type): Add
1749         CGEN_PARSE_OPERAND_SYMBOLIC.
1750
1751 2005-01-21  Fred Fish  <fnf@specifixinc.com>
1752
1753         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1754         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1755         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1756
1757 2005-01-19  Fred Fish  <fnf@specifixinc.com>
1758
1759         * mips.h (struct mips_opcode): Add new pinfo2 member.
1760         (INSN_ALIAS): New define for opcode table entries that are
1761         specific instances of another entry, such as 'move' for an 'or'
1762         with a zero operand.
1763         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1764         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1765
1766 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
1767
1768         * mips.h (CPU_RM9000): Define.
1769         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1770
1771 2004-11-25 Jan Beulich  <jbeulich@novell.com>
1772
1773         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1774         to/from test registers are illegal in 64-bit mode. Add missing
1775         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1776         (previously one had to explicitly encode a rex64 prefix). Re-enable
1777         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1778         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1779
1780 2004-11-23 Jan Beulich  <jbeulich@novell.com>
1781
1782         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1783         available only with SSE2. Change the MMX additions introduced by SSE
1784         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1785         instructions by their now designated identifier (since combining i686
1786         and 3DNow! does not really imply 3DNow!A).
1787
1788 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
1789
1790         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1791         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1792
1793 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
1794             Vineet Sharma      <vineets@noida.hcltech.com>
1795
1796         * maxq.h: New file: Disassembly information for the maxq port.
1797
1798 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
1799
1800         * i386.h (i386_optab): Put back "movzb".
1801
1802 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
1803
1804         * cris.h (enum cris_insn_version_usage): Tweak formatting and
1805         comments.  Remove member cris_ver_sim.  Add members
1806         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1807         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1808         (struct cris_support_reg, struct cris_cond15): New types.
1809         (cris_conds15): Declare.
1810         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1811         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1812         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1813         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1814         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1815         SIZE_FIELD_UNSIGNED.
1816
1817 2004-11-04 Jan Beulich  <jbeulich@novell.com>
1818
1819         * i386.h (sldx_Suf): Remove.
1820         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1821         (q_FP): Define, implying no REX64.
1822         (x_FP, sl_FP): Imply FloatMF.
1823         (i386_optab): Split reg and mem forms of moving from segment registers
1824         so that the memory forms can ignore the 16-/32-bit operand size
1825         distinction. Adjust a few others for Intel mode. Remove *FP uses from
1826         all non-floating-point instructions. Unite 32- and 64-bit forms of
1827         movsx, movzx, and movd. Adjust floating point operations for the above
1828         changes to the *FP macros. Add DefaultSize to floating point control
1829         insns operating on larger memory ranges. Remove left over comments
1830         hinting at certain insns being Intel-syntax ones where the ones
1831         actually meant are already gone.
1832
1833 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
1834
1835         * crx.h: Add COPS_REG_INS - Coprocessor Special register
1836         instruction type.
1837
1838 2004-09-30  Paul Brook  <paul@codesourcery.com>
1839
1840         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1841         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1842
1843 2004-09-11  Theodore A. Roth  <troth@openavr.org>
1844
1845         * avr.h: Add support for
1846         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1847
1848 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
1849
1850         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1851
1852 2004-08-24  Dmitry Diky  <diwil@spec.ru>
1853
1854         * msp430.h (msp430_opc): Add new instructions.
1855         (msp430_rcodes): Declare new instructions.
1856         (msp430_hcodes): Likewise..
1857
1858 2004-08-13  Nick Clifton  <nickc@redhat.com>
1859
1860         PR/301
1861         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1862         processors.
1863
1864 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
1865
1866         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1867
1868 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
1869
1870         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1871
1872 2004-07-21  Jan Beulich  <jbeulich@novell.com>
1873
1874         * i386.h: Adjust instruction descriptions to better match the
1875         specification.
1876
1877 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
1878
1879         * arm.h: Remove all old content.  Replace with architecture defines
1880         from gas/config/tc-arm.c.
1881
1882 2004-07-09  Andreas Schwab  <schwab@suse.de>
1883
1884         * m68k.h: Fix comment.
1885
1886 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
1887
1888         * crx.h: New file.
1889
1890 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
1891
1892         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1893
1894 2004-05-24  Peter Barada  <peter@the-baradas.com>
1895
1896         * m68k.h: Add 'size' to m68k_opcode.
1897
1898 2004-05-05  Peter Barada  <peter@the-baradas.com>
1899
1900         * m68k.h: Switch from ColdFire chip name to core variant.
1901
1902 2004-04-22  Peter Barada  <peter@the-baradas.com>
1903
1904         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
1905         descriptions for new EMAC cases.
1906         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1907         handle Motorola MAC syntax.
1908         Allow disassembly of ColdFire V4e object files.
1909
1910 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
1911
1912         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
1913
1914 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
1915
1916         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1917
1918 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1919
1920         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1921
1922 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1923
1924         * i386.h (i386_optab): Added xstore/xcrypt insns.
1925
1926 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1927
1928         * h8300.h (32bit ldc/stc): Add relaxing support.
1929
1930 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
1931
1932         * h8300.h (BITOP): Pass MEMRELAX flag.
1933
1934 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1935
1936         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1937         except for the H8S.
1938
1939 For older changes see ChangeLog-9103
1940 \f
1941 Copyright (C) 2004-2012 Free Software Foundation, Inc.
1942
1943 Copying and distribution of this file, with or without modification,
1944 are permitted in any medium without royalty provided the copyright
1945 notice and this notice are preserved.
1946
1947 Local Variables:
1948 mode: change-log
1949 left-margin: 8
1950 fill-column: 74
1951 version-control: never
1952 End: