include/opcode/ChangeLog

   1 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
   2
   3         * m68k.h (mcfisa_c): New.
   4         (mcfusp, mcf_mask): Adjust.
   5
   6 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
   7
   8         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
   9         (num_powerpc_operands): Declare.
  10         (PPC_OPERAND_SIGNED et al): Redefine as hex.
  11         (PPC_OPERAND_PLUS1): Define.
  12
  13 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
  14
  15         * i386.h (REX_MODE64): Renamed to ...
  16         (REX_W): This.
  17         (REX_EXTX): Renamed to ...
  18         (REX_R): This.
  19         (REX_EXTY): Renamed to ...
  20         (REX_X): This.
  21         (REX_EXTZ): Renamed to ...
  22         (REX_B): This.
  23
  24 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
  25
  26         * i386.h: Add entries from config/tc-i386.h and move tables
  27         to opcodes/i386-opc.h.
  28
  29 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
  30
  31         * i386.h (FloatDR): Removed.
  32         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
  33
  34 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
  35
  36         * spu-insns.h: Add soma double-float insns.
  37
  38 2007-02-20  Thiemo Seufer  <ths@mips.com>
  39             Chao-Ying Fu  <fu@mips.com>
  40
  41         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
  42         (INSN_DSPR2): Add flag for DSP R2 instructions.
  43         (M_BALIGN): New macro.
  44
  45 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
  46
  47         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
  48         and Seg3ShortFrom with Shortform.
  49
  50 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
  51
  52         PR gas/4027
  53         * i386.h (i386_optab): Put the real "test" before the pseudo
  54         one.
  55
  56 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
  57
  58         * m68k.h (m68010up): OR fido_a.
  59
  60 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
  61
  62         * m68k.h (fido_a): New.
  63
  64 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
  65
  66         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
  67         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
  68         values.
  69
  70 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
  71
  72         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
  73
  74 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
  75
  76         * score-inst.h (enum score_insn_type): Add Insn_internal.
  77
  78 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
  79             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
  80             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
  81             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
  82             Alan Modra  <amodra@bigpond.net.au>
  83
  84         * spu-insns.h: New file.
  85         * spu.h: New file.
  86
  87 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
  88
  89         * ppc.h (PPC_OPCODE_CELL): Define.
  90
  91 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
  92
  93         * i386.h :  Modify opcode to support for the change in POPCNT opcode
  94         in amdfam10 architecture.
  95
  96 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
  97
  98         * i386.h: Replace CpuMNI with CpuSSSE3.
  99
 100 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
 101             Joseph Myers  <joseph@codesourcery.com>
 102             Ian Lance Taylor  <ian@wasabisystems.com>
 103             Ben Elliston  <bje@wasabisystems.com>
 104
 105         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
 106
 107 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 108
 109         * score-datadep.h: New file.
 110         * score-inst.h: New file.
 111
 112 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 113
 114         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
 115         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
 116         movdq2q and movq2dq.
 117
 118 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 119            Michael Meissner             <michael.meissner@amd.com>
 120
 121         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
 122
 123 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 124
 125         * i386.h (i386_optab): Add "nop" with memory reference.
 126
 127 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 128
 129         * i386.h (i386_optab): Update comment for 64bit NOP.
 130
 131 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 132             Anton Blanchard  <anton@samba.org>
 133
 134         * ppc.h (PPC_OPCODE_POWER6): Define.
 135         Adjust whitespace.
 136
 137 2006-06-05  Thiemo Seufer  <ths@mips.com>
 138
 139         * mips.h: Improve description of MT flags.
 140
 141 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 142
 143         * m68k.h (mcf_mask): Define.
 144
 145 2006-05-05  Thiemo Seufer  <ths@mips.com>
 146             David Ung  <davidu@mips.com>
 147
 148         * mips.h (enum): Add macro M_CACHE_AB.
 149
 150 2006-05-04  Thiemo Seufer  <ths@mips.com>
 151             Nigel Stephens  <nigel@mips.com>
 152             David Ung  <davidu@mips.com>
 153
 154         * mips.h: Add INSN_SMARTMIPS define.
 155
 156 2006-04-30  Thiemo Seufer  <ths@mips.com>
 157             David Ung  <davidu@mips.com>
 158
 159         * mips.h: Defines udi bits and masks.  Add description of
 160         characters which may appear in the args field of udi
 161         instructions.
 162
 163 2006-04-26  Thiemo Seufer  <ths@networkno.de>
 164
 165         * mips.h: Improve comments describing the bitfield instruction
 166         fields.
 167
 168 2006-04-26  Julian Brown  <julian@codesourcery.com>
 169
 170         * arm.h (FPU_VFP_EXT_V3): Define constant.
 171         (FPU_NEON_EXT_V1): Likewise.
 172         (FPU_VFP_HARD): Update.
 173         (FPU_VFP_V3): Define macro.
 174         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 175
 176 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 177
 178         * avr.h (AVR_ISA_PWMx): New.
 179
 180 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 181
 182         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 183         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 184         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 185         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 186         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 187
 188 2006-03-10  Paul Brook  <paul@codesourcery.com>
 189
 190         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 191
 192 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 193
 194         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 195         first.  Correct mask of bb "B" opcode.
 196
 197 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 198
 199         * i386.h (i386_optab): Support Intel Merom New Instructions.
 200
 201 2006-02-24  Paul Brook  <paul@codesourcery.com>
 202
 203         * arm.h: Add V7 feature bits.
 204
 205 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 206
 207         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 208
 209 2006-01-31  Paul Brook  <paul@codesourcery.com>
 210         Richard Earnshaw <rearnsha@arm.com>
 211
 212         * arm.h: Use ARM_CPU_FEATURE.
 213         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 214         (arm_feature_set): Change to a structure.
 215         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 216         ARM_FEATURE): New macros.
 217
 218 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 219
 220         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 221         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 222         (ADD_PC_INCR_OPCODE): Don't define.
 223
 224 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 225
 226         PR gas/1874
 227         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 228
 229 2005-11-14  David Ung  <davidu@mips.com>
 230
 231         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 232         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 233         save/restore encoding of the args field.
 234
 235 2005-10-28  Dave Brolley  <brolley@redhat.com>
 236
 237         Contribute the following changes:
 238         2005-02-16  Dave Brolley  <brolley@redhat.com>
 239
 240         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 241         cgen_isa_mask_* to cgen_bitset_*.
 242         * cgen.h: Likewise.
 243
 244         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 245
 246         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 247         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 248         (CGEN_CPU_TABLE): Make isas a ponter.
 249
 250         2003-09-29  Dave Brolley  <brolley@redhat.com>
 251
 252         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 253         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 254         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 255
 256         2002-12-13  Dave Brolley  <brolley@redhat.com>
 257
 258         * cgen.h (symcat.h): #include it.
 259         (cgen-bitset.h): #include it.
 260         (CGEN_ATTR_VALUE_TYPE): Now a union.
 261         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 262         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 263         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 264         * cgen-bitset.h: New file.
 265
 266 2005-09-30  Catherine Moore  <clm@cm00re.com>
 267
 268         * bfin.h: New file.
 269
 270 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 271
 272         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 273         indirect operands.
 274
 275 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 276
 277         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 278         Add FLAG_STRICT to pa10 ftest opcode.
 279
 280 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 281
 282         * hppa.h (pa_opcodes): Remove lha entries.
 283
 284 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 285
 286         * hppa.h (FLAG_STRICT): Revise comment.
 287         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 288         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 289         entries for "fdc".
 290
 291 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 292
 293         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 294
 295 2005-09-06  Chao-ying Fu  <fu@mips.com>
 296
 297         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 298         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 299         define.
 300         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 301         (INSN_ASE_MASK): Update to include INSN_MT.
 302         (INSN_MT): New define for MT ASE.
 303
 304 2005-08-25  Chao-ying Fu  <fu@mips.com>
 305
 306         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 307         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 308         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 309         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 310         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 311         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 312         instructions.
 313         (INSN_DSP): New define for DSP ASE.
 314
 315 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 316
 317         * a29k.h: Delete.
 318
 319 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 320
 321         * ppc.h (PPC_OPCODE_E300): Define.
 322
 323 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 324
 325         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 326
 327 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 328
 329         PR gas/336
 330         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 331         and pitlb.
 332
 333 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 334
 335         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 336         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 337         Add movq-s as 64-bit variants of movd-s.
 338
 339 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 340
 341         * hppa.h: Fix punctuation in comment.
 342
 343         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 344         implicit space-register addressing.  Set space-register bits on opcodes
 345         using implicit space-register addressing.  Add various missing pa20
 346         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 347         space-register addressing.  Use "fE" instead of "fe" in various
 348         fstw opcodes.
 349
 350 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 351
 352         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 353
 354 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 355
 356         * i386.h (i386_optab): Support Intel VMX Instructions.
 357
 358 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 359
 360         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 361
 362 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 363
 364         * i386.h (i386_optab): Add new insns.
 365
 366 2005-07-01  Nick Clifton  <nickc@redhat.com>
 367
 368         * sparc.h: Add typedefs to structure declarations.
 369
 370 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 371
 372         PR 1013
 373         * i386.h (i386_optab): Update comments for 64bit addressing on
 374         mov. Allow 64bit addressing for mov and movq.
 375
 376 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 377
 378         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 379         respectively, in various floating-point load and store patterns.
 380
 381 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 382
 383         * hppa.h (FLAG_STRICT): Correct comment.
 384         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 385         PA 2.0 mneumonics when equivalent.  Entries with cache control
 386         completers now require PA 1.1.  Adjust whitespace.
 387
 388 2005-05-19  Anton Blanchard  <anton@samba.org>
 389
 390         * ppc.h (PPC_OPCODE_POWER5): Define.
 391
 392 2005-05-10  Nick Clifton  <nickc@redhat.com>
 393
 394         * Update the address and phone number of the FSF organization in
 395         the GPL notices in the following files:
 396         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 397         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 398         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 399         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 400         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 401         tic54x.h, tic80.h, v850.h, vax.h
 402
 403 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 404
 405         * i386.h (i386_optab): Add ht and hnt.
 406
 407 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 408
 409         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 410         Add xcrypt-ctr.  Provide aliases without hyphens.
 411
 412 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 413
 414         Moved from ../ChangeLog
 415
 416         2005-04-12  Paul Brook  <paul@codesourcery.com>
 417         * m88k.h: Rename psr macros to avoid conflicts.
 418
 419         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 420         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 421         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 422         and ARM_ARCH_V6ZKT2.
 423
 424         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 425         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 426         Remove redundant instruction types.
 427         (struct argument): X_op - new field.
 428         (struct cst4_entry): Remove.
 429         (no_op_insn): Declare.
 430
 431         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 432         * crx.h (enum argtype): Rename types, remove unused types.
 433
 434         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 435         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 436         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 437         (enum operand_type): Rearrange operands, edit comments.
 438         replace us<N> with ui<N> for unsigned immediate.
 439         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 440         displacements (respectively).
 441         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 442         (instruction type): Add NO_TYPE_INS.
 443         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 444         (operand_entry): New field - 'flags'.
 445         (operand flags): New.
 446
 447         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 448         * crx.h (operand_type): Remove redundant types i3, i4,
 449         i5, i8, i12.
 450         Add new unsigned immediate types us3, us4, us5, us16.
 451
 452 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 453
 454         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 455         adjust them accordingly.
 456
 457 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 458
 459         * i386.h (i386_optab): Add rdtscp.
 460
 461 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 462
 463         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 464         between memory and segment register. Allow movq for moving between
 465         general-purpose register and segment register.
 466
 467 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 468
 469         PR gas/707
 470         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 471         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 472         fnstsw.
 473
 474 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 475
 476         * m68k.h (m68008, m68ec030, m68882): Remove.
 477         (m68k_mask): New.
 478         (cpu_m68k, cpu_cf): New.
 479         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 480         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 481
 482 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 483
 484         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 485         * cgen.h (enum cgen_parse_operand_type): Add
 486         CGEN_PARSE_OPERAND_SYMBOLIC.
 487
 488 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 489
 490         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 491         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 492         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 493
 494 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 495
 496         * mips.h (struct mips_opcode): Add new pinfo2 member.
 497         (INSN_ALIAS): New define for opcode table entries that are
 498         specific instances of another entry, such as 'move' for an 'or'
 499         with a zero operand.
 500         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 501         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 502
 503 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 504
 505         * mips.h (CPU_RM9000): Define.
 506         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 507
 508 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 509
 510         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 511         to/from test registers are illegal in 64-bit mode. Add missing
 512         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 513         (previously one had to explicitly encode a rex64 prefix). Re-enable
 514         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 515         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 516
 517 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 518
 519         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 520         available only with SSE2. Change the MMX additions introduced by SSE
 521         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 522         instructions by their now designated identifier (since combining i686
 523         and 3DNow! does not really imply 3DNow!A).
 524
 525 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 526
 527         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 528         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 529
 530 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 531             Vineet Sharma      <vineets@noida.hcltech.com>
 532
 533         * maxq.h: New file: Disassembly information for the maxq port.
 534
 535 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 536
 537         * i386.h (i386_optab): Put back "movzb".
 538
 539 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 540
 541         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 542         comments.  Remove member cris_ver_sim.  Add members
 543         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 544         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 545         (struct cris_support_reg, struct cris_cond15): New types.
 546         (cris_conds15): Declare.
 547         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 548         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 549         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 550         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 551         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 552         SIZE_FIELD_UNSIGNED.
 553
 554 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 555
 556         * i386.h (sldx_Suf): Remove.
 557         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 558         (q_FP): Define, implying no REX64.
 559         (x_FP, sl_FP): Imply FloatMF.
 560         (i386_optab): Split reg and mem forms of moving from segment registers
 561         so that the memory forms can ignore the 16-/32-bit operand size
 562         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 563         all non-floating-point instructions. Unite 32- and 64-bit forms of
 564         movsx, movzx, and movd. Adjust floating point operations for the above
 565         changes to the *FP macros. Add DefaultSize to floating point control
 566         insns operating on larger memory ranges. Remove left over comments
 567         hinting at certain insns being Intel-syntax ones where the ones
 568         actually meant are already gone.
 569
 570 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 571
 572         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 573         instruction type.
 574
 575 2004-09-30  Paul Brook  <paul@codesourcery.com>
 576
 577         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 578         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 579
 580 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 581
 582         * avr.h: Add support for
 583         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 584
 585 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 586
 587         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 588
 589 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 590
 591         * msp430.h (msp430_opc): Add new instructions.
 592         (msp430_rcodes): Declare new instructions.
 593         (msp430_hcodes): Likewise..
 594
 595 2004-08-13  Nick Clifton  <nickc@redhat.com>
 596
 597         PR/301
 598         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 599         processors.
 600
 601 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 602
 603         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 604
 605 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 606
 607         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 608
 609 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 610
 611         * i386.h: Adjust instruction descriptions to better match the
 612         specification.
 613
 614 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 615
 616         * arm.h: Remove all old content.  Replace with architecture defines
 617         from gas/config/tc-arm.c.
 618
 619 2004-07-09  Andreas Schwab  <schwab@suse.de>
 620
 621         * m68k.h: Fix comment.
 622
 623 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 624
 625         * crx.h: New file.
 626
 627 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 628
 629         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 630
 631 2004-05-24  Peter Barada  <peter@the-baradas.com>
 632
 633         * m68k.h: Add 'size' to m68k_opcode.
 634
 635 2004-05-05  Peter Barada  <peter@the-baradas.com>
 636
 637         * m68k.h: Switch from ColdFire chip name to core variant.
 638
 639 2004-04-22  Peter Barada  <peter@the-baradas.com>
 640
 641         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 642         descriptions for new EMAC cases.
 643         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 644         handle Motorola MAC syntax.
 645         Allow disassembly of ColdFire V4e object files.
 646
 647 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 648
 649         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 650
 651 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 652
 653         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 654
 655 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 656
 657         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 658
 659 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 660
 661         * i386.h (i386_optab): Added xstore/xcrypt insns.
 662
 663 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 664
 665         * h8300.h (32bit ldc/stc): Add relaxing support.
 666
 667 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 668
 669         * h8300.h (BITOP): Pass MEMRELAX flag.
 670
 671 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 672
 673         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 674         except for the H8S.
 675
 676 For older changes see ChangeLog-9103
 677 \f
 678 Local Variables:
 679 mode: change-log
 680 left-margin: 8
 681 fill-column: 74
 682 version-control: never
 683 End: