include/opcode/ChangeLog

   1 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
   4
   5 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
   6
   7         * score-inst.h (enum score_insn_type): Add Insn_internal.
   8
   9 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
  10
  11         * score-inst.h (enum score_insn_type): Add Insn_internal.
  12
  13 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
  14             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
  15             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
  16             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
  17             Alan Modra  <amodra@bigpond.net.au>
  18
  19         * spu-insns.h: New file.
  20         * spu.h: New file.
  21
  22 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
  23
  24         * ppc.h (PPC_OPCODE_CELL): Define.
  25
  26 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
  27
  28         * i386.h :  Modify opcode to support for the change in POPCNT opcode
  29         in amdfam10 architecture.
  30
  31 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
  32
  33         * i386.h: Replace CpuMNI with CpuSSSE3.
  34
  35 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
  36             Joseph Myers  <joseph@codesourcery.com>
  37             Ian Lance Taylor  <ian@wasabisystems.com>
  38             Ben Elliston  <bje@wasabisystems.com>
  39
  40         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
  41
  42 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
  43
  44         * score-datadep.h: New file.
  45         * score-inst.h: New file.
  46
  47 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
  48
  49         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
  50         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
  51         movdq2q and movq2dq.
  52
  53 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
  54            Michael Meissner             <michael.meissner@amd.com>
  55
  56         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
  57
  58 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
  59
  60         * i386.h (i386_optab): Add "nop" with memory reference.
  61
  62 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
  63
  64         * i386.h (i386_optab): Update comment for 64bit NOP.
  65
  66 2006-06-06  Ben Elliston  <bje@au.ibm.com>
  67             Anton Blanchard  <anton@samba.org>
  68
  69         * ppc.h (PPC_OPCODE_POWER6): Define.
  70         Adjust whitespace.
  71
  72 2006-06-05  Thiemo Seufer  <ths@mips.com>
  73
  74         * mips.h: Improve description of MT flags.
  75
  76 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
  77
  78         * m68k.h (mcf_mask): Define.
  79
  80 2006-05-05  Thiemo Seufer  <ths@mips.com>
  81             David Ung  <davidu@mips.com>
  82
  83         * mips.h (enum): Add macro M_CACHE_AB.
  84
  85 2006-05-04  Thiemo Seufer  <ths@mips.com>
  86             Nigel Stephens  <nigel@mips.com>
  87             David Ung  <davidu@mips.com>
  88
  89         * mips.h: Add INSN_SMARTMIPS define.
  90
  91 2006-04-30  Thiemo Seufer  <ths@mips.com>
  92             David Ung  <davidu@mips.com>
  93
  94         * mips.h: Defines udi bits and masks.  Add description of
  95         characters which may appear in the args field of udi
  96         instructions.
  97
  98 2006-04-26  Thiemo Seufer  <ths@networkno.de>
  99
 100         * mips.h: Improve comments describing the bitfield instruction
 101         fields.
 102
 103 2006-04-26  Julian Brown  <julian@codesourcery.com>
 104
 105         * arm.h (FPU_VFP_EXT_V3): Define constant.
 106         (FPU_NEON_EXT_V1): Likewise.
 107         (FPU_VFP_HARD): Update.
 108         (FPU_VFP_V3): Define macro.
 109         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 110
 111 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 112
 113         * avr.h (AVR_ISA_PWMx): New.
 114
 115 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 116
 117         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 118         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 119         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 120         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 121         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 122
 123 2006-03-10  Paul Brook  <paul@codesourcery.com>
 124
 125         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 126
 127 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 128
 129         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 130         first.  Correct mask of bb "B" opcode.
 131
 132 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 133
 134         * i386.h (i386_optab): Support Intel Merom New Instructions.
 135
 136 2006-02-24  Paul Brook  <paul@codesourcery.com>
 137
 138         * arm.h: Add V7 feature bits.
 139
 140 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 141
 142         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 143
 144 2006-01-31  Paul Brook  <paul@codesourcery.com>
 145         Richard Earnshaw <rearnsha@arm.com>
 146
 147         * arm.h: Use ARM_CPU_FEATURE.
 148         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 149         (arm_feature_set): Change to a structure.
 150         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 151         ARM_FEATURE): New macros.
 152
 153 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 154
 155         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 156         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 157         (ADD_PC_INCR_OPCODE): Don't define.
 158
 159 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 160
 161         PR gas/1874
 162         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 163
 164 2005-11-14  David Ung  <davidu@mips.com>
 165
 166         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 167         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 168         save/restore encoding of the args field.
 169
 170 2005-10-28  Dave Brolley  <brolley@redhat.com>
 171
 172         Contribute the following changes:
 173         2005-02-16  Dave Brolley  <brolley@redhat.com>
 174
 175         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 176         cgen_isa_mask_* to cgen_bitset_*.
 177         * cgen.h: Likewise.
 178
 179         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 180
 181         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 182         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 183         (CGEN_CPU_TABLE): Make isas a ponter.
 184
 185         2003-09-29  Dave Brolley  <brolley@redhat.com>
 186
 187         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 188         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 189         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 190
 191         2002-12-13  Dave Brolley  <brolley@redhat.com>
 192
 193         * cgen.h (symcat.h): #include it.
 194         (cgen-bitset.h): #include it.
 195         (CGEN_ATTR_VALUE_TYPE): Now a union.
 196         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 197         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 198         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 199         * cgen-bitset.h: New file.
 200
 201 2005-09-30  Catherine Moore  <clm@cm00re.com>
 202
 203         * bfin.h: New file.
 204
 205 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 206
 207         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 208         indirect operands.
 209
 210 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 211
 212         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 213         Add FLAG_STRICT to pa10 ftest opcode.
 214
 215 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 216
 217         * hppa.h (pa_opcodes): Remove lha entries.
 218
 219 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 220
 221         * hppa.h (FLAG_STRICT): Revise comment.
 222         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 223         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 224         entries for "fdc".
 225
 226 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 227
 228         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 229
 230 2005-09-06  Chao-ying Fu  <fu@mips.com>
 231
 232         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 233         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 234         define.
 235         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 236         (INSN_ASE_MASK): Update to include INSN_MT.
 237         (INSN_MT): New define for MT ASE.
 238
 239 2005-08-25  Chao-ying Fu  <fu@mips.com>
 240
 241         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 242         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 243         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 244         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 245         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 246         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 247         instructions.
 248         (INSN_DSP): New define for DSP ASE.
 249
 250 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 251
 252         * a29k.h: Delete.
 253
 254 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 255
 256         * ppc.h (PPC_OPCODE_E300): Define.
 257
 258 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 259
 260         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 261
 262 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 263
 264         PR gas/336
 265         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 266         and pitlb.
 267
 268 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 269
 270         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 271         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 272         Add movq-s as 64-bit variants of movd-s.
 273
 274 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 275
 276         * hppa.h: Fix punctuation in comment.
 277
 278         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 279         implicit space-register addressing.  Set space-register bits on opcodes
 280         using implicit space-register addressing.  Add various missing pa20
 281         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 282         space-register addressing.  Use "fE" instead of "fe" in various
 283         fstw opcodes.
 284
 285 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 286
 287         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 288
 289 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 290
 291         * i386.h (i386_optab): Support Intel VMX Instructions.
 292
 293 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 294
 295         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 296
 297 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 298
 299         * i386.h (i386_optab): Add new insns.
 300
 301 2005-07-01  Nick Clifton  <nickc@redhat.com>
 302
 303         * sparc.h: Add typedefs to structure declarations.
 304
 305 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 306
 307         PR 1013
 308         * i386.h (i386_optab): Update comments for 64bit addressing on
 309         mov. Allow 64bit addressing for mov and movq.
 310
 311 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 312
 313         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 314         respectively, in various floating-point load and store patterns.
 315
 316 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 317
 318         * hppa.h (FLAG_STRICT): Correct comment.
 319         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 320         PA 2.0 mneumonics when equivalent.  Entries with cache control
 321         completers now require PA 1.1.  Adjust whitespace.
 322
 323 2005-05-19  Anton Blanchard  <anton@samba.org>
 324
 325         * ppc.h (PPC_OPCODE_POWER5): Define.
 326
 327 2005-05-10  Nick Clifton  <nickc@redhat.com>
 328
 329         * Update the address and phone number of the FSF organization in
 330         the GPL notices in the following files:
 331         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 332         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 333         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 334         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 335         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 336         tic54x.h, tic80.h, v850.h, vax.h
 337
 338 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 339
 340         * i386.h (i386_optab): Add ht and hnt.
 341
 342 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 343
 344         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 345         Add xcrypt-ctr.  Provide aliases without hyphens.
 346
 347 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 348
 349         Moved from ../ChangeLog
 350
 351         2005-04-12  Paul Brook  <paul@codesourcery.com>
 352         * m88k.h: Rename psr macros to avoid conflicts.
 353
 354         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 355         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 356         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 357         and ARM_ARCH_V6ZKT2.
 358
 359         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 360         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 361         Remove redundant instruction types.
 362         (struct argument): X_op - new field.
 363         (struct cst4_entry): Remove.
 364         (no_op_insn): Declare.
 365
 366         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 367         * crx.h (enum argtype): Rename types, remove unused types.
 368
 369         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 370         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 371         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 372         (enum operand_type): Rearrange operands, edit comments.
 373         replace us<N> with ui<N> for unsigned immediate.
 374         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 375         displacements (respectively).
 376         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 377         (instruction type): Add NO_TYPE_INS.
 378         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 379         (operand_entry): New field - 'flags'.
 380         (operand flags): New.
 381
 382         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 383         * crx.h (operand_type): Remove redundant types i3, i4,
 384         i5, i8, i12.
 385         Add new unsigned immediate types us3, us4, us5, us16.
 386
 387 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 388
 389         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 390         adjust them accordingly.
 391
 392 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 393
 394         * i386.h (i386_optab): Add rdtscp.
 395
 396 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 397
 398         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 399         between memory and segment register. Allow movq for moving between
 400         general-purpose register and segment register.
 401
 402 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 403
 404         PR gas/707
 405         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 406         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 407         fnstsw.
 408
 409 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 410
 411         * m68k.h (m68008, m68ec030, m68882): Remove.
 412         (m68k_mask): New.
 413         (cpu_m68k, cpu_cf): New.
 414         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 415         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 416
 417 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 418
 419         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 420         * cgen.h (enum cgen_parse_operand_type): Add
 421         CGEN_PARSE_OPERAND_SYMBOLIC.
 422
 423 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 424
 425         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 426         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 427         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 428
 429 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 430
 431         * mips.h (struct mips_opcode): Add new pinfo2 member.
 432         (INSN_ALIAS): New define for opcode table entries that are
 433         specific instances of another entry, such as 'move' for an 'or'
 434         with a zero operand.
 435         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 436         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 437
 438 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 439
 440         * mips.h (CPU_RM9000): Define.
 441         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 442
 443 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 444
 445         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 446         to/from test registers are illegal in 64-bit mode. Add missing
 447         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 448         (previously one had to explicitly encode a rex64 prefix). Re-enable
 449         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 450         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 451
 452 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 453
 454         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 455         available only with SSE2. Change the MMX additions introduced by SSE
 456         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 457         instructions by their now designated identifier (since combining i686
 458         and 3DNow! does not really imply 3DNow!A).
 459
 460 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 461
 462         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 463         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 464
 465 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 466             Vineet Sharma      <vineets@noida.hcltech.com>
 467
 468         * maxq.h: New file: Disassembly information for the maxq port.
 469
 470 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 471
 472         * i386.h (i386_optab): Put back "movzb".
 473
 474 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 475
 476         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 477         comments.  Remove member cris_ver_sim.  Add members
 478         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 479         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 480         (struct cris_support_reg, struct cris_cond15): New types.
 481         (cris_conds15): Declare.
 482         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 483         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 484         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 485         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 486         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 487         SIZE_FIELD_UNSIGNED.
 488
 489 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 490
 491         * i386.h (sldx_Suf): Remove.
 492         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 493         (q_FP): Define, implying no REX64.
 494         (x_FP, sl_FP): Imply FloatMF.
 495         (i386_optab): Split reg and mem forms of moving from segment registers
 496         so that the memory forms can ignore the 16-/32-bit operand size
 497         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 498         all non-floating-point instructions. Unite 32- and 64-bit forms of
 499         movsx, movzx, and movd. Adjust floating point operations for the above
 500         changes to the *FP macros. Add DefaultSize to floating point control
 501         insns operating on larger memory ranges. Remove left over comments
 502         hinting at certain insns being Intel-syntax ones where the ones
 503         actually meant are already gone.
 504
 505 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 506
 507         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 508         instruction type.
 509
 510 2004-09-30  Paul Brook  <paul@codesourcery.com>
 511
 512         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 513         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 514
 515 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 516
 517         * avr.h: Add support for
 518         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 519
 520 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 521
 522         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 523
 524 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 525
 526         * msp430.h (msp430_opc): Add new instructions.
 527         (msp430_rcodes): Declare new instructions.
 528         (msp430_hcodes): Likewise..
 529
 530 2004-08-13  Nick Clifton  <nickc@redhat.com>
 531
 532         PR/301
 533         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 534         processors.
 535
 536 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 537
 538         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 539
 540 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 541
 542         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 543
 544 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 545
 546         * i386.h: Adjust instruction descriptions to better match the
 547         specification.
 548
 549 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 550
 551         * arm.h: Remove all old content.  Replace with architecture defines
 552         from gas/config/tc-arm.c.
 553
 554 2004-07-09  Andreas Schwab  <schwab@suse.de>
 555
 556         * m68k.h: Fix comment.
 557
 558 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 559
 560         * crx.h: New file.
 561
 562 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 563
 564         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 565
 566 2004-05-24  Peter Barada  <peter@the-baradas.com>
 567
 568         * m68k.h: Add 'size' to m68k_opcode.
 569
 570 2004-05-05  Peter Barada  <peter@the-baradas.com>
 571
 572         * m68k.h: Switch from ColdFire chip name to core variant.
 573
 574 2004-04-22  Peter Barada  <peter@the-baradas.com>
 575
 576         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 577         descriptions for new EMAC cases.
 578         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 579         handle Motorola MAC syntax.
 580         Allow disassembly of ColdFire V4e object files.
 581
 582 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 583
 584         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 585
 586 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 587
 588         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 589
 590 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 591
 592         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 593
 594 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 595
 596         * i386.h (i386_optab): Added xstore/xcrypt insns.
 597
 598 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 599
 600         * h8300.h (32bit ldc/stc): Add relaxing support.
 601
 602 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 603
 604         * h8300.h (BITOP): Pass MEMRELAX flag.
 605
 606 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 607
 608         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 609         except for the H8S.
 610
 611 For older changes see ChangeLog-9103
 612 \f
 613 Local Variables:
 614 mode: change-log
 615 left-margin: 8
 616 fill-column: 74
 617 version-control: never
 618 End:
 619 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
 620             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
 621             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
 622             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
 623             Alan Modra  <amodra@bigpond.net.au>
 624
 625         * spu-insns.h: New file.
 626         * spu.h: New file.
 627
 628 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
 629
 630         * ppc.h (PPC_OPCODE_CELL): Define.
 631
 632 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 633
 634         * i386.h :  Modify opcode to support for the change in POPCNT opcode
 635         in amdfam10 architecture.
 636
 637 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
 638
 639         * i386.h: Replace CpuMNI with CpuSSSE3.
 640
 641 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
 642             Joseph Myers  <joseph@codesourcery.com>
 643             Ian Lance Taylor  <ian@wasabisystems.com>
 644             Ben Elliston  <bje@wasabisystems.com>
 645
 646         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
 647
 648 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 649
 650         * score-datadep.h: New file.
 651         * score-inst.h: New file.
 652
 653 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 654
 655         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
 656         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
 657         movdq2q and movq2dq.
 658
 659 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 660            Michael Meissner             <michael.meissner@amd.com>
 661
 662         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
 663
 664 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 665
 666         * i386.h (i386_optab): Add "nop" with memory reference.
 667
 668 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 669
 670         * i386.h (i386_optab): Update comment for 64bit NOP.
 671
 672 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 673             Anton Blanchard  <anton@samba.org>
 674
 675         * ppc.h (PPC_OPCODE_POWER6): Define.
 676         Adjust whitespace.
 677
 678 2006-06-05  Thiemo Seufer  <ths@mips.com>
 679
 680         * mips.h: Improve description of MT flags.
 681
 682 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 683
 684         * m68k.h (mcf_mask): Define.
 685
 686 2006-05-05  Thiemo Seufer  <ths@mips.com>
 687             David Ung  <davidu@mips.com>
 688
 689         * mips.h (enum): Add macro M_CACHE_AB.
 690
 691 2006-05-04  Thiemo Seufer  <ths@mips.com>
 692             Nigel Stephens  <nigel@mips.com>
 693             David Ung  <davidu@mips.com>
 694
 695         * mips.h: Add INSN_SMARTMIPS define.
 696
 697 2006-04-30  Thiemo Seufer  <ths@mips.com>
 698             David Ung  <davidu@mips.com>
 699
 700         * mips.h: Defines udi bits and masks.  Add description of
 701         characters which may appear in the args field of udi
 702         instructions.
 703
 704 2006-04-26  Thiemo Seufer  <ths@networkno.de>
 705
 706         * mips.h: Improve comments describing the bitfield instruction
 707         fields.
 708
 709 2006-04-26  Julian Brown  <julian@codesourcery.com>
 710
 711         * arm.h (FPU_VFP_EXT_V3): Define constant.
 712         (FPU_NEON_EXT_V1): Likewise.
 713         (FPU_VFP_HARD): Update.
 714         (FPU_VFP_V3): Define macro.
 715         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 716
 717 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 718
 719         * avr.h (AVR_ISA_PWMx): New.
 720
 721 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 722
 723         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 724         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 725         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 726         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 727         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 728
 729 2006-03-10  Paul Brook  <paul@codesourcery.com>
 730
 731         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 732
 733 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 734
 735         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 736         first.  Correct mask of bb "B" opcode.
 737
 738 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 739
 740         * i386.h (i386_optab): Support Intel Merom New Instructions.
 741
 742 2006-02-24  Paul Brook  <paul@codesourcery.com>
 743
 744         * arm.h: Add V7 feature bits.
 745
 746 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 747
 748         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 749
 750 2006-01-31  Paul Brook  <paul@codesourcery.com>
 751         Richard Earnshaw <rearnsha@arm.com>
 752
 753         * arm.h: Use ARM_CPU_FEATURE.
 754         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 755         (arm_feature_set): Change to a structure.
 756         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 757         ARM_FEATURE): New macros.
 758
 759 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 760
 761         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 762         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 763         (ADD_PC_INCR_OPCODE): Don't define.
 764
 765 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 766
 767         PR gas/1874
 768         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 769
 770 2005-11-14  David Ung  <davidu@mips.com>
 771
 772         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 773         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 774         save/restore encoding of the args field.
 775
 776 2005-10-28  Dave Brolley  <brolley@redhat.com>
 777
 778         Contribute the following changes:
 779         2005-02-16  Dave Brolley  <brolley@redhat.com>
 780
 781         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 782         cgen_isa_mask_* to cgen_bitset_*.
 783         * cgen.h: Likewise.
 784
 785         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 786
 787         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 788         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 789         (CGEN_CPU_TABLE): Make isas a ponter.
 790
 791         2003-09-29  Dave Brolley  <brolley@redhat.com>
 792
 793         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 794         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 795         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 796
 797         2002-12-13  Dave Brolley  <brolley@redhat.com>
 798
 799         * cgen.h (symcat.h): #include it.
 800         (cgen-bitset.h): #include it.
 801         (CGEN_ATTR_VALUE_TYPE): Now a union.
 802         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 803         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 804         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 805         * cgen-bitset.h: New file.
 806
 807 2005-09-30  Catherine Moore  <clm@cm00re.com>
 808
 809         * bfin.h: New file.
 810
 811 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 812
 813         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 814         indirect operands.
 815
 816 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 817
 818         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 819         Add FLAG_STRICT to pa10 ftest opcode.
 820
 821 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 822
 823         * hppa.h (pa_opcodes): Remove lha entries.
 824
 825 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 826
 827         * hppa.h (FLAG_STRICT): Revise comment.
 828         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 829         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 830         entries for "fdc".
 831
 832 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 833
 834         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 835
 836 2005-09-06  Chao-ying Fu  <fu@mips.com>
 837
 838         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 839         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 840         define.
 841         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 842         (INSN_ASE_MASK): Update to include INSN_MT.
 843         (INSN_MT): New define for MT ASE.
 844
 845 2005-08-25  Chao-ying Fu  <fu@mips.com>
 846
 847         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 848         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 849         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 850         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 851         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 852         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 853         instructions.
 854         (INSN_DSP): New define for DSP ASE.
 855
 856 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 857
 858         * a29k.h: Delete.
 859
 860 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 861
 862         * ppc.h (PPC_OPCODE_E300): Define.
 863
 864 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 865
 866         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 867
 868 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 869
 870         PR gas/336
 871         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 872         and pitlb.
 873
 874 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 875
 876         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 877         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 878         Add movq-s as 64-bit variants of movd-s.
 879
 880 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 881
 882         * hppa.h: Fix punctuation in comment.
 883
 884         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 885         implicit space-register addressing.  Set space-register bits on opcodes
 886         using implicit space-register addressing.  Add various missing pa20
 887         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 888         space-register addressing.  Use "fE" instead of "fe" in various
 889         fstw opcodes.
 890
 891 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 892
 893         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 894
 895 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 896
 897         * i386.h (i386_optab): Support Intel VMX Instructions.
 898
 899 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 900
 901         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 902
 903 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 904
 905         * i386.h (i386_optab): Add new insns.
 906
 907 2005-07-01  Nick Clifton  <nickc@redhat.com>
 908
 909         * sparc.h: Add typedefs to structure declarations.
 910
 911 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 912
 913         PR 1013
 914         * i386.h (i386_optab): Update comments for 64bit addressing on
 915         mov. Allow 64bit addressing for mov and movq.
 916
 917 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 918
 919         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 920         respectively, in various floating-point load and store patterns.
 921
 922 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 923
 924         * hppa.h (FLAG_STRICT): Correct comment.
 925         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 926         PA 2.0 mneumonics when equivalent.  Entries with cache control
 927         completers now require PA 1.1.  Adjust whitespace.
 928
 929 2005-05-19  Anton Blanchard  <anton@samba.org>
 930
 931         * ppc.h (PPC_OPCODE_POWER5): Define.
 932
 933 2005-05-10  Nick Clifton  <nickc@redhat.com>
 934
 935         * Update the address and phone number of the FSF organization in
 936         the GPL notices in the following files:
 937         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 938         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 939         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 940         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 941         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 942         tic54x.h, tic80.h, v850.h, vax.h
 943
 944 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 945
 946         * i386.h (i386_optab): Add ht and hnt.
 947
 948 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 949
 950         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 951         Add xcrypt-ctr.  Provide aliases without hyphens.
 952
 953 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 954
 955         Moved from ../ChangeLog
 956
 957         2005-04-12  Paul Brook  <paul@codesourcery.com>
 958         * m88k.h: Rename psr macros to avoid conflicts.
 959
 960         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 961         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 962         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 963         and ARM_ARCH_V6ZKT2.
 964
 965         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 966         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 967         Remove redundant instruction types.
 968         (struct argument): X_op - new field.
 969         (struct cst4_entry): Remove.
 970         (no_op_insn): Declare.
 971
 972         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 973         * crx.h (enum argtype): Rename types, remove unused types.
 974
 975         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 976         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 977         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 978         (enum operand_type): Rearrange operands, edit comments.
 979         replace us<N> with ui<N> for unsigned immediate.
 980         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 981         displacements (respectively).
 982         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 983         (instruction type): Add NO_TYPE_INS.
 984         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 985         (operand_entry): New field - 'flags'.
 986         (operand flags): New.
 987
 988         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 989         * crx.h (operand_type): Remove redundant types i3, i4,
 990         i5, i8, i12.
 991         Add new unsigned immediate types us3, us4, us5, us16.
 992
 993 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 994
 995         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 996         adjust them accordingly.
 997
 998 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 999
1000         * i386.h (i386_optab): Add rdtscp.
1001
1002 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
1003
1004         * i386.h (i386_optab): Don't allow the `l' suffix for moving
1005         between memory and segment register. Allow movq for moving between
1006         general-purpose register and segment register.
1007
1008 2005-02-09  Jan Beulich  <jbeulich@novell.com>
1009
1010         PR gas/707
1011         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1012         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1013         fnstsw.
1014
1015 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
1016
1017         * m68k.h (m68008, m68ec030, m68882): Remove.
1018         (m68k_mask): New.
1019         (cpu_m68k, cpu_cf): New.
1020         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1021         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1022
1023 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
1024
1025         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
1026         * cgen.h (enum cgen_parse_operand_type): Add
1027         CGEN_PARSE_OPERAND_SYMBOLIC.
1028
1029 2005-01-21  Fred Fish  <fnf@specifixinc.com>
1030
1031         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1032         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1033         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1034
1035 2005-01-19  Fred Fish  <fnf@specifixinc.com>
1036
1037         * mips.h (struct mips_opcode): Add new pinfo2 member.
1038         (INSN_ALIAS): New define for opcode table entries that are
1039         specific instances of another entry, such as 'move' for an 'or'
1040         with a zero operand.
1041         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1042         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1043
1044 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
1045
1046         * mips.h (CPU_RM9000): Define.
1047         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1048
1049 2004-11-25 Jan Beulich  <jbeulich@novell.com>
1050
1051         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1052         to/from test registers are illegal in 64-bit mode. Add missing
1053         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1054         (previously one had to explicitly encode a rex64 prefix). Re-enable
1055         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1056         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1057
1058 2004-11-23 Jan Beulich  <jbeulich@novell.com>
1059
1060         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1061         available only with SSE2. Change the MMX additions introduced by SSE
1062         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1063         instructions by their now designated identifier (since combining i686
1064         and 3DNow! does not really imply 3DNow!A).
1065
1066 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
1067
1068         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1069         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1070
1071 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
1072             Vineet Sharma      <vineets@noida.hcltech.com>
1073
1074         * maxq.h: New file: Disassembly information for the maxq port.
1075
1076 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
1077
1078         * i386.h (i386_optab): Put back "movzb".
1079
1080 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
1081
1082         * cris.h (enum cris_insn_version_usage): Tweak formatting and
1083         comments.  Remove member cris_ver_sim.  Add members
1084         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1085         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1086         (struct cris_support_reg, struct cris_cond15): New types.
1087         (cris_conds15): Declare.
1088         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1089         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1090         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1091         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1092         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1093         SIZE_FIELD_UNSIGNED.
1094
1095 2004-11-04 Jan Beulich  <jbeulich@novell.com>
1096
1097         * i386.h (sldx_Suf): Remove.
1098         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1099         (q_FP): Define, implying no REX64.
1100         (x_FP, sl_FP): Imply FloatMF.
1101         (i386_optab): Split reg and mem forms of moving from segment registers
1102         so that the memory forms can ignore the 16-/32-bit operand size
1103         distinction. Adjust a few others for Intel mode. Remove *FP uses from
1104         all non-floating-point instructions. Unite 32- and 64-bit forms of
1105         movsx, movzx, and movd. Adjust floating point operations for the above
1106         changes to the *FP macros. Add DefaultSize to floating point control
1107         insns operating on larger memory ranges. Remove left over comments
1108         hinting at certain insns being Intel-syntax ones where the ones
1109         actually meant are already gone.
1110
1111 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
1112
1113         * crx.h: Add COPS_REG_INS - Coprocessor Special register
1114         instruction type.
1115
1116 2004-09-30  Paul Brook  <paul@codesourcery.com>
1117
1118         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1119         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1120
1121 2004-09-11  Theodore A. Roth  <troth@openavr.org>
1122
1123         * avr.h: Add support for
1124         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1125
1126 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
1127
1128         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1129
1130 2004-08-24  Dmitry Diky  <diwil@spec.ru>
1131
1132         * msp430.h (msp430_opc): Add new instructions.
1133         (msp430_rcodes): Declare new instructions.
1134         (msp430_hcodes): Likewise..
1135
1136 2004-08-13  Nick Clifton  <nickc@redhat.com>
1137
1138         PR/301
1139         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1140         processors.
1141
1142 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
1143
1144         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1145
1146 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
1147
1148         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1149
1150 2004-07-21  Jan Beulich  <jbeulich@novell.com>
1151
1152         * i386.h: Adjust instruction descriptions to better match the
1153         specification.
1154
1155 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
1156
1157         * arm.h: Remove all old content.  Replace with architecture defines
1158         from gas/config/tc-arm.c.
1159
1160 2004-07-09  Andreas Schwab  <schwab@suse.de>
1161
1162         * m68k.h: Fix comment.
1163
1164 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
1165
1166         * crx.h: New file.
1167
1168 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
1169
1170         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1171
1172 2004-05-24  Peter Barada  <peter@the-baradas.com>
1173
1174         * m68k.h: Add 'size' to m68k_opcode.
1175
1176 2004-05-05  Peter Barada  <peter@the-baradas.com>
1177
1178         * m68k.h: Switch from ColdFire chip name to core variant.
1179
1180 2004-04-22  Peter Barada  <peter@the-baradas.com>
1181
1182         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
1183         descriptions for new EMAC cases.
1184         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1185         handle Motorola MAC syntax.
1186         Allow disassembly of ColdFire V4e object files.
1187
1188 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
1189
1190         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
1191
1192 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
1193
1194         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1195
1196 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1197
1198         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1199
1200 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1201
1202         * i386.h (i386_optab): Added xstore/xcrypt insns.
1203
1204 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1205
1206         * h8300.h (32bit ldc/stc): Add relaxing support.
1207
1208 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
1209
1210         * h8300.h (BITOP): Pass MEMRELAX flag.
1211
1212 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1213
1214         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1215         except for the H8S.
1216
1217 For older changes see ChangeLog-9103
1218 \f
1219 Local Variables:
1220 mode: change-log
1221 left-margin: 8
1222 fill-column: 74
1223 version-control: never
1224 End: