include/opcode/ChangeLog

   1 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
   2
   3         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
   4         Add FLAG_STRICT to pa10 ftest opcode.
   5
   6 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
   7
   8         * hppa.h (pa_opcodes): Remove lha entries.
   9
  10 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  11
  12         * hppa.h (FLAG_STRICT): Revise comment.
  13         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
  14         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
  15         entries for "fdc".
  16
  17 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  18
  19         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
  20
  21 2005-09-06  Chao-ying Fu  <fu@mips.com>
  22
  23         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
  24         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
  25         define.
  26         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
  27         (INSN_ASE_MASK): Update to include INSN_MT.
  28         (INSN_MT): New define for MT ASE.
  29
  30 2005-08-25  Chao-ying Fu  <fu@mips.com>
  31
  32         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
  33         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
  34         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
  35         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
  36         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
  37         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
  38         instructions.
  39         (INSN_DSP): New define for DSP ASE.
  40
  41 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
  42
  43         * a29k.h: Delete.
  44
  45 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
  46
  47         * ppc.h (PPC_OPCODE_E300): Define.
  48
  49 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
  50
  51         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
  52
  53 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  54
  55         PR gas/336
  56         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
  57         and pitlb.
  58
  59 2005-07-27  Jan Beulich  <jbeulich@novell.com>
  60
  61         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
  62         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
  63         Add movq-s as 64-bit variants of movd-s.
  64
  65 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  66
  67         * hppa.h: Fix punctuation in comment.
  68
  69         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
  70         implicit space-register addressing.  Set space-register bits on opcodes
  71         using implicit space-register addressing.  Add various missing pa20
  72         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
  73         space-register addressing.  Use "fE" instead of "fe" in various
  74         fstw opcodes.
  75
  76 2005-07-18  Jan Beulich  <jbeulich@novell.com>
  77
  78         * i386.h (i386_optab): Operands of aam and aad are unsigned.
  79
  80 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
  81
  82         * i386.h (i386_optab): Support Intel VMX Instructions.
  83
  84 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  85
  86         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
  87
  88 2005-07-05  Jan Beulich  <jbeulich@novell.com>
  89
  90         * i386.h (i386_optab): Add new insns.
  91
  92 2005-07-01  Nick Clifton  <nickc@redhat.com>
  93
  94         * sparc.h: Add typedefs to structure declarations.
  95
  96 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
  97
  98         PR 1013
  99         * i386.h (i386_optab): Update comments for 64bit addressing on
 100         mov. Allow 64bit addressing for mov and movq.
 101
 102 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 103
 104         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 105         respectively, in various floating-point load and store patterns.
 106
 107 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 108
 109         * hppa.h (FLAG_STRICT): Correct comment.
 110         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 111         PA 2.0 mneumonics when equivalent.  Entries with cache control
 112         completers now require PA 1.1.  Adjust whitespace.
 113
 114 2005-05-19  Anton Blanchard  <anton@samba.org>
 115
 116         * ppc.h (PPC_OPCODE_POWER5): Define.
 117
 118 2005-05-10  Nick Clifton  <nickc@redhat.com>
 119
 120         * Update the address and phone number of the FSF organization in
 121         the GPL notices in the following files:
 122         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 123         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 124         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 125         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 126         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 127         tic54x.h, tic80.h, v850.h, vax.h
 128
 129 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 130
 131         * i386.h (i386_optab): Add ht and hnt.
 132
 133 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 134
 135         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 136         Add xcrypt-ctr.  Provide aliases without hyphens.
 137
 138 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 139
 140         Moved from ../ChangeLog
 141
 142         2005-04-12  Paul Brook  <paul@codesourcery.com>
 143         * m88k.h: Rename psr macros to avoid conflicts.
 144
 145         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 146         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 147         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 148         and ARM_ARCH_V6ZKT2.
 149
 150         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 151         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 152         Remove redundant instruction types.
 153         (struct argument): X_op - new field.
 154         (struct cst4_entry): Remove.
 155         (no_op_insn): Declare.
 156
 157         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 158         * crx.h (enum argtype): Rename types, remove unused types.
 159
 160         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 161         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 162         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 163         (enum operand_type): Rearrange operands, edit comments.
 164         replace us<N> with ui<N> for unsigned immediate.
 165         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 166         displacements (respectively).
 167         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 168         (instruction type): Add NO_TYPE_INS.
 169         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 170         (operand_entry): New field - 'flags'.
 171         (operand flags): New.
 172
 173         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 174         * crx.h (operand_type): Remove redundant types i3, i4,
 175         i5, i8, i12.
 176         Add new unsigned immediate types us3, us4, us5, us16.
 177
 178 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 179
 180         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 181         adjust them accordingly.
 182
 183 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 184
 185         * i386.h (i386_optab): Add rdtscp.
 186
 187 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 188
 189         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 190         between memory and segment register. Allow movq for moving between
 191         general-purpose register and segment register.
 192
 193 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 194
 195         PR gas/707
 196         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 197         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 198         fnstsw.
 199
 200 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 201
 202         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 203         * cgen.h (enum cgen_parse_operand_type): Add
 204         CGEN_PARSE_OPERAND_SYMBOLIC.
 205
 206 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 207
 208         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 209         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 210         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 211
 212 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 213
 214         * mips.h (struct mips_opcode): Add new pinfo2 member.
 215         (INSN_ALIAS): New define for opcode table entries that are
 216         specific instances of another entry, such as 'move' for an 'or'
 217         with a zero operand.
 218         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 219         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 220
 221 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 222
 223         * mips.h (CPU_RM9000): Define.
 224         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 225
 226 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 227
 228         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 229         to/from test registers are illegal in 64-bit mode. Add missing
 230         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 231         (previously one had to explicitly encode a rex64 prefix). Re-enable
 232         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 233         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 234
 235 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 236
 237         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 238         available only with SSE2. Change the MMX additions introduced by SSE
 239         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 240         instructions by their now designated identifier (since combining i686
 241         and 3DNow! does not really imply 3DNow!A).
 242
 243 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 244
 245         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 246         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 247
 248 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 249             Vineet Sharma      <vineets@noida.hcltech.com>
 250
 251         * maxq.h: New file: Disassembly information for the maxq port.
 252
 253 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 254
 255         * i386.h (i386_optab): Put back "movzb".
 256
 257 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 258
 259         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 260         comments.  Remove member cris_ver_sim.  Add members
 261         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 262         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 263         (struct cris_support_reg, struct cris_cond15): New types.
 264         (cris_conds15): Declare.
 265         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 266         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 267         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 268         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 269         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 270         SIZE_FIELD_UNSIGNED.
 271
 272 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 273
 274         * i386.h (sldx_Suf): Remove.
 275         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 276         (q_FP): Define, implying no REX64.
 277         (x_FP, sl_FP): Imply FloatMF.
 278         (i386_optab): Split reg and mem forms of moving from segment registers
 279         so that the memory forms can ignore the 16-/32-bit operand size
 280         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 281         all non-floating-point instructions. Unite 32- and 64-bit forms of
 282         movsx, movzx, and movd. Adjust floating point operations for the above
 283         changes to the *FP macros. Add DefaultSize to floating point control
 284         insns operating on larger memory ranges. Remove left over comments
 285         hinting at certain insns being Intel-syntax ones where the ones
 286         actually meant are already gone.
 287
 288 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 289
 290         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 291         instruction type.
 292
 293 2004-09-30  Paul Brook  <paul@codesourcery.com>
 294
 295         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 296         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 297
 298 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 299
 300         * avr.h: Add support for
 301         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 302
 303 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 304
 305         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 306
 307 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 308
 309         * msp430.h (msp430_opc): Add new instructions.
 310         (msp430_rcodes): Declare new instructions.
 311         (msp430_hcodes): Likewise..
 312
 313 2004-08-13  Nick Clifton  <nickc@redhat.com>
 314
 315         PR/301
 316         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 317         processors.
 318
 319 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 320
 321         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 322
 323 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 324
 325         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 326
 327 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 328
 329         * i386.h: Adjust instruction descriptions to better match the
 330         specification.
 331
 332 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 333
 334         * arm.h: Remove all old content.  Replace with architecture defines
 335         from gas/config/tc-arm.c.
 336
 337 2004-07-09  Andreas Schwab  <schwab@suse.de>
 338
 339         * m68k.h: Fix comment.
 340
 341 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 342
 343         * crx.h: New file.
 344
 345 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 346
 347         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 348
 349 2004-05-24  Peter Barada  <peter@the-baradas.com>
 350
 351         * m68k.h: Add 'size' to m68k_opcode.
 352
 353 2004-05-05  Peter Barada  <peter@the-baradas.com>
 354
 355         * m68k.h: Switch from ColdFire chip name to core variant.
 356
 357 2004-04-22  Peter Barada  <peter@the-baradas.com>
 358
 359         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 360         descriptions for new EMAC cases.
 361         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 362         handle Motorola MAC syntax.
 363         Allow disassembly of ColdFire V4e object files.
 364
 365 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 366
 367         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 368
 369 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 370
 371         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 372
 373 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 374
 375         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 376
 377 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 378
 379         * i386.h (i386_optab): Added xstore/xcrypt insns.
 380
 381 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 382
 383         * h8300.h (32bit ldc/stc): Add relaxing support.
 384
 385 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 386
 387         * h8300.h (BITOP): Pass MEMRELAX flag.
 388
 389 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 390
 391         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 392         except for the H8S.
 393
 394 For older changes see ChangeLog-9103
 395 \f
 396 Local Variables:
 397 mode: change-log
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