include/opcode/ChangeLog

   1 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
   2
   3         * mips.h: Document MIPS16 "I" opcode.
   4
   5 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
   6
   7         * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
   8         (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
   9         (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
  10         (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
  11         (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
  12         (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
  13         (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
  14         (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
  15         (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
  16         (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
  17         (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
  18         (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
  19         (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
  20         Rename to...
  21         (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
  22         (M_USD_AB): ...these.
  23
  24 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  25
  26         * mips.h: Remove documentation of "[" and "]".  Update documentation
  27         of "k" and the MDMX formats.
  28
  29 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  30
  31         * mips.h: Update documentation of "+s" and "+S".
  32
  33 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  34
  35         * mips.h: Document "+i".
  36
  37 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  38
  39         * mips.h: Remove "mi" documentation.  Update "mh" documentation.
  40         (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
  41         Delete.
  42         (INSN2_WRITE_GPR_MHI): Rename to...
  43         (INSN2_WRITE_GPR_MH): ...this.
  44
  45 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  46
  47         * mips.h: Remove documentation of "+D" and "+T".
  48
  49 2013-06-26  Richard Sandiford  <rdsandiford@googlemail.com>
  50
  51         * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
  52         Use "source" rather than "destination" for microMIPS "G".
  53
  54 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
  55
  56         * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
  57         values.
  58
  59 2013-06-23  Richard Sandiford  <rdsandiford@googlemail.com>
  60
  61         * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
  62
  63 2013-06-17  Catherine Moore  <clm@codesourcery.com>
  64             Maciej W. Rozycki  <macro@codesourcery.com>
  65             Chao-Ying Fu  <fu@mips.com>
  66
  67         * mips.h (OP_SH_EVAOFFSET): Define.
  68         (OP_MASK_EVAOFFSET): Define.
  69         (INSN_ASE_MASK): Delete.
  70         (ASE_EVA): Define.
  71         (M_CACHEE_AB, M_CACHEE_OB): New.
  72         (M_LBE_OB, M_LBE_AB): New.
  73         (M_LBUE_OB, M_LBUE_AB): New.
  74         (M_LHE_OB, M_LHE_AB): New.
  75         (M_LHUE_OB, M_LHUE_AB): New.
  76         (M_LLE_AB, M_LLE_OB): New.
  77         (M_LWE_OB, M_LWE_AB): New.
  78         (M_LWLE_AB, M_LWLE_OB): New.
  79         (M_LWRE_AB, M_LWRE_OB): New.
  80         (M_PREFE_AB, M_PREFE_OB): New.
  81         (M_SCE_AB, M_SCE_OB): New.
  82         (M_SBE_OB, M_SBE_AB): New.
  83         (M_SHE_OB, M_SHE_AB): New.
  84         (M_SWE_OB, M_SWE_AB): New.
  85         (M_SWLE_AB, M_SWLE_OB): New.
  86         (M_SWRE_AB, M_SWRE_OB): New.
  87         (MICROMIPSOP_SH_EVAOFFSET): Define.
  88         (MICROMIPSOP_MASK_EVAOFFSET): Define.
  89
  90 2013-06-12  Sandra Loosemore  <sandra@codesourcery.com>
  91
  92         * nios2.h (OP_MATCH_ERET): Correct eret encoding.
  93
  94 2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
  95
  96         * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
  97
  98 2013-05-09  Andrew Pinski  <apinski@cavium.com>
  99
 100         * mips.h (OP_MASK_CODE10): Correct definition.
 101         (OP_SH_CODE10): Likewise.
 102         Add a comment that "+J" is used now for OP_*CODE10.
 103         (INSN_ASE_MASK): Update.
 104         (INSN_VIRT): New macro.
 105         (INSN_VIRT64): New macro
 106
 107 2013-05-02  Nick Clifton  <nickc@redhat.com>
 108
 109         * msp430.h: Add patterns for MSP430X instructions.
 110
 111 2013-04-06  David S. Miller  <davem@davemloft.net>
 112
 113         * sparc.h (F_PREFERRED): Define.
 114         (F_PREF_ALIAS): Define.
 115
 116 2013-04-03  Nick Clifton  <nickc@redhat.com>
 117
 118         * v850.h (V850_INVERSE_PCREL): Define.
 119
 120 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 121
 122         PR binutils/15068
 123         * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
 124
 125 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 126
 127         PR binutils/15068
 128         * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
 129         Add 16-bit opcodes.
 130         * tic6xc-opcode-table.h: Add 16-bit insns.
 131         * tic6x.h: Add support for 16-bit insns.
 132
 133 2013-03-21  Michael Schewe  <michael.schewe@gmx.net>
 134
 135         * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
 136         and mov.b/w/l Rs,@(d:32,ERd).
 137
 138 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 139
 140         PR gas/15082
 141         * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
 142         from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
 143         tic6x_operand_xregpair operand coding type.
 144         Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
 145         opcode field, usu ORXREGD1324 for the src2 operand and remove the
 146         TIC6X_FLAG_NO_CROSS.
 147
 148 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 149
 150         PR gas/15095
 151         * tic6x.h (enum tic6x_coding_method): Add
 152         tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
 153         separately the msb and lsb of a register pair.  This is needed to
 154         encode the opcodes in the same way as TI assembler does.
 155         * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
 156         and rsqrdp opcodes to use the new field coding types.
 157
 158 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 159
 160         * arm.h (CRC_EXT_ARMV8): New constant.
 161         (ARCH_CRC_ARMV8): New macro.
 162
 163 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
 164
 165         * aarch64.h (AARCH64_FEATURE_CRC): New macro.
 166
 167 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
 168             Andrew Jenner <andrew@codesourcery.com>
 169
 170         Based on patches from Altera Corporation.
 171
 172         * nios2.h: New file.
 173
 174 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
 175
 176         * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
 177
 178 2013-01-28  Alexis Deruelle  <alexis.deruelle@gmail.com>
 179
 180         PR gas/15069
 181         * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
 182
 183 2013-01-24  Nick Clifton  <nickc@redhat.com>
 184
 185         * v850.h: Add e3v5 support.
 186
 187 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
 188
 189         * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
 190
 191 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
 192
 193         * ppc.h (PPC_OPCODE_POWER8): New define.
 194         (PPC_OPCODE_HTM): Likewise.
 195
 196 2013-01-10  Will Newton <will.newton@imgtec.com>
 197
 198         * metag.h: New file.
 199
 200 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 201
 202         * cr16.h (make_instruction): Rename to cr16_make_instruction.
 203         (match_opcode): Rename to cr16_match_opcode.
 204
 205 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
 206
 207         * mips.h: Add support for r5900 instructions including lq and sq.
 208
 209 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 210
 211         * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
 212         (make_instruction,match_opcode): Added function prototypes.
 213         (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
 214
 215 2012-11-23  Alan Modra  <amodra@gmail.com>
 216
 217         * ppc.h (ppc_parse_cpu): Update prototype.
 218
 219 2012-10-14  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 220
 221         * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
 222         opcodes.  Likewise, use "cM" instead of "cm" in fstqs opcodes.
 223
 224 2012-10-04  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 225
 226         * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
 227
 228 2012-09-04  Sergey A. Guriev <sergey.a.guriev@intel.com>
 229
 230         * ia64.h (ia64_opnd): Add new operand types.
 231
 232 2012-08-21  David S. Miller  <davem@davemloft.net>
 233
 234         * sparc.h (F3F4): New macro.
 235
 236 2012-08-13  Ian Bolton  <ian.bolton@arm.com>
 237             Laurent Desnogues  <laurent.desnogues@arm.com>
 238             Jim MacArthur  <jim.macarthur@arm.com>
 239             Marcus Shawcroft  <marcus.shawcroft@arm.com>
 240             Nigel Stephens  <nigel.stephens@arm.com>
 241             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 242             Richard Earnshaw  <rearnsha@arm.com>
 243             Sofiane Naci  <sofiane.naci@arm.com>
 244             Tejas Belagod  <tejas.belagod@arm.com>
 245             Yufeng Zhang  <yufeng.zhang@arm.com>
 246
 247         * aarch64.h: New file.
 248
 249 2012-08-13  Richard Sandiford  <rdsandiford@googlemail.com>
 250             Maciej W. Rozycki  <macro@codesourcery.com>
 251
 252         * mips.h (mips_opcode): Add the exclusions field.
 253         (OPCODE_IS_MEMBER): Remove macro.
 254         (cpu_is_member): New inline function.
 255         (opcode_is_member): Likewise.
 256
 257 2012-07-31  Chao-Ying Fu  <fu@mips.com>
 258             Catherine Moore  <clm@codesourcery.com>
 259             Maciej W. Rozycki  <macro@codesourcery.com>
 260
 261         * mips.h: Document microMIPS DSP ASE usage.
 262         (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
 263         microMIPS DSP ASE support.
 264         (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
 265         (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
 266         (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
 267         (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
 268         (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
 269         (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
 270         (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
 271
 272 2012-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 273
 274         * mips.h: Fix a typo in description.
 275
 276 2012-06-07  Georg-Johann Lay  <avr@gjlay.de>
 277
 278         * avr.h: (AVR_ISA_XCH): New define.
 279         (AVR_ISA_XMEGA): Use it.
 280         (XCH, LAS, LAT, LAC): New XMEGA opcodes.
 281
 282 2012-05-15  James Murray <jsm@jsm-net.demon.co.uk>
 283
 284         * m68hc11.h: Add XGate definitions.
 285         (struct m68hc11_opcode): Add xg_mask field.
 286
 287 2012-05-14  Catherine Moore  <clm@codesourcery.com>
 288             Maciej W. Rozycki  <macro@codesourcery.com>
 289             Rhonda Wittels  <rhonda@codesourcery.com>
 290
 291         * ppc.h (PPC_OPCODE_VLE): New definition.
 292         (PPC_OP_SA): New macro.
 293         (PPC_OP_SE_VLE): New macro.
 294         (PPC_OP): Use a variable shift amount.
 295         (powerpc_operand): Update comments.
 296         (PPC_OPSHIFT_INV): New macro.
 297         (PPC_OPERAND_CR): Replace with...
 298         (PPC_OPERAND_CR_BIT): ...this and
 299         (PPC_OPERAND_CR_REG): ...this.
 300
 301
 302 2012-05-03  Sean Keys  <skeys@ipdatasys.com>
 303
 304         * xgate.h: Header file for XGATE assembler.
 305
 306 2012-04-27  David S. Miller  <davem@davemloft.net>
 307
 308         * sparc.h: Document new arg code' )' for crypto RS3
 309         immediates.
 310
 311         * sparc.h (struct sparc_opcode): New field 'hwcaps'.
 312         F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
 313         F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
 314         F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
 315         (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
 316         HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
 317         HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
 318         HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
 319         HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
 320         HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
 321         HWCAP_CBCOND, HWCAP_CRC32): New defines.
 322
 323 2012-03-10  Edmar Wienskoski  <edmar@freescale.com>
 324
 325         * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
 326
 327 2012-02-27  Alan Modra  <amodra@gmail.com>
 328
 329         * crx.h (cst4_map): Update declaration.
 330
 331 2012-02-25  Walter Lee  <walt@tilera.com>
 332
 333         * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
 334         TILEGX_OPC_LD_TLS.
 335         * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
 336         TILEPRO_OPC_LW_TLS_SN.
 337
 338 2012-02-08  H.J. Lu  <hongjiu.lu@intel.com>
 339
 340         * i386.h (XACQUIRE_PREFIX_OPCODE): New.
 341         (XRELEASE_PREFIX_OPCODE): Likewise.
 342
 343 2011-12-08  Andrew Pinski  <apinski@cavium.com>
 344             Adam Nemet  <anemet@caviumnetworks.com>
 345
 346         * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
 347         (INSN_OCTEON2): New macro.
 348         (CPU_OCTEON2): New macro.
 349         (OPCODE_IS_MEMBER): Add Octeon2.
 350
 351 2011-11-29  Andrew Pinski  <apinski@cavium.com>
 352
 353         * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
 354         (INSN_OCTEONP): New macro.
 355         (CPU_OCTEONP): New macro.
 356         (OPCODE_IS_MEMBER): Add Octeon+.
 357         (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
 358
 359 2011-11-01  DJ Delorie  <dj@redhat.com>
 360
 361         * rl78.h: New file.
 362
 363 2011-10-24  Maciej W. Rozycki  <macro@codesourcery.com>
 364
 365         * mips.h: Fix a typo in description.
 366
 367 2011-09-21  David S. Miller  <davem@davemloft.net>
 368
 369         * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
 370         (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
 371         F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
 372         F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
 373
 374 2011-08-09  Chao-ying Fu  <fu@mips.com>
 375             Maciej W. Rozycki  <macro@codesourcery.com>
 376
 377         * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
 378         (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
 379         (INSN_ASE_MASK): Add the MCU bit.
 380         (INSN_MCU): New macro.
 381         (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
 382         (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
 383
 384 2011-08-09  Maciej W. Rozycki  <macro@codesourcery.com>
 385
 386         * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
 387         (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
 388         (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
 389         (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
 390         (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
 391         (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
 392         (INSN2_READ_GPR_MMN): Likewise.
 393         (INSN2_READ_FPR_D): Change the bit used.
 394         (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
 395         (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
 396         (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
 397         (INSN2_COND_BRANCH): Likewise.
 398         (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
 399         (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
 400         (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
 401         (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
 402         (INSN2_MOD_GPR_MN): Likewise.
 403
 404 2011-08-05  David S. Miller  <davem@davemloft.net>
 405
 406         * sparc.h: Document new format codes '4', '5', and '('.
 407         (OPF_LOW4, RS3): New macros.
 408
 409 2011-08-03  Maciej W. Rozycki  <macro@codesourcery.com>
 410
 411         * mips.h: Document the use of FP_D in MIPS16 mode.  Adjust the
 412         order of flags documented.
 413
 414 2011-07-29  Maciej W. Rozycki  <macro@codesourcery.com>
 415
 416         * mips.h: Clarify the description of microMIPS instruction
 417         manipulation macros.
 418         (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
 419
 420 2011-07-24  Chao-ying Fu  <fu@mips.com>
 421             Maciej W. Rozycki  <macro@codesourcery.com>
 422
 423         * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
 424         (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
 425         (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
 426         (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
 427         (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
 428         (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
 429         (OP_MASK_RS3, OP_SH_RS3): Likewise.
 430         (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
 431         (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
 432         (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
 433         (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
 434         (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
 435         (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
 436         (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
 437         (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
 438         (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
 439         (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
 440         (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
 441         (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
 442         (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
 443         (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
 444         (INSN_WRITE_GPR_S): New macro.
 445         (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
 446         (INSN2_READ_FPR_D): Likewise.
 447         (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
 448         (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
 449         (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
 450         (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
 451         (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
 452         (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
 453         (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
 454         (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
 455         (CPU_MICROMIPS): New macro.
 456         (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
 457         (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
 458         (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
 459         (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
 460         (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
 461         (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
 462         (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
 463         (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
 464         (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
 465         (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
 466         (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
 467         (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
 468         (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
 469         (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
 470         (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
 471         (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
 472         (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
 473         (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
 474         (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
 475         (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
 476         (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
 477         (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
 478         (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
 479         (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
 480         (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
 481         (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
 482         (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
 483         (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
 484         (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
 485         (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
 486         (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
 487         (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
 488         (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
 489         (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
 490         (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
 491         (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
 492         (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
 493         (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
 494         (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
 495         (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
 496         (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
 497         (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
 498         (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
 499         (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
 500         (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
 501         (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
 502         (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
 503         (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
 504         (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
 505         (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
 506         (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
 507         (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
 508         (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
 509         (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
 510         (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
 511         (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
 512         (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
 513         (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
 514         (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
 515         (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
 516         (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
 517         (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
 518         (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
 519         (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
 520         (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
 521         (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
 522         (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
 523         (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
 524         (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
 525         (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
 526         (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
 527         (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
 528         (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
 529         (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
 530         (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
 531         (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
 532         (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
 533         (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
 534         (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
 535         (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
 536         (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
 537         (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
 538         (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
 539         (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
 540         (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
 541         (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
 542         (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
 543         (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
 544         (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
 545         (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
 546         (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
 547         (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
 548         (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
 549         (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
 550         (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
 551         (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
 552         (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
 553         (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
 554         (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
 555         (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
 556         (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
 557         (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
 558         (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
 559         (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
 560         (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
 561         (micromips_opcodes): New declaration.
 562         (bfd_micromips_num_opcodes): Likewise.
 563
 564 2011-07-24  Maciej W. Rozycki  <macro@codesourcery.com>
 565
 566         * mips.h (INSN_TRAP): Rename to...
 567         (INSN_NO_DELAY_SLOT): ... this.
 568         (INSN_SYNC): Remove macro.
 569
 570 2011-07-01  Eric B. Weddington  <eric.weddington@atmel.com>
 571
 572         * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
 573         a duplicate of AVR_ISA_SPM.
 574
 575 2011-07-01  Nick Clifton  <nickc@redhat.com>
 576
 577         * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
 578
 579 2011-06-18  Robin Getz  <robin.getz@analog.com>
 580
 581         * bfin.h (is_macmod_signed): New func
 582
 583 2011-06-18  Mike Frysinger  <vapier@gentoo.org>
 584
 585         * bfin.h (is_macmod_pmove): Add missing space before func args.
 586         (is_macmod_hmove): Likewise.
 587
 588 2011-06-13  Walter Lee  <walt@tilera.com>
 589
 590         * tilegx.h: New file.
 591         * tilepro.h: New file.
 592
 593 2011-05-31  Paul Brook  <paul@codesourcery.com>
 594
 595         * arm.h (ARM_ARCH_V7R_IDIV): Define.
 596
 597 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 598
 599         * s390.h: Replace S390_OPERAND_REG_EVEN with
 600         S390_OPERAND_REG_PAIR.
 601
 602 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 603
 604         * s390.h: Add S390_OPCODE_REG_EVEN flag.
 605
 606 2011-04-18  Julian Brown  <julian@codesourcery.com>
 607
 608         * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
 609
 610 2011-04-11  Dan McDonald  <dan@wellkeeper.com>
 611
 612         PR gas/12296
 613         * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
 614
 615 2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>
 616
 617         * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
 618         New instruction set flags.
 619         (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
 620
 621 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 622
 623         * mips.h (M_PREF_AB): New enum value.
 624
 625 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 626
 627         * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
 628         M_IU): Define.
 629         (is_macmod_pmove, is_macmod_hmove): New functions.
 630
 631 2011-02-11  Mike Frysinger  <vapier@gentoo.org>
 632
 633         * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
 634
 635 2011-02-04  Bernd Schmidt  <bernds@codesourcery.com>
 636
 637         * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
 638         * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
 639
 640 2010-12-31  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 641
 642         PR gas/11395
 643         * hppa.h (pa_opcodes): Revert last change.  Exchange 32 and 64-bit
 644         "bb" entries.
 645
 646 2010-12-26  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 647
 648         PR gas/11395
 649         * hppa.h: Clear "d" bit in "add" and "sub" patterns.
 650
 651 2010-12-18  Richard Sandiford  <rdsandiford@googlemail.com>
 652
 653         * mips.h: Update commentary after last commit.
 654
 655 2010-12-18  Mingjie Xing  <mingjie.xing@gmail.com>
 656
 657         * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
 658         (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
 659         (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
 660
 661 2010-11-25  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 662
 663         * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
 664
 665 2010-11-23  Richard Sandiford  <rdsandiford@googlemail.com>
 666
 667         * mips.h: Fix previous commit.
 668
 669 2010-11-23  Maciej W. Rozycki  <macro@linux-mips.org>
 670
 671         * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
 672         (INSN_LOONGSON_3A): Clear bit 31.
 673
 674 2010-11-15  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 675
 676         PR gas/12198
 677         * arm.h (ARM_AEXT_V6M_ONLY): New define.
 678         (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
 679         (ARM_ARCH_V6M_ONLY): New define.
 680
 681 2010-11-11  Mingming Sun  <mingm.sun@gmail.com>
 682
 683         * mips.h (INSN_LOONGSON_3A): Defined.
 684         (CPU_LOONGSON_3A): Defined.
 685         (OPCODE_IS_MEMBER): Add LOONGSON_3A.
 686
 687 2010-10-09  Matt Rice  <ratmice@gmail.com>
 688
 689         * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
 690         (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
 691
 692 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 693
 694         * arm.h (ARM_EXT_VIRT): New define.
 695         (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
 696         (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
 697         Extensions.
 698
 699 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 700
 701         * arm.h (ARM_AEXT_ADIV): New define.
 702         (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
 703
 704 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 705
 706         * arm.h (ARM_EXT_OS): New define.
 707         (ARM_AEXT_V6SM): Likewise.
 708         (ARM_ARCH_V6SM): Likewise.
 709
 710 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 711
 712         * arm.h (ARM_EXT_MP): Add.
 713         (ARM_ARCH_V7A_MP): Likewise.
 714
 715 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 716
 717         * bfin.h: Declare pseudoChr structs/defines.
 718
 719 2010-09-21  Mike Frysinger  <vapier@gentoo.org>
 720
 721         * bfin.h: Strip trailing whitespace.
 722
 723 2010-07-29  DJ Delorie  <dj@redhat.com>
 724
 725         * rx.h (RX_Operand_Type): Add TwoReg.
 726         (RX_Opcode_ID): Remove ediv and ediv2.
 727
 728 2010-07-27  DJ Delorie  <dj@redhat.com>
 729
 730         * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
 731
 732 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
 733             Ina Pandit  <ina.pandit@kpitcummins.com>
 734
 735         * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
 736         PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
 737         PROCESSOR_V850E2_ALL.
 738         Remove PROCESSOR_V850EA support.
 739         (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
 740         V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
 741         V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
 742         V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
 743         V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
 744         V850_OPERAND_PERCENT.
 745         Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
 746         V850_NOT_R0.
 747         Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
 748         and V850E_PUSH_POP
 749
 750 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 751
 752         * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
 753         (MIPS16_INSN_BRANCH): Rename to...
 754         (MIPS16_INSN_COND_BRANCH): ... this.
 755
 756 2010-07-03  Alan Modra  <amodra@gmail.com>
 757
 758         * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
 759         Renumber other PPC_OPCODE defines.
 760
 761 2010-07-03  Alan Modra  <amodra@gmail.com>
 762
 763         * ppc.h (PPC_OPCODE_COMMON): Expand comment.
 764
 765 2010-06-29  Alan Modra  <amodra@gmail.com>
 766
 767         * maxq.h: Delete file.
 768
 769 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 770
 771         * ppc.h (PPC_OPCODE_E500): Define.
 772
 773 2010-05-26  Catherine Moore  <clm@codesourcery.com>
 774
 775         * opcode/mips.h (INSN_MIPS16): Remove.
 776
 777 2010-04-21  Joseph Myers  <joseph@codesourcery.com>
 778
 779         * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
 780
 781 2010-04-15  Nick Clifton  <nickc@redhat.com>
 782
 783         * alpha.h: Update copyright notice to use GPLv3.
 784         * arc.h: Likewise.
 785         * arm.h: Likewise.
 786         * avr.h: Likewise.
 787         * bfin.h: Likewise.
 788         * cgen.h: Likewise.
 789         * convex.h: Likewise.
 790         * cr16.h: Likewise.
 791         * cris.h: Likewise.
 792         * crx.h: Likewise.
 793         * d10v.h: Likewise.
 794         * d30v.h: Likewise.
 795         * dlx.h: Likewise.
 796         * h8300.h: Likewise.
 797         * hppa.h: Likewise.
 798         * i370.h: Likewise.
 799         * i386.h: Likewise.
 800         * i860.h: Likewise.
 801         * i960.h: Likewise.
 802         * ia64.h: Likewise.
 803         * m68hc11.h: Likewise.
 804         * m68k.h: Likewise.
 805         * m88k.h: Likewise.
 806         * maxq.h: Likewise.
 807         * mips.h: Likewise.
 808         * mmix.h: Likewise.
 809         * mn10200.h: Likewise.
 810         * mn10300.h: Likewise.
 811         * msp430.h: Likewise.
 812         * np1.h: Likewise.
 813         * ns32k.h: Likewise.
 814         * or32.h: Likewise.
 815         * pdp11.h: Likewise.
 816         * pj.h: Likewise.
 817         * pn.h: Likewise.
 818         * ppc.h: Likewise.
 819         * pyr.h: Likewise.
 820         * rx.h: Likewise.
 821         * s390.h: Likewise.
 822         * score-datadep.h: Likewise.
 823         * score-inst.h: Likewise.
 824         * sparc.h: Likewise.
 825         * spu-insns.h: Likewise.
 826         * spu.h: Likewise.
 827         * tic30.h: Likewise.
 828         * tic4x.h: Likewise.
 829         * tic54x.h: Likewise.
 830         * tic80.h: Likewise.
 831         * v850.h: Likewise.
 832         * vax.h: Likewise.
 833
 834 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
 835
 836         * tic6x-control-registers.h, tic6x-insn-formats.h,
 837         tic6x-opcode-table.h, tic6x.h: New.
 838
 839 2010-02-25  Wu Zhangjin  <wuzhangjin@gmail.com>
 840
 841         * mips.h: (LOONGSON2F_NOP_INSN): New macro.
 842
 843 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
 844
 845         * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
 846
 847 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 848
 849         * ia64.h (ia64_find_opcode): Remove argument name.
 850         (ia64_find_next_opcode): Likewise.
 851         (ia64_dis_opcode): Likewise.
 852         (ia64_free_opcode): Likewise.
 853         (ia64_find_dependency): Likewise.
 854
 855 2009-11-22  Doug Evans  <dje@sebabeach.org>
 856
 857         * cgen.h: Include bfd_stdint.h.
 858         (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
 859
 860 2009-11-18  Paul Brook  <paul@codesourcery.com>
 861
 862         * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
 863
 864 2009-11-17  Paul Brook  <paul@codesourcery.com>
 865         Daniel Jacobowitz  <dan@codesourcery.com>
 866
 867         * arm.h (ARM_EXT_V6_DSP): Define.
 868         (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
 869         (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
 870
 871 2009-11-04  DJ Delorie  <dj@redhat.com>
 872
 873         * rx.h (rx_decode_opcode) (mvtipl): Add.
 874         (mvtcp, mvfcp, opecp): Remove.
 875
 876 2009-11-02  Paul Brook  <paul@codesourcery.com>
 877
 878         * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
 879         FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
 880         (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
 881         FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
 882         FPU_ARCH_NEON_VFP_V4): Define.
 883
 884 2009-10-23  Doug Evans  <dje@sebabeach.org>
 885
 886         * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
 887         * cgen.h: Update.  Improve multi-inclusion macro name.
 888
 889 2009-10-02  Peter Bergner  <bergner@vnet.ibm.com>
 890
 891         * ppc.h (PPC_OPCODE_476): Define.
 892
 893 2009-10-01  Peter Bergner  <bergner@vnet.ibm.com>
 894
 895         * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
 896
 897 2009-09-29  DJ Delorie  <dj@redhat.com>
 898
 899         * rx.h: New file.
 900
 901 2009-09-22  Peter Bergner  <bergner@vnet.ibm.com>
 902
 903         * ppc.h (ppc_cpu_t): Typedef to uint64_t.
 904
 905 2009-09-21  Ben Elliston  <bje@au.ibm.com>
 906
 907         * ppc.h (PPC_OPCODE_PPCA2): New.
 908
 909 2009-09-05  Martin Thuresson  <martin@mtme.org>
 910
 911         * ia64.h (struct ia64_operand): Renamed member class to op_class.
 912
 913 2009-08-29  Martin Thuresson  <martin@mtme.org>
 914
 915         * tic30.h (template): Rename type template to
 916         insn_template. Updated code to use new name.
 917         * tic54x.h (template): Rename type template to
 918         insn_template.
 919
 920 2009-08-20  Nick Hudson  <nick.hudson@gmx.co.uk>
 921
 922         * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
 923
 924 2009-06-11  Anthony Green  <green@moxielogic.com>
 925
 926         * moxie.h (MOXIE_F3_PCREL): Define.
 927         (moxie_form3_opc_info): Grow.
 928
 929 2009-06-06  Anthony Green  <green@moxielogic.com>
 930
 931         * moxie.h (MOXIE_F1_M): Define.
 932
 933 2009-04-15  Anthony Green  <green@moxielogic.com>
 934
 935         * moxie.h: Created.
 936
 937 2009-04-06  DJ Delorie  <dj@redhat.com>
 938
 939         * h8300.h: Add relaxation attributes to MOVA opcodes.
 940
 941 2009-03-10  Alan Modra  <amodra@bigpond.net.au>
 942
 943         * ppc.h (ppc_parse_cpu): Declare.
 944
 945 2009-03-02  Qinwei  <qinwei@sunnorth.com.cn>
 946
 947         * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
 948         and _IMM11 for mbitclr and mbitset.
 949         * score-datadep.h: Update dependency information.
 950
 951 2009-02-26  Peter Bergner  <bergner@vnet.ibm.com>
 952
 953         * ppc.h (PPC_OPCODE_POWER7): New.
 954
 955 2009-02-06  Doug Evans  <dje@google.com>
 956
 957         * i386.h: Add comment regarding sse* insns and prefixes.
 958
 959 2009-02-03  Sandip Matte  <sandip@rmicorp.com>
 960
 961         * mips.h (INSN_XLR): Define.
 962         (INSN_CHIP_MASK): Update.
 963         (CPU_XLR): Define.
 964         (OPCODE_IS_MEMBER): Update.
 965         (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
 966
 967 2009-01-28  Doug Evans  <dje@google.com>
 968
 969         * opcode/i386.h: Add multiple inclusion protection.
 970         (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
 971         (EDI_REG_NUM): New macros.
 972         (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
 973         (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
 974         (REX_PREFIX_P): New macro.
 975
 976 2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
 977
 978         * ppc.h (struct powerpc_opcode): New field "deprecated".
 979         (PPC_OPCODE_NOPOWER4): Delete.
 980
 981 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
 982
 983         * mips.h: Define CPU_R14000, CPU_R16000.
 984         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
 985
 986 2008-11-18  Catherine Moore  <clm@codesourcery.com>
 987
 988         * arm.h (FPU_NEON_FP16): New.
 989         (FPU_ARCH_NEON_FP16): New.
 990
 991 2008-11-06  Chao-ying Fu  <fu@mips.com>
 992
 993         * mips.h: Doucument '1' for 5-bit sync type.
 994
 995 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
 996
 997         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
 998         IA64_RS_CR.
 999
1000 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
1001
1002         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1003
1004 2008-07-30  Michael J. Eager  <eager@eagercon.com>
1005
1006         * ppc.h (PPC_OPCODE_405): Define.
1007         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1008
1009 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
1010
1011         * ppc.h (ppc_cpu_t): New typedef.
1012         (struct powerpc_opcode <flags>): Use it.
1013         (struct powerpc_operand <insert, extract>): Likewise.
1014         (struct powerpc_macro <flags>): Likewise.
1015
1016 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
1017
1018         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1019         Update comment before MIPS16 field descriptors to mention MIPS16.
1020         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1021         BBIT.
1022         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1023         New bit masks and shift counts for cins and exts.
1024
1025         * mips.h: Document new field descriptors +Q.
1026         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1027
1028 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
1029
1030         * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
1031         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1032
1033 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
1034
1035         * ppc.h: (PPC_OPCODE_E500MC): New.
1036
1037 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
1038
1039         * i386.h (MAX_OPERANDS): Set to 5.
1040         (MAX_MNEM_SIZE): Changed to 20.
1041
1042 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
1043
1044         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1045
1046 2008-03-09  Paul Brook  <paul@codesourcery.com>
1047
1048         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1049
1050 2008-03-04  Paul Brook  <paul@codesourcery.com>
1051
1052         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1053         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1054         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1055
1056 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
1057             Nick Clifton  <nickc@redhat.com>
1058
1059         PR 3134
1060         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1061         with a 32-bit displacement but without the top bit of the 4th byte
1062         set.
1063
1064 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1065
1066         * cr16.h (cr16_num_optab): Declared.
1067
1068 2008-02-14  Hakan Ardo  <hakan@debian.org>
1069
1070         PR gas/2626
1071         * avr.h (AVR_ISA_2xxe): Define.
1072
1073 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
1074
1075         * mips.h: Update copyright.
1076         (INSN_CHIP_MASK): New macro.
1077         (INSN_OCTEON): New macro.
1078         (CPU_OCTEON): New macro.
1079         (OPCODE_IS_MEMBER): Handle Octeon instructions.
1080
1081 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
1082
1083         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1084
1085 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
1086
1087         * avr.h (AVR_ISA_USB162): Add new opcode set.
1088         (AVR_ISA_AVR3): Likewise.
1089
1090 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
1091
1092         * mips.h (INSN_LOONGSON_2E): New.
1093         (INSN_LOONGSON_2F): New.
1094         (CPU_LOONGSON_2E): New.
1095         (CPU_LOONGSON_2F): New.
1096         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1097
1098 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
1099
1100         * mips.h (INSN_ISA*): Redefine certain values as an
1101         enumeration.  Update comments.
1102         (mips_isa_table): New.
1103         (ISA_MIPS*): Redefine to match enumeration.
1104         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1105         values.
1106
1107 2007-08-08  Ben Elliston  <bje@au.ibm.com>
1108
1109         * ppc.h (PPC_OPCODE_PPCPS): New.
1110
1111 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
1112
1113         * m68k.h: Document j K & E.
1114
1115 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
1116
1117         * cr16.h: New file for CR16 target.
1118
1119 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
1120
1121         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1122
1123 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
1124
1125         * m68k.h (mcfisa_c): New.
1126         (mcfusp, mcf_mask): Adjust.
1127
1128 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
1129
1130         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1131         (num_powerpc_operands): Declare.
1132         (PPC_OPERAND_SIGNED et al): Redefine as hex.
1133         (PPC_OPERAND_PLUS1): Define.
1134
1135 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
1136
1137         * i386.h (REX_MODE64): Renamed to ...
1138         (REX_W): This.
1139         (REX_EXTX): Renamed to ...
1140         (REX_R): This.
1141         (REX_EXTY): Renamed to ...
1142         (REX_X): This.
1143         (REX_EXTZ): Renamed to ...
1144         (REX_B): This.
1145
1146 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
1147
1148         * i386.h: Add entries from config/tc-i386.h and move tables
1149         to opcodes/i386-opc.h.
1150
1151 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
1152
1153         * i386.h (FloatDR): Removed.
1154         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1155
1156 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
1157
1158         * spu-insns.h: Add soma double-float insns.
1159
1160 2007-02-20  Thiemo Seufer  <ths@mips.com>
1161             Chao-Ying Fu  <fu@mips.com>
1162
1163         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1164         (INSN_DSPR2): Add flag for DSP R2 instructions.
1165         (M_BALIGN): New macro.
1166
1167 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
1168
1169         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1170         and Seg3ShortFrom with Shortform.
1171
1172 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
1173
1174         PR gas/4027
1175         * i386.h (i386_optab): Put the real "test" before the pseudo
1176         one.
1177
1178 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
1179
1180         * m68k.h (m68010up): OR fido_a.
1181
1182 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
1183
1184         * m68k.h (fido_a): New.
1185
1186 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
1187
1188         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1189         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1190         values.
1191
1192 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
1193
1194         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1195
1196 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
1197
1198         * score-inst.h (enum score_insn_type): Add Insn_internal.
1199
1200 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
1201             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
1202             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
1203             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
1204             Alan Modra  <amodra@bigpond.net.au>
1205
1206         * spu-insns.h: New file.
1207         * spu.h: New file.
1208
1209 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
1210
1211         * ppc.h (PPC_OPCODE_CELL): Define.
1212
1213 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
1214
1215         * i386.h :  Modify opcode to support for the change in POPCNT opcode
1216         in amdfam10 architecture.
1217
1218 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
1219
1220         * i386.h: Replace CpuMNI with CpuSSSE3.
1221
1222 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
1223             Joseph Myers  <joseph@codesourcery.com>
1224             Ian Lance Taylor  <ian@wasabisystems.com>
1225             Ben Elliston  <bje@wasabisystems.com>
1226
1227         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1228
1229 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
1230
1231         * score-datadep.h: New file.
1232         * score-inst.h: New file.
1233
1234 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
1235
1236         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1237         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1238         movdq2q and movq2dq.
1239
1240 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
1241            Michael Meissner             <michael.meissner@amd.com>
1242
1243         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1244
1245 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
1246
1247         * i386.h (i386_optab): Add "nop" with memory reference.
1248
1249 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
1250
1251         * i386.h (i386_optab): Update comment for 64bit NOP.
1252
1253 2006-06-06  Ben Elliston  <bje@au.ibm.com>
1254             Anton Blanchard  <anton@samba.org>
1255
1256         * ppc.h (PPC_OPCODE_POWER6): Define.
1257         Adjust whitespace.
1258
1259 2006-06-05  Thiemo Seufer  <ths@mips.com>
1260
1261         * mips.h: Improve description of MT flags.
1262
1263 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
1264
1265         * m68k.h (mcf_mask): Define.
1266
1267 2006-05-05  Thiemo Seufer  <ths@mips.com>
1268             David Ung  <davidu@mips.com>
1269
1270         * mips.h (enum): Add macro M_CACHE_AB.
1271
1272 2006-05-04  Thiemo Seufer  <ths@mips.com>
1273             Nigel Stephens  <nigel@mips.com>
1274             David Ung  <davidu@mips.com>
1275
1276         * mips.h: Add INSN_SMARTMIPS define.
1277
1278 2006-04-30  Thiemo Seufer  <ths@mips.com>
1279             David Ung  <davidu@mips.com>
1280
1281         * mips.h: Defines udi bits and masks.  Add description of
1282         characters which may appear in the args field of udi
1283         instructions.
1284
1285 2006-04-26  Thiemo Seufer  <ths@networkno.de>
1286
1287         * mips.h: Improve comments describing the bitfield instruction
1288         fields.
1289
1290 2006-04-26  Julian Brown  <julian@codesourcery.com>
1291
1292         * arm.h (FPU_VFP_EXT_V3): Define constant.
1293         (FPU_NEON_EXT_V1): Likewise.
1294         (FPU_VFP_HARD): Update.
1295         (FPU_VFP_V3): Define macro.
1296         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1297
1298 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
1299
1300         * avr.h (AVR_ISA_PWMx): New.
1301
1302 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
1303
1304         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1305         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1306         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1307         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1308         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1309
1310 2006-03-10  Paul Brook  <paul@codesourcery.com>
1311
1312         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1313
1314 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1315
1316         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1317         first.  Correct mask of bb "B" opcode.
1318
1319 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
1320
1321         * i386.h (i386_optab): Support Intel Merom New Instructions.
1322
1323 2006-02-24  Paul Brook  <paul@codesourcery.com>
1324
1325         * arm.h: Add V7 feature bits.
1326
1327 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
1328
1329         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1330
1331 2006-01-31  Paul Brook  <paul@codesourcery.com>
1332         Richard Earnshaw <rearnsha@arm.com>
1333
1334         * arm.h: Use ARM_CPU_FEATURE.
1335         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1336         (arm_feature_set): Change to a structure.
1337         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1338         ARM_FEATURE): New macros.
1339
1340 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
1341
1342         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1343         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1344         (ADD_PC_INCR_OPCODE): Don't define.
1345
1346 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
1347
1348         PR gas/1874
1349         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1350
1351 2005-11-14  David Ung  <davidu@mips.com>
1352
1353         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1354         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1355         save/restore encoding of the args field.
1356
1357 2005-10-28  Dave Brolley  <brolley@redhat.com>
1358
1359         Contribute the following changes:
1360         2005-02-16  Dave Brolley  <brolley@redhat.com>
1361
1362         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1363         cgen_isa_mask_* to cgen_bitset_*.
1364         * cgen.h: Likewise.
1365
1366         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
1367
1368         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1369         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1370         (CGEN_CPU_TABLE): Make isas a ponter.
1371
1372         2003-09-29  Dave Brolley  <brolley@redhat.com>
1373
1374         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1375         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1376         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1377
1378         2002-12-13  Dave Brolley  <brolley@redhat.com>
1379
1380         * cgen.h (symcat.h): #include it.
1381         (cgen-bitset.h): #include it.
1382         (CGEN_ATTR_VALUE_TYPE): Now a union.
1383         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1384         (CGEN_ATTR_ENTRY): 'value' now unsigned.
1385         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1386         * cgen-bitset.h: New file.
1387
1388 2005-09-30  Catherine Moore  <clm@cm00re.com>
1389
1390         * bfin.h: New file.
1391
1392 2005-10-24  Jan Beulich  <jbeulich@novell.com>
1393
1394         * ia64.h (enum ia64_opnd): Move memory operand out of set of
1395         indirect operands.
1396
1397 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1398
1399         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
1400         Add FLAG_STRICT to pa10 ftest opcode.
1401
1402 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1403
1404         * hppa.h (pa_opcodes): Remove lha entries.
1405
1406 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1407
1408         * hppa.h (FLAG_STRICT): Revise comment.
1409         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
1410         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
1411         entries for "fdc".
1412
1413 2005-09-30  Catherine Moore  <clm@cm00re.com>
1414
1415         * bfin.h: New file.
1416
1417 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1418
1419         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1420
1421 2005-09-06  Chao-ying Fu  <fu@mips.com>
1422
1423         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1424         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1425         define.
1426         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1427         (INSN_ASE_MASK): Update to include INSN_MT.
1428         (INSN_MT): New define for MT ASE.
1429
1430 2005-08-25  Chao-ying Fu  <fu@mips.com>
1431
1432         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1433         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1434         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1435         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1436         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1437         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1438         instructions.
1439         (INSN_DSP): New define for DSP ASE.
1440
1441 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
1442
1443         * a29k.h: Delete.
1444
1445 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
1446
1447         * ppc.h (PPC_OPCODE_E300): Define.
1448
1449 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
1450
1451         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1452
1453 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1454
1455         PR gas/336
1456         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1457         and pitlb.
1458
1459 2005-07-27  Jan Beulich  <jbeulich@novell.com>
1460
1461         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1462         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1463         Add movq-s as 64-bit variants of movd-s.
1464
1465 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1466
1467         * hppa.h: Fix punctuation in comment.
1468
1469         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
1470         implicit space-register addressing.  Set space-register bits on opcodes
1471         using implicit space-register addressing.  Add various missing pa20
1472         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
1473         space-register addressing.  Use "fE" instead of "fe" in various
1474         fstw opcodes.
1475
1476 2005-07-18  Jan Beulich  <jbeulich@novell.com>
1477
1478         * i386.h (i386_optab): Operands of aam and aad are unsigned.
1479
1480 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
1481
1482         * i386.h (i386_optab): Support Intel VMX Instructions.
1483
1484 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1485
1486         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1487
1488 2005-07-05  Jan Beulich  <jbeulich@novell.com>
1489
1490         * i386.h (i386_optab): Add new insns.
1491
1492 2005-07-01  Nick Clifton  <nickc@redhat.com>
1493
1494         * sparc.h: Add typedefs to structure declarations.
1495
1496 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
1497
1498         PR 1013
1499         * i386.h (i386_optab): Update comments for 64bit addressing on
1500         mov. Allow 64bit addressing for mov and movq.
1501
1502 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1503
1504         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1505         respectively, in various floating-point load and store patterns.
1506
1507 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1508
1509         * hppa.h (FLAG_STRICT): Correct comment.
1510         (pa_opcodes): Update load and store entries to allow both PA 1.X and
1511         PA 2.0 mneumonics when equivalent.  Entries with cache control
1512         completers now require PA 1.1.  Adjust whitespace.
1513
1514 2005-05-19  Anton Blanchard  <anton@samba.org>
1515
1516         * ppc.h (PPC_OPCODE_POWER5): Define.
1517
1518 2005-05-10  Nick Clifton  <nickc@redhat.com>
1519
1520         * Update the address and phone number of the FSF organization in
1521         the GPL notices in the following files:
1522         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1523         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1524         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1525         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1526         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1527         tic54x.h, tic80.h, v850.h, vax.h
1528
1529 2005-05-09  Jan Beulich  <jbeulich@novell.com>
1530
1531         * i386.h (i386_optab): Add ht and hnt.
1532
1533 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
1534
1535         * i386.h: Insert hyphens into selected VIA PadLock extensions.
1536         Add xcrypt-ctr.  Provide aliases without hyphens.
1537
1538 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
1539
1540         Moved from ../ChangeLog
1541
1542         2005-04-12  Paul Brook  <paul@codesourcery.com>
1543         * m88k.h: Rename psr macros to avoid conflicts.
1544
1545         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
1546         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1547         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1548         and ARM_ARCH_V6ZKT2.
1549
1550         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
1551         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1552         Remove redundant instruction types.
1553         (struct argument): X_op - new field.
1554         (struct cst4_entry): Remove.
1555         (no_op_insn): Declare.
1556
1557         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
1558         * crx.h (enum argtype): Rename types, remove unused types.
1559
1560         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
1561         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1562         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1563         (enum operand_type): Rearrange operands, edit comments.
1564         replace us<N> with ui<N> for unsigned immediate.
1565         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1566         displacements (respectively).
1567         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1568         (instruction type): Add NO_TYPE_INS.
1569         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1570         (operand_entry): New field - 'flags'.
1571         (operand flags): New.
1572
1573         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
1574         * crx.h (operand_type): Remove redundant types i3, i4,
1575         i5, i8, i12.
1576         Add new unsigned immediate types us3, us4, us5, us16.
1577
1578 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
1579
1580         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1581         adjust them accordingly.
1582
1583 2005-04-01  Jan Beulich  <jbeulich@novell.com>
1584
1585         * i386.h (i386_optab): Add rdtscp.
1586
1587 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
1588
1589         * i386.h (i386_optab): Don't allow the `l' suffix for moving
1590         between memory and segment register. Allow movq for moving between
1591         general-purpose register and segment register.
1592
1593 2005-02-09  Jan Beulich  <jbeulich@novell.com>
1594
1595         PR gas/707
1596         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1597         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1598         fnstsw.
1599
1600 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
1601
1602         * m68k.h (m68008, m68ec030, m68882): Remove.
1603         (m68k_mask): New.
1604         (cpu_m68k, cpu_cf): New.
1605         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1606         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1607
1608 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
1609
1610         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
1611         * cgen.h (enum cgen_parse_operand_type): Add
1612         CGEN_PARSE_OPERAND_SYMBOLIC.
1613
1614 2005-01-21  Fred Fish  <fnf@specifixinc.com>
1615
1616         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1617         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1618         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1619
1620 2005-01-19  Fred Fish  <fnf@specifixinc.com>
1621
1622         * mips.h (struct mips_opcode): Add new pinfo2 member.
1623         (INSN_ALIAS): New define for opcode table entries that are
1624         specific instances of another entry, such as 'move' for an 'or'
1625         with a zero operand.
1626         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1627         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1628
1629 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
1630
1631         * mips.h (CPU_RM9000): Define.
1632         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1633
1634 2004-11-25 Jan Beulich  <jbeulich@novell.com>
1635
1636         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1637         to/from test registers are illegal in 64-bit mode. Add missing
1638         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1639         (previously one had to explicitly encode a rex64 prefix). Re-enable
1640         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1641         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1642
1643 2004-11-23 Jan Beulich  <jbeulich@novell.com>
1644
1645         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1646         available only with SSE2. Change the MMX additions introduced by SSE
1647         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1648         instructions by their now designated identifier (since combining i686
1649         and 3DNow! does not really imply 3DNow!A).
1650
1651 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
1652
1653         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1654         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1655
1656 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
1657             Vineet Sharma      <vineets@noida.hcltech.com>
1658
1659         * maxq.h: New file: Disassembly information for the maxq port.
1660
1661 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
1662
1663         * i386.h (i386_optab): Put back "movzb".
1664
1665 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
1666
1667         * cris.h (enum cris_insn_version_usage): Tweak formatting and
1668         comments.  Remove member cris_ver_sim.  Add members
1669         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1670         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1671         (struct cris_support_reg, struct cris_cond15): New types.
1672         (cris_conds15): Declare.
1673         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1674         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1675         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1676         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1677         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1678         SIZE_FIELD_UNSIGNED.
1679
1680 2004-11-04 Jan Beulich  <jbeulich@novell.com>
1681
1682         * i386.h (sldx_Suf): Remove.
1683         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1684         (q_FP): Define, implying no REX64.
1685         (x_FP, sl_FP): Imply FloatMF.
1686         (i386_optab): Split reg and mem forms of moving from segment registers
1687         so that the memory forms can ignore the 16-/32-bit operand size
1688         distinction. Adjust a few others for Intel mode. Remove *FP uses from
1689         all non-floating-point instructions. Unite 32- and 64-bit forms of
1690         movsx, movzx, and movd. Adjust floating point operations for the above
1691         changes to the *FP macros. Add DefaultSize to floating point control
1692         insns operating on larger memory ranges. Remove left over comments
1693         hinting at certain insns being Intel-syntax ones where the ones
1694         actually meant are already gone.
1695
1696 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
1697
1698         * crx.h: Add COPS_REG_INS - Coprocessor Special register
1699         instruction type.
1700
1701 2004-09-30  Paul Brook  <paul@codesourcery.com>
1702
1703         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1704         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1705
1706 2004-09-11  Theodore A. Roth  <troth@openavr.org>
1707
1708         * avr.h: Add support for
1709         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1710
1711 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
1712
1713         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1714
1715 2004-08-24  Dmitry Diky  <diwil@spec.ru>
1716
1717         * msp430.h (msp430_opc): Add new instructions.
1718         (msp430_rcodes): Declare new instructions.
1719         (msp430_hcodes): Likewise..
1720
1721 2004-08-13  Nick Clifton  <nickc@redhat.com>
1722
1723         PR/301
1724         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1725         processors.
1726
1727 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
1728
1729         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1730
1731 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
1732
1733         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1734
1735 2004-07-21  Jan Beulich  <jbeulich@novell.com>
1736
1737         * i386.h: Adjust instruction descriptions to better match the
1738         specification.
1739
1740 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
1741
1742         * arm.h: Remove all old content.  Replace with architecture defines
1743         from gas/config/tc-arm.c.
1744
1745 2004-07-09  Andreas Schwab  <schwab@suse.de>
1746
1747         * m68k.h: Fix comment.
1748
1749 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
1750
1751         * crx.h: New file.
1752
1753 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
1754
1755         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1756
1757 2004-05-24  Peter Barada  <peter@the-baradas.com>
1758
1759         * m68k.h: Add 'size' to m68k_opcode.
1760
1761 2004-05-05  Peter Barada  <peter@the-baradas.com>
1762
1763         * m68k.h: Switch from ColdFire chip name to core variant.
1764
1765 2004-04-22  Peter Barada  <peter@the-baradas.com>
1766
1767         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
1768         descriptions for new EMAC cases.
1769         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1770         handle Motorola MAC syntax.
1771         Allow disassembly of ColdFire V4e object files.
1772
1773 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
1774
1775         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
1776
1777 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
1778
1779         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1780
1781 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1782
1783         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1784
1785 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1786
1787         * i386.h (i386_optab): Added xstore/xcrypt insns.
1788
1789 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1790
1791         * h8300.h (32bit ldc/stc): Add relaxing support.
1792
1793 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
1794
1795         * h8300.h (BITOP): Pass MEMRELAX flag.
1796
1797 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1798
1799         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1800         except for the H8S.
1801
1802 For older changes see ChangeLog-9103
1803 \f
1804 Copyright (C) 2004-2012 Free Software Foundation, Inc.
1805
1806 Copying and distribution of this file, with or without modification,
1807 are permitted in any medium without royalty provided the copyright
1808 notice and this notice are preserved.
1809
1810 Local Variables:
1811 mode: change-log
1812 left-margin: 8
1813 fill-column: 74
1814 version-control: never
1815 End: