1 2011-08-09 Chao-ying Fu <fu@mips.com>
2 Maciej W. Rozycki <macro@codesourcery.com>
4 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
5 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
6 (INSN_ASE_MASK): Add the MCU bit.
8 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
9 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
11 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
13 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
14 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
15 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
16 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
17 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
18 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
19 (INSN2_READ_GPR_MMN): Likewise.
20 (INSN2_READ_FPR_D): Change the bit used.
21 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
22 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
23 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
24 (INSN2_COND_BRANCH): Likewise.
25 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
26 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
27 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
28 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
29 (INSN2_MOD_GPR_MN): Likewise.
31 2011-08-05 David S. Miller <davem@davemloft.net>
33 * sparc.h: Document new format codes '4', '5', and '('.
34 (OPF_LOW4, RS3): New macros.
36 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
38 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
39 order of flags documented.
41 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
43 * mips.h: Clarify the description of microMIPS instruction
45 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
47 2011-07-24 Chao-ying Fu <fu@mips.com>
48 Maciej W. Rozycki <macro@codesourcery.com>
50 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
51 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
52 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
53 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
54 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
55 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
56 (OP_MASK_RS3, OP_SH_RS3): Likewise.
57 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
58 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
59 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
60 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
61 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
62 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
63 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
64 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
65 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
66 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
67 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
68 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
69 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
70 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
71 (INSN_WRITE_GPR_S): New macro.
72 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
73 (INSN2_READ_FPR_D): Likewise.
74 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
75 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
76 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
77 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
78 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
79 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
80 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
81 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
82 (CPU_MICROMIPS): New macro.
83 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
84 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
85 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
86 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
87 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
88 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
89 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
90 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
91 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
92 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
93 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
94 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
95 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
96 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
97 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
98 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
99 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
100 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
101 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
102 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
103 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
104 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
105 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
106 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
107 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
108 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
109 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
110 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
111 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
112 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
113 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
114 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
115 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
116 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
117 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
118 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
119 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
120 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
121 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
122 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
123 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
124 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
125 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
126 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
127 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
128 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
129 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
130 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
131 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
132 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
133 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
134 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
135 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
136 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
137 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
138 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
139 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
140 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
141 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
142 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
143 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
144 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
145 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
146 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
147 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
148 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
149 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
150 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
151 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
152 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
153 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
154 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
155 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
156 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
157 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
158 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
159 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
160 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
161 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
162 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
163 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
164 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
165 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
166 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
167 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
168 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
169 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
170 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
171 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
172 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
173 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
174 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
175 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
176 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
177 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
178 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
179 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
180 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
181 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
182 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
183 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
184 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
185 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
186 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
187 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
188 (micromips_opcodes): New declaration.
189 (bfd_micromips_num_opcodes): Likewise.
191 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
193 * mips.h (INSN_TRAP): Rename to...
194 (INSN_NO_DELAY_SLOT): ... this.
195 (INSN_SYNC): Remove macro.
197 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
199 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
200 a duplicate of AVR_ISA_SPM.
202 2011-07-01 Nick Clifton <nickc@redhat.com>
204 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
206 2011-06-18 Robin Getz <robin.getz@analog.com>
208 * bfin.h (is_macmod_signed): New func
210 2011-06-18 Mike Frysinger <vapier@gentoo.org>
212 * bfin.h (is_macmod_pmove): Add missing space before func args.
213 (is_macmod_hmove): Likewise.
215 2011-06-13 Walter Lee <walt@tilera.com>
217 * tilegx.h: New file.
218 * tilepro.h: New file.
220 2011-05-31 Paul Brook <paul@codesourcery.com>
222 * arm.h (ARM_ARCH_V7R_IDIV): Define.
224 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
226 * s390.h: Replace S390_OPERAND_REG_EVEN with
227 S390_OPERAND_REG_PAIR.
229 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
231 * s390.h: Add S390_OPCODE_REG_EVEN flag.
233 2011-04-18 Julian Brown <julian@codesourcery.com>
235 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
237 2011-04-11 Dan McDonald <dan@wellkeeper.com>
240 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
242 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
244 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
245 New instruction set flags.
246 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
248 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
250 * mips.h (M_PREF_AB): New enum value.
252 2011-02-12 Mike Frysinger <vapier@gentoo.org>
254 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
256 (is_macmod_pmove, is_macmod_hmove): New functions.
258 2011-02-11 Mike Frysinger <vapier@gentoo.org>
260 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
262 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
264 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
265 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
267 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
270 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
273 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
276 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
278 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
280 * mips.h: Update commentary after last commit.
282 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
284 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
285 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
286 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
288 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
290 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
292 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
294 * mips.h: Fix previous commit.
296 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
298 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
299 (INSN_LOONGSON_3A): Clear bit 31.
301 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
304 * arm.h (ARM_AEXT_V6M_ONLY): New define.
305 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
306 (ARM_ARCH_V6M_ONLY): New define.
308 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
310 * mips.h (INSN_LOONGSON_3A): Defined.
311 (CPU_LOONGSON_3A): Defined.
312 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
314 2010-10-09 Matt Rice <ratmice@gmail.com>
316 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
317 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
319 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
321 * arm.h (ARM_EXT_VIRT): New define.
322 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
323 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
326 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
328 * arm.h (ARM_AEXT_ADIV): New define.
329 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
331 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
333 * arm.h (ARM_EXT_OS): New define.
334 (ARM_AEXT_V6SM): Likewise.
335 (ARM_ARCH_V6SM): Likewise.
337 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
339 * arm.h (ARM_EXT_MP): Add.
340 (ARM_ARCH_V7A_MP): Likewise.
342 2010-09-22 Mike Frysinger <vapier@gentoo.org>
344 * bfin.h: Declare pseudoChr structs/defines.
346 2010-09-21 Mike Frysinger <vapier@gentoo.org>
348 * bfin.h: Strip trailing whitespace.
350 2010-07-29 DJ Delorie <dj@redhat.com>
352 * rx.h (RX_Operand_Type): Add TwoReg.
353 (RX_Opcode_ID): Remove ediv and ediv2.
355 2010-07-27 DJ Delorie <dj@redhat.com>
357 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
359 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
360 Ina Pandit <ina.pandit@kpitcummins.com>
362 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
363 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
364 PROCESSOR_V850E2_ALL.
365 Remove PROCESSOR_V850EA support.
366 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
367 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
368 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
369 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
370 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
371 V850_OPERAND_PERCENT.
372 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
374 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
377 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
379 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
380 (MIPS16_INSN_BRANCH): Rename to...
381 (MIPS16_INSN_COND_BRANCH): ... this.
383 2010-07-03 Alan Modra <amodra@gmail.com>
385 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
386 Renumber other PPC_OPCODE defines.
388 2010-07-03 Alan Modra <amodra@gmail.com>
390 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
392 2010-06-29 Alan Modra <amodra@gmail.com>
394 * maxq.h: Delete file.
396 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
398 * ppc.h (PPC_OPCODE_E500): Define.
400 2010-05-26 Catherine Moore <clm@codesourcery.com>
402 * opcode/mips.h (INSN_MIPS16): Remove.
404 2010-04-21 Joseph Myers <joseph@codesourcery.com>
406 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
408 2010-04-15 Nick Clifton <nickc@redhat.com>
410 * alpha.h: Update copyright notice to use GPLv3.
416 * convex.h: Likewise.
430 * m68hc11.h: Likewise.
436 * mn10200.h: Likewise.
437 * mn10300.h: Likewise.
438 * msp430.h: Likewise.
449 * score-datadep.h: Likewise.
450 * score-inst.h: Likewise.
452 * spu-insns.h: Likewise.
456 * tic54x.h: Likewise.
461 2010-03-25 Joseph Myers <joseph@codesourcery.com>
463 * tic6x-control-registers.h, tic6x-insn-formats.h,
464 tic6x-opcode-table.h, tic6x.h: New.
466 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
468 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
470 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
472 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
474 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
476 * ia64.h (ia64_find_opcode): Remove argument name.
477 (ia64_find_next_opcode): Likewise.
478 (ia64_dis_opcode): Likewise.
479 (ia64_free_opcode): Likewise.
480 (ia64_find_dependency): Likewise.
482 2009-11-22 Doug Evans <dje@sebabeach.org>
484 * cgen.h: Include bfd_stdint.h.
485 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
487 2009-11-18 Paul Brook <paul@codesourcery.com>
489 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
491 2009-11-17 Paul Brook <paul@codesourcery.com>
492 Daniel Jacobowitz <dan@codesourcery.com>
494 * arm.h (ARM_EXT_V6_DSP): Define.
495 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
496 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
498 2009-11-04 DJ Delorie <dj@redhat.com>
500 * rx.h (rx_decode_opcode) (mvtipl): Add.
501 (mvtcp, mvfcp, opecp): Remove.
503 2009-11-02 Paul Brook <paul@codesourcery.com>
505 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
506 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
507 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
508 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
509 FPU_ARCH_NEON_VFP_V4): Define.
511 2009-10-23 Doug Evans <dje@sebabeach.org>
513 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
514 * cgen.h: Update. Improve multi-inclusion macro name.
516 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
518 * ppc.h (PPC_OPCODE_476): Define.
520 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
522 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
524 2009-09-29 DJ Delorie <dj@redhat.com>
528 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
530 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
532 2009-09-21 Ben Elliston <bje@au.ibm.com>
534 * ppc.h (PPC_OPCODE_PPCA2): New.
536 2009-09-05 Martin Thuresson <martin@mtme.org>
538 * ia64.h (struct ia64_operand): Renamed member class to op_class.
540 2009-08-29 Martin Thuresson <martin@mtme.org>
542 * tic30.h (template): Rename type template to
543 insn_template. Updated code to use new name.
544 * tic54x.h (template): Rename type template to
547 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
549 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
551 2009-06-11 Anthony Green <green@moxielogic.com>
553 * moxie.h (MOXIE_F3_PCREL): Define.
554 (moxie_form3_opc_info): Grow.
556 2009-06-06 Anthony Green <green@moxielogic.com>
558 * moxie.h (MOXIE_F1_M): Define.
560 2009-04-15 Anthony Green <green@moxielogic.com>
564 2009-04-06 DJ Delorie <dj@redhat.com>
566 * h8300.h: Add relaxation attributes to MOVA opcodes.
568 2009-03-10 Alan Modra <amodra@bigpond.net.au>
570 * ppc.h (ppc_parse_cpu): Declare.
572 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
574 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
575 and _IMM11 for mbitclr and mbitset.
576 * score-datadep.h: Update dependency information.
578 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
580 * ppc.h (PPC_OPCODE_POWER7): New.
582 2009-02-06 Doug Evans <dje@google.com>
584 * i386.h: Add comment regarding sse* insns and prefixes.
586 2009-02-03 Sandip Matte <sandip@rmicorp.com>
588 * mips.h (INSN_XLR): Define.
589 (INSN_CHIP_MASK): Update.
591 (OPCODE_IS_MEMBER): Update.
592 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
594 2009-01-28 Doug Evans <dje@google.com>
596 * opcode/i386.h: Add multiple inclusion protection.
597 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
598 (EDI_REG_NUM): New macros.
599 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
600 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
601 (REX_PREFIX_P): New macro.
603 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
605 * ppc.h (struct powerpc_opcode): New field "deprecated".
606 (PPC_OPCODE_NOPOWER4): Delete.
608 2008-11-28 Joshua Kinard <kumba@gentoo.org>
610 * mips.h: Define CPU_R14000, CPU_R16000.
611 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
613 2008-11-18 Catherine Moore <clm@codesourcery.com>
615 * arm.h (FPU_NEON_FP16): New.
616 (FPU_ARCH_NEON_FP16): New.
618 2008-11-06 Chao-ying Fu <fu@mips.com>
620 * mips.h: Doucument '1' for 5-bit sync type.
622 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
624 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
627 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
629 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
631 2008-07-30 Michael J. Eager <eager@eagercon.com>
633 * ppc.h (PPC_OPCODE_405): Define.
634 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
636 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
638 * ppc.h (ppc_cpu_t): New typedef.
639 (struct powerpc_opcode <flags>): Use it.
640 (struct powerpc_operand <insert, extract>): Likewise.
641 (struct powerpc_macro <flags>): Likewise.
643 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
645 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
646 Update comment before MIPS16 field descriptors to mention MIPS16.
647 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
649 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
650 New bit masks and shift counts for cins and exts.
652 * mips.h: Document new field descriptors +Q.
653 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
655 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
657 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
658 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
660 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
662 * ppc.h: (PPC_OPCODE_E500MC): New.
664 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
666 * i386.h (MAX_OPERANDS): Set to 5.
667 (MAX_MNEM_SIZE): Changed to 20.
669 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
671 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
673 2008-03-09 Paul Brook <paul@codesourcery.com>
675 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
677 2008-03-04 Paul Brook <paul@codesourcery.com>
679 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
680 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
681 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
683 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
684 Nick Clifton <nickc@redhat.com>
687 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
688 with a 32-bit displacement but without the top bit of the 4th byte
691 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
693 * cr16.h (cr16_num_optab): Declared.
695 2008-02-14 Hakan Ardo <hakan@debian.org>
698 * avr.h (AVR_ISA_2xxe): Define.
700 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
702 * mips.h: Update copyright.
703 (INSN_CHIP_MASK): New macro.
704 (INSN_OCTEON): New macro.
705 (CPU_OCTEON): New macro.
706 (OPCODE_IS_MEMBER): Handle Octeon instructions.
708 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
710 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
712 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
714 * avr.h (AVR_ISA_USB162): Add new opcode set.
715 (AVR_ISA_AVR3): Likewise.
717 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
719 * mips.h (INSN_LOONGSON_2E): New.
720 (INSN_LOONGSON_2F): New.
721 (CPU_LOONGSON_2E): New.
722 (CPU_LOONGSON_2F): New.
723 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
725 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
727 * mips.h (INSN_ISA*): Redefine certain values as an
728 enumeration. Update comments.
729 (mips_isa_table): New.
730 (ISA_MIPS*): Redefine to match enumeration.
731 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
734 2007-08-08 Ben Elliston <bje@au.ibm.com>
736 * ppc.h (PPC_OPCODE_PPCPS): New.
738 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
740 * m68k.h: Document j K & E.
742 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
744 * cr16.h: New file for CR16 target.
746 2007-05-02 Alan Modra <amodra@bigpond.net.au>
748 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
750 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
752 * m68k.h (mcfisa_c): New.
753 (mcfusp, mcf_mask): Adjust.
755 2007-04-20 Alan Modra <amodra@bigpond.net.au>
757 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
758 (num_powerpc_operands): Declare.
759 (PPC_OPERAND_SIGNED et al): Redefine as hex.
760 (PPC_OPERAND_PLUS1): Define.
762 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
764 * i386.h (REX_MODE64): Renamed to ...
766 (REX_EXTX): Renamed to ...
768 (REX_EXTY): Renamed to ...
770 (REX_EXTZ): Renamed to ...
773 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
775 * i386.h: Add entries from config/tc-i386.h and move tables
776 to opcodes/i386-opc.h.
778 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
780 * i386.h (FloatDR): Removed.
781 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
783 2007-03-01 Alan Modra <amodra@bigpond.net.au>
785 * spu-insns.h: Add soma double-float insns.
787 2007-02-20 Thiemo Seufer <ths@mips.com>
788 Chao-Ying Fu <fu@mips.com>
790 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
791 (INSN_DSPR2): Add flag for DSP R2 instructions.
792 (M_BALIGN): New macro.
794 2007-02-14 Alan Modra <amodra@bigpond.net.au>
796 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
797 and Seg3ShortFrom with Shortform.
799 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
802 * i386.h (i386_optab): Put the real "test" before the pseudo
805 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
807 * m68k.h (m68010up): OR fido_a.
809 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
811 * m68k.h (fido_a): New.
813 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
815 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
816 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
819 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
821 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
823 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
825 * score-inst.h (enum score_insn_type): Add Insn_internal.
827 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
828 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
829 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
830 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
831 Alan Modra <amodra@bigpond.net.au>
833 * spu-insns.h: New file.
836 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
838 * ppc.h (PPC_OPCODE_CELL): Define.
840 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
842 * i386.h : Modify opcode to support for the change in POPCNT opcode
843 in amdfam10 architecture.
845 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
847 * i386.h: Replace CpuMNI with CpuSSSE3.
849 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
850 Joseph Myers <joseph@codesourcery.com>
851 Ian Lance Taylor <ian@wasabisystems.com>
852 Ben Elliston <bje@wasabisystems.com>
854 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
856 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
858 * score-datadep.h: New file.
859 * score-inst.h: New file.
861 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
863 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
864 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
867 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
868 Michael Meissner <michael.meissner@amd.com>
870 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
872 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
874 * i386.h (i386_optab): Add "nop" with memory reference.
876 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
878 * i386.h (i386_optab): Update comment for 64bit NOP.
880 2006-06-06 Ben Elliston <bje@au.ibm.com>
881 Anton Blanchard <anton@samba.org>
883 * ppc.h (PPC_OPCODE_POWER6): Define.
886 2006-06-05 Thiemo Seufer <ths@mips.com>
888 * mips.h: Improve description of MT flags.
890 2006-05-25 Richard Sandiford <richard@codesourcery.com>
892 * m68k.h (mcf_mask): Define.
894 2006-05-05 Thiemo Seufer <ths@mips.com>
895 David Ung <davidu@mips.com>
897 * mips.h (enum): Add macro M_CACHE_AB.
899 2006-05-04 Thiemo Seufer <ths@mips.com>
900 Nigel Stephens <nigel@mips.com>
901 David Ung <davidu@mips.com>
903 * mips.h: Add INSN_SMARTMIPS define.
905 2006-04-30 Thiemo Seufer <ths@mips.com>
906 David Ung <davidu@mips.com>
908 * mips.h: Defines udi bits and masks. Add description of
909 characters which may appear in the args field of udi
912 2006-04-26 Thiemo Seufer <ths@networkno.de>
914 * mips.h: Improve comments describing the bitfield instruction
917 2006-04-26 Julian Brown <julian@codesourcery.com>
919 * arm.h (FPU_VFP_EXT_V3): Define constant.
920 (FPU_NEON_EXT_V1): Likewise.
921 (FPU_VFP_HARD): Update.
922 (FPU_VFP_V3): Define macro.
923 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
925 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
927 * avr.h (AVR_ISA_PWMx): New.
929 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
931 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
932 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
933 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
934 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
935 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
937 2006-03-10 Paul Brook <paul@codesourcery.com>
939 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
941 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
943 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
944 first. Correct mask of bb "B" opcode.
946 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
948 * i386.h (i386_optab): Support Intel Merom New Instructions.
950 2006-02-24 Paul Brook <paul@codesourcery.com>
952 * arm.h: Add V7 feature bits.
954 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
956 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
958 2006-01-31 Paul Brook <paul@codesourcery.com>
959 Richard Earnshaw <rearnsha@arm.com>
961 * arm.h: Use ARM_CPU_FEATURE.
962 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
963 (arm_feature_set): Change to a structure.
964 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
965 ARM_FEATURE): New macros.
967 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
969 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
970 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
971 (ADD_PC_INCR_OPCODE): Don't define.
973 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
976 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
978 2005-11-14 David Ung <davidu@mips.com>
980 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
981 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
982 save/restore encoding of the args field.
984 2005-10-28 Dave Brolley <brolley@redhat.com>
986 Contribute the following changes:
987 2005-02-16 Dave Brolley <brolley@redhat.com>
989 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
990 cgen_isa_mask_* to cgen_bitset_*.
993 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
995 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
996 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
997 (CGEN_CPU_TABLE): Make isas a ponter.
999 2003-09-29 Dave Brolley <brolley@redhat.com>
1001 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1002 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1003 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1005 2002-12-13 Dave Brolley <brolley@redhat.com>
1007 * cgen.h (symcat.h): #include it.
1008 (cgen-bitset.h): #include it.
1009 (CGEN_ATTR_VALUE_TYPE): Now a union.
1010 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1011 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1012 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1013 * cgen-bitset.h: New file.
1015 2005-09-30 Catherine Moore <clm@cm00re.com>
1019 2005-10-24 Jan Beulich <jbeulich@novell.com>
1021 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1024 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1026 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1027 Add FLAG_STRICT to pa10 ftest opcode.
1029 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1031 * hppa.h (pa_opcodes): Remove lha entries.
1033 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1035 * hppa.h (FLAG_STRICT): Revise comment.
1036 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1037 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1040 2005-09-30 Catherine Moore <clm@cm00re.com>
1044 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1046 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1048 2005-09-06 Chao-ying Fu <fu@mips.com>
1050 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1051 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1053 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1054 (INSN_ASE_MASK): Update to include INSN_MT.
1055 (INSN_MT): New define for MT ASE.
1057 2005-08-25 Chao-ying Fu <fu@mips.com>
1059 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1060 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1061 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1062 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1063 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1064 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1066 (INSN_DSP): New define for DSP ASE.
1068 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1072 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1074 * ppc.h (PPC_OPCODE_E300): Define.
1076 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1078 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1080 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1083 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1086 2005-07-27 Jan Beulich <jbeulich@novell.com>
1088 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1089 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1090 Add movq-s as 64-bit variants of movd-s.
1092 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1094 * hppa.h: Fix punctuation in comment.
1096 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1097 implicit space-register addressing. Set space-register bits on opcodes
1098 using implicit space-register addressing. Add various missing pa20
1099 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1100 space-register addressing. Use "fE" instead of "fe" in various
1103 2005-07-18 Jan Beulich <jbeulich@novell.com>
1105 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1107 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1109 * i386.h (i386_optab): Support Intel VMX Instructions.
1111 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1113 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1115 2005-07-05 Jan Beulich <jbeulich@novell.com>
1117 * i386.h (i386_optab): Add new insns.
1119 2005-07-01 Nick Clifton <nickc@redhat.com>
1121 * sparc.h: Add typedefs to structure declarations.
1123 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1126 * i386.h (i386_optab): Update comments for 64bit addressing on
1127 mov. Allow 64bit addressing for mov and movq.
1129 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1131 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1132 respectively, in various floating-point load and store patterns.
1134 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1136 * hppa.h (FLAG_STRICT): Correct comment.
1137 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1138 PA 2.0 mneumonics when equivalent. Entries with cache control
1139 completers now require PA 1.1. Adjust whitespace.
1141 2005-05-19 Anton Blanchard <anton@samba.org>
1143 * ppc.h (PPC_OPCODE_POWER5): Define.
1145 2005-05-10 Nick Clifton <nickc@redhat.com>
1147 * Update the address and phone number of the FSF organization in
1148 the GPL notices in the following files:
1149 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1150 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1151 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1152 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1153 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1154 tic54x.h, tic80.h, v850.h, vax.h
1156 2005-05-09 Jan Beulich <jbeulich@novell.com>
1158 * i386.h (i386_optab): Add ht and hnt.
1160 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1162 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1163 Add xcrypt-ctr. Provide aliases without hyphens.
1165 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1167 Moved from ../ChangeLog
1169 2005-04-12 Paul Brook <paul@codesourcery.com>
1170 * m88k.h: Rename psr macros to avoid conflicts.
1172 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1173 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1174 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1175 and ARM_ARCH_V6ZKT2.
1177 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1178 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1179 Remove redundant instruction types.
1180 (struct argument): X_op - new field.
1181 (struct cst4_entry): Remove.
1182 (no_op_insn): Declare.
1184 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1185 * crx.h (enum argtype): Rename types, remove unused types.
1187 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1188 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1189 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1190 (enum operand_type): Rearrange operands, edit comments.
1191 replace us<N> with ui<N> for unsigned immediate.
1192 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1193 displacements (respectively).
1194 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1195 (instruction type): Add NO_TYPE_INS.
1196 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1197 (operand_entry): New field - 'flags'.
1198 (operand flags): New.
1200 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1201 * crx.h (operand_type): Remove redundant types i3, i4,
1203 Add new unsigned immediate types us3, us4, us5, us16.
1205 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1207 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1208 adjust them accordingly.
1210 2005-04-01 Jan Beulich <jbeulich@novell.com>
1212 * i386.h (i386_optab): Add rdtscp.
1214 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1216 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1217 between memory and segment register. Allow movq for moving between
1218 general-purpose register and segment register.
1220 2005-02-09 Jan Beulich <jbeulich@novell.com>
1223 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1224 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1227 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1229 * m68k.h (m68008, m68ec030, m68882): Remove.
1231 (cpu_m68k, cpu_cf): New.
1232 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1233 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1235 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1237 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1238 * cgen.h (enum cgen_parse_operand_type): Add
1239 CGEN_PARSE_OPERAND_SYMBOLIC.
1241 2005-01-21 Fred Fish <fnf@specifixinc.com>
1243 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1244 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1245 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1247 2005-01-19 Fred Fish <fnf@specifixinc.com>
1249 * mips.h (struct mips_opcode): Add new pinfo2 member.
1250 (INSN_ALIAS): New define for opcode table entries that are
1251 specific instances of another entry, such as 'move' for an 'or'
1252 with a zero operand.
1253 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1254 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1256 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1258 * mips.h (CPU_RM9000): Define.
1259 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1261 2004-11-25 Jan Beulich <jbeulich@novell.com>
1263 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1264 to/from test registers are illegal in 64-bit mode. Add missing
1265 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1266 (previously one had to explicitly encode a rex64 prefix). Re-enable
1267 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1268 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1270 2004-11-23 Jan Beulich <jbeulich@novell.com>
1272 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1273 available only with SSE2. Change the MMX additions introduced by SSE
1274 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1275 instructions by their now designated identifier (since combining i686
1276 and 3DNow! does not really imply 3DNow!A).
1278 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1280 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1281 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1283 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1284 Vineet Sharma <vineets@noida.hcltech.com>
1286 * maxq.h: New file: Disassembly information for the maxq port.
1288 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1290 * i386.h (i386_optab): Put back "movzb".
1292 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1294 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1295 comments. Remove member cris_ver_sim. Add members
1296 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1297 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1298 (struct cris_support_reg, struct cris_cond15): New types.
1299 (cris_conds15): Declare.
1300 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1301 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1302 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1303 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1304 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1305 SIZE_FIELD_UNSIGNED.
1307 2004-11-04 Jan Beulich <jbeulich@novell.com>
1309 * i386.h (sldx_Suf): Remove.
1310 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1311 (q_FP): Define, implying no REX64.
1312 (x_FP, sl_FP): Imply FloatMF.
1313 (i386_optab): Split reg and mem forms of moving from segment registers
1314 so that the memory forms can ignore the 16-/32-bit operand size
1315 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1316 all non-floating-point instructions. Unite 32- and 64-bit forms of
1317 movsx, movzx, and movd. Adjust floating point operations for the above
1318 changes to the *FP macros. Add DefaultSize to floating point control
1319 insns operating on larger memory ranges. Remove left over comments
1320 hinting at certain insns being Intel-syntax ones where the ones
1321 actually meant are already gone.
1323 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1325 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1328 2004-09-30 Paul Brook <paul@codesourcery.com>
1330 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1331 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1333 2004-09-11 Theodore A. Roth <troth@openavr.org>
1335 * avr.h: Add support for
1336 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1338 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1340 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1342 2004-08-24 Dmitry Diky <diwil@spec.ru>
1344 * msp430.h (msp430_opc): Add new instructions.
1345 (msp430_rcodes): Declare new instructions.
1346 (msp430_hcodes): Likewise..
1348 2004-08-13 Nick Clifton <nickc@redhat.com>
1351 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1354 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1356 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1358 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1360 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1362 2004-07-21 Jan Beulich <jbeulich@novell.com>
1364 * i386.h: Adjust instruction descriptions to better match the
1367 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1369 * arm.h: Remove all old content. Replace with architecture defines
1370 from gas/config/tc-arm.c.
1372 2004-07-09 Andreas Schwab <schwab@suse.de>
1374 * m68k.h: Fix comment.
1376 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1380 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1382 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1384 2004-05-24 Peter Barada <peter@the-baradas.com>
1386 * m68k.h: Add 'size' to m68k_opcode.
1388 2004-05-05 Peter Barada <peter@the-baradas.com>
1390 * m68k.h: Switch from ColdFire chip name to core variant.
1392 2004-04-22 Peter Barada <peter@the-baradas.com>
1394 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1395 descriptions for new EMAC cases.
1396 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1397 handle Motorola MAC syntax.
1398 Allow disassembly of ColdFire V4e object files.
1400 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1402 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1404 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1406 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1408 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1410 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1412 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1414 * i386.h (i386_optab): Added xstore/xcrypt insns.
1416 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1418 * h8300.h (32bit ldc/stc): Add relaxing support.
1420 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1422 * h8300.h (BITOP): Pass MEMRELAX flag.
1424 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1426 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1429 For older changes see ChangeLog-9103
1435 version-control: never