include/opcode/ChangeLog

   1 2005-05-10  Nick Clifton  <nickc@redhat.com>
   2
   3         * Update the address and phone number of the FSF organization in
   4         the GPL notices in the following files:
   5         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
   6         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
   7         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
   8         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
   9         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
  10         tic54x.h, tic80.h, v850.h, vax.h
  11
  12 2005-05-09  Jan Beulich  <jbeulich@novell.com>
  13
  14         * i386.h (i386_optab): Add ht and hnt.
  15
  16 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
  17
  18         * i386.h: Insert hyphens into selected VIA PadLock extensions.
  19         Add xcrypt-ctr.  Provide aliases without hyphens.
  20
  21 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
  22
  23         Moved from ../ChangeLog
  24
  25         2005-04-12  Paul Brook  <paul@codesourcery.com>
  26         * m88k.h: Rename psr macros to avoid conflicts.
  27
  28         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
  29         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
  30         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
  31         and ARM_ARCH_V6ZKT2.
  32
  33         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
  34         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
  35         Remove redundant instruction types.
  36         (struct argument): X_op - new field.
  37         (struct cst4_entry): Remove.
  38         (no_op_insn): Declare.
  39
  40         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
  41         * crx.h (enum argtype): Rename types, remove unused types.
  42
  43         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
  44         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
  45         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
  46         (enum operand_type): Rearrange operands, edit comments.
  47         replace us<N> with ui<N> for unsigned immediate.
  48         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
  49         displacements (respectively).
  50         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
  51         (instruction type): Add NO_TYPE_INS.
  52         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
  53         (operand_entry): New field - 'flags'.
  54         (operand flags): New.
  55
  56         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
  57         * crx.h (operand_type): Remove redundant types i3, i4,
  58         i5, i8, i12.
  59         Add new unsigned immediate types us3, us4, us5, us16.
  60
  61 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
  62
  63         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
  64         adjust them accordingly.
  65
  66 2005-04-01  Jan Beulich  <jbeulich@novell.com>
  67
  68         * i386.h (i386_optab): Add rdtscp.
  69
  70 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
  71
  72         * i386.h (i386_optab): Don't allow the `l' suffix for moving
  73         between memory and segment register. Allow movq for moving between
  74         general-purpose register and segment register.
  75
  76 2005-02-09  Jan Beulich  <jbeulich@novell.com>
  77
  78         PR gas/707
  79         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
  80         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
  81         fnstsw.
  82
  83 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
  84
  85         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
  86         * cgen.h (enum cgen_parse_operand_type): Add
  87         CGEN_PARSE_OPERAND_SYMBOLIC.
  88
  89 2005-01-21  Fred Fish  <fnf@specifixinc.com>
  90
  91         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
  92         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
  93         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
  94
  95 2005-01-19  Fred Fish  <fnf@specifixinc.com>
  96
  97         * mips.h (struct mips_opcode): Add new pinfo2 member.
  98         (INSN_ALIAS): New define for opcode table entries that are
  99         specific instances of another entry, such as 'move' for an 'or'
 100         with a zero operand.
 101         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 102         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 103
 104 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 105
 106         * mips.h (CPU_RM9000): Define.
 107         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 108
 109 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 110
 111         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 112         to/from test registers are illegal in 64-bit mode. Add missing
 113         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 114         (previously one had to explicitly encode a rex64 prefix). Re-enable
 115         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 116         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 117
 118 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 119
 120         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 121         available only with SSE2. Change the MMX additions introduced by SSE
 122         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 123         instructions by their now designated identifier (since combining i686
 124         and 3DNow! does not really imply 3DNow!A).
 125
 126 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 127
 128         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 129         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 130
 131 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 132             Vineet Sharma      <vineets@noida.hcltech.com>
 133
 134         * maxq.h: New file: Disassembly information for the maxq port.
 135
 136 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 137
 138         * i386.h (i386_optab): Put back "movzb".
 139
 140 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 141
 142         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 143         comments.  Remove member cris_ver_sim.  Add members
 144         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 145         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 146         (struct cris_support_reg, struct cris_cond15): New types.
 147         (cris_conds15): Declare.
 148         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 149         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 150         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 151         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 152         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 153         SIZE_FIELD_UNSIGNED.
 154
 155 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 156
 157         * i386.h (sldx_Suf): Remove.
 158         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 159         (q_FP): Define, implying no REX64.
 160         (x_FP, sl_FP): Imply FloatMF.
 161         (i386_optab): Split reg and mem forms of moving from segment registers
 162         so that the memory forms can ignore the 16-/32-bit operand size
 163         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 164         all non-floating-point instructions. Unite 32- and 64-bit forms of
 165         movsx, movzx, and movd. Adjust floating point operations for the above
 166         changes to the *FP macros. Add DefaultSize to floating point control
 167         insns operating on larger memory ranges. Remove left over comments
 168         hinting at certain insns being Intel-syntax ones where the ones
 169         actually meant are already gone.
 170
 171 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 172
 173         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 174         instruction type.
 175
 176 2004-09-30  Paul Brook  <paul@codesourcery.com>
 177
 178         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 179         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 180
 181 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 182
 183         * avr.h: Add support for
 184         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 185
 186 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 187
 188         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 189
 190 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 191
 192         * msp430.h (msp430_opc): Add new instructions.
 193         (msp430_rcodes): Declare new instructions.
 194         (msp430_hcodes): Likewise..
 195
 196 2004-08-13  Nick Clifton  <nickc@redhat.com>
 197
 198         PR/301
 199         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 200         processors.
 201
 202 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 203
 204         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 205
 206 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 207
 208         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 209
 210 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 211
 212         * i386.h: Adjust instruction descriptions to better match the
 213         specification.
 214
 215 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 216
 217         * arm.h: Remove all old content.  Replace with architecture defines
 218         from gas/config/tc-arm.c.
 219
 220 2004-07-09  Andreas Schwab  <schwab@suse.de>
 221
 222         * m68k.h: Fix comment.
 223
 224 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 225
 226         * crx.h: New file.
 227
 228 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 229
 230         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 231
 232 2004-05-24  Peter Barada  <peter@the-baradas.com>
 233
 234         * m68k.h: Add 'size' to m68k_opcode.
 235
 236 2004-05-05  Peter Barada  <peter@the-baradas.com>
 237
 238         * m68k.h: Switch from ColdFire chip name to core variant.
 239
 240 2004-04-22  Peter Barada  <peter@the-baradas.com>
 241
 242         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 243         descriptions for new EMAC cases.
 244         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 245         handle Motorola MAC syntax.
 246         Allow disassembly of ColdFire V4e object files.
 247
 248 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 249
 250         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 251
 252 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 253
 254         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 255
 256 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 257
 258         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 259
 260 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 261
 262         * i386.h (i386_optab): Added xstore/xcrypt insns.
 263
 264 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 265
 266         * h8300.h (32bit ldc/stc): Add relaxing support.
 267
 268 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 269
 270         * h8300.h (BITOP): Pass MEMRELAX flag.
 271
 272 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 273
 274         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 275         except for the H8S.
 276
 277 For older changes see ChangeLog-9103
 278 \f
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 280 mode: change-log
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