include/opcode/ChangeLog

   1 2013-12-16  Andrew Bennett  <andrew.bennett@imgtec.com>
   2
   3         * mips.h: Updated description of +o, +u, +v and +w for MIPS and
   4         microMIPS.
   5
   6 2013-12-13  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
   7             Wei-Cheng Wang  <cole945@gmail.com>
   8
   9         * nds32.h: New file for Andes NDS32.
  10
  11 2013-12-07  Mike Frysinger  <vapier@gentoo.org>
  12
  13         * bfin.h: Remove +x file mode.
  14
  15 2013-11-20  Yufeng Zhang  <yufeng.zhang@arm.com>
  16
  17         * aarch64.h (aarch64_pstatefields): Change element type to
  18         aarch64_sys_reg.
  19
  20 2013-11-18  Renlin Li  <Renlin.Li@arm.com>
  21
  22         * arm.h (ARM_AEXT_V7VE): New define.
  23         (ARM_ARCH_V7VE): New define.
  24         (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
  25
  26 2013-11-18  Yufeng Zhang  <yufeng.zhang@arm.com>
  27
  28         Revert
  29
  30         2013-11-15  Yufeng Zhang  <yufeng.zhang@arm.com>
  31
  32         * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
  33         (aarch64_sys_reg_writeonly_p): Ditto.
  34
  35 2013-11-15  Yufeng Zhang  <yufeng.zhang@arm.com>
  36
  37         * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
  38         (aarch64_sys_reg_writeonly_p): Ditto.
  39
  40 2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
  41
  42         * aarch64.h (aarch64_sys_reg): New typedef.
  43         (aarch64_sys_regs): Change to define with the new type.
  44         (aarch64_sys_reg_deprecated_p): Declare.
  45
  46 2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
  47
  48         * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
  49         (enum aarch64_opnd): Add AARCH64_OPND_COND1.
  50
  51 2013-10-14  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
  52
  53         * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
  54         (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
  55         For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
  56         +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
  57         For MIPS, update extension character sequences after +.
  58         (ASE_MSA): New define.
  59         (ASE_MSA64): New define.
  60         For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
  61         +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
  62         For microMIPS, update extension character sequences after +.
  63
  64 2013-08-23  Yuri Chornoivan  <yurchor@ukr.net>
  65
  66         PR binutils/15834
  67         * i960.h: Fix typos.
  68
  69 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
  70
  71         * mips.h: Remove references to "+I" and imm2_expr.
  72
  73 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
  74
  75         * mips.h (M_DEXT, M_DINS): Delete.
  76
  77 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
  78
  79         * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
  80         (mips_optional_operand_p): New function.
  81
  82 2013-08-04  Jürgen Urban  <JuergenUrban@gmx.de>
  83             Richard Sandiford  <rdsandiford@googlemail.com>
  84
  85         * mips.h: Document new VU0 operand characters.
  86         (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
  87         (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
  88         (OP_REG_R5900_ACC): New mips_reg_operand_types.
  89         (INSN2_VU0_CHANNEL_SUFFIX): New macro.
  90         (mips_vu0_channel_mask): Declare.
  91
  92 2013-08-03  Richard Sandiford  <rdsandiford@googlemail.com>
  93
  94         * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
  95         (mips_int_operand_min, mips_int_operand_max): New functions.
  96         (mips_decode_pcrel_operand): Use mips_decode_int_operand.
  97
  98 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
  99
 100         * mips.h (mips_decode_reg_operand): New function.
 101         (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
 102         (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
 103         (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
 104         New macros.
 105         (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
 106         (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
 107         (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
 108         (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
 109         (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
 110         (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
 111         (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
 112         (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
 113         (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
 114         (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete.  Renumber other
 115         macros to cover the gaps.
 116         (INSN2_MOD_SP): Replace with...
 117         (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
 118         (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
 119         (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
 120         (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
 121         (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
 122         Delete.
 123
 124 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 125
 126         * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
 127         (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
 128         (MIPS16_INSN_COND_BRANCH): Delete.
 129
 130 2013-07-24  Anna Tikhonova  <anna.tikhonova@intel.com>
 131             Kirill Yukhin  <kirill.yukhin@intel.com>
 132             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 133
 134         * i386.h (BND_PREFIX_OPCODE): New.
 135
 136 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 137
 138         * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
 139         OP_SAVE_RESTORE_LIST.
 140         (decode_mips16_operand): Declare.
 141
 142 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 143
 144         * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
 145         (mips_operand, mips_int_operand, mips_mapped_int_operand)
 146         (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
 147         (mips_pcrel_operand): New structures.
 148         (mips_insert_operand, mips_extract_operand, mips_signed_operand)
 149         (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
 150         (decode_mips_operand, decode_micromips_operand): Declare.
 151
 152 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 153
 154         * mips.h: Document MIPS16 "I" opcode.
 155
 156 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 157
 158         * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
 159         (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
 160         (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
 161         (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
 162         (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
 163         (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
 164         (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
 165         (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
 166         (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
 167         (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
 168         (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
 169         (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
 170         (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
 171         Rename to...
 172         (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
 173         (M_USD_AB): ...these.
 174
 175 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 176
 177         * mips.h: Remove documentation of "[" and "]".  Update documentation
 178         of "k" and the MDMX formats.
 179
 180 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 181
 182         * mips.h: Update documentation of "+s" and "+S".
 183
 184 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 185
 186         * mips.h: Document "+i".
 187
 188 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 189
 190         * mips.h: Remove "mi" documentation.  Update "mh" documentation.
 191         (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
 192         Delete.
 193         (INSN2_WRITE_GPR_MHI): Rename to...
 194         (INSN2_WRITE_GPR_MH): ...this.
 195
 196 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 197
 198         * mips.h: Remove documentation of "+D" and "+T".
 199
 200 2013-06-26  Richard Sandiford  <rdsandiford@googlemail.com>
 201
 202         * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
 203         Use "source" rather than "destination" for microMIPS "G".
 204
 205 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
 206
 207         * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
 208         values.
 209
 210 2013-06-23  Richard Sandiford  <rdsandiford@googlemail.com>
 211
 212         * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
 213
 214 2013-06-17  Catherine Moore  <clm@codesourcery.com>
 215             Maciej W. Rozycki  <macro@codesourcery.com>
 216             Chao-Ying Fu  <fu@mips.com>
 217
 218         * mips.h (OP_SH_EVAOFFSET): Define.
 219         (OP_MASK_EVAOFFSET): Define.
 220         (INSN_ASE_MASK): Delete.
 221         (ASE_EVA): Define.
 222         (M_CACHEE_AB, M_CACHEE_OB): New.
 223         (M_LBE_OB, M_LBE_AB): New.
 224         (M_LBUE_OB, M_LBUE_AB): New.
 225         (M_LHE_OB, M_LHE_AB): New.
 226         (M_LHUE_OB, M_LHUE_AB): New.
 227         (M_LLE_AB, M_LLE_OB): New.
 228         (M_LWE_OB, M_LWE_AB): New.
 229         (M_LWLE_AB, M_LWLE_OB): New.
 230         (M_LWRE_AB, M_LWRE_OB): New.
 231         (M_PREFE_AB, M_PREFE_OB): New.
 232         (M_SCE_AB, M_SCE_OB): New.
 233         (M_SBE_OB, M_SBE_AB): New.
 234         (M_SHE_OB, M_SHE_AB): New.
 235         (M_SWE_OB, M_SWE_AB): New.
 236         (M_SWLE_AB, M_SWLE_OB): New.
 237         (M_SWRE_AB, M_SWRE_OB): New.
 238         (MICROMIPSOP_SH_EVAOFFSET): Define.
 239         (MICROMIPSOP_MASK_EVAOFFSET): Define.
 240
 241 2013-06-12  Sandra Loosemore  <sandra@codesourcery.com>
 242
 243         * nios2.h (OP_MATCH_ERET): Correct eret encoding.
 244
 245 2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
 246
 247         * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
 248
 249 2013-05-09  Andrew Pinski  <apinski@cavium.com>
 250
 251         * mips.h (OP_MASK_CODE10): Correct definition.
 252         (OP_SH_CODE10): Likewise.
 253         Add a comment that "+J" is used now for OP_*CODE10.
 254         (INSN_ASE_MASK): Update.
 255         (INSN_VIRT): New macro.
 256         (INSN_VIRT64): New macro
 257
 258 2013-05-02  Nick Clifton  <nickc@redhat.com>
 259
 260         * msp430.h: Add patterns for MSP430X instructions.
 261
 262 2013-04-06  David S. Miller  <davem@davemloft.net>
 263
 264         * sparc.h (F_PREFERRED): Define.
 265         (F_PREF_ALIAS): Define.
 266
 267 2013-04-03  Nick Clifton  <nickc@redhat.com>
 268
 269         * v850.h (V850_INVERSE_PCREL): Define.
 270
 271 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 272
 273         PR binutils/15068
 274         * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
 275
 276 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 277
 278         PR binutils/15068
 279         * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
 280         Add 16-bit opcodes.
 281         * tic6xc-opcode-table.h: Add 16-bit insns.
 282         * tic6x.h: Add support for 16-bit insns.
 283
 284 2013-03-21  Michael Schewe  <michael.schewe@gmx.net>
 285
 286         * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
 287         and mov.b/w/l Rs,@(d:32,ERd).
 288
 289 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 290
 291         PR gas/15082
 292         * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
 293         from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
 294         tic6x_operand_xregpair operand coding type.
 295         Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
 296         opcode field, usu ORXREGD1324 for the src2 operand and remove the
 297         TIC6X_FLAG_NO_CROSS.
 298
 299 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 300
 301         PR gas/15095
 302         * tic6x.h (enum tic6x_coding_method): Add
 303         tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
 304         separately the msb and lsb of a register pair.  This is needed to
 305         encode the opcodes in the same way as TI assembler does.
 306         * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
 307         and rsqrdp opcodes to use the new field coding types.
 308
 309 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 310
 311         * arm.h (CRC_EXT_ARMV8): New constant.
 312         (ARCH_CRC_ARMV8): New macro.
 313
 314 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
 315
 316         * aarch64.h (AARCH64_FEATURE_CRC): New macro.
 317
 318 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
 319             Andrew Jenner <andrew@codesourcery.com>
 320
 321         Based on patches from Altera Corporation.
 322
 323         * nios2.h: New file.
 324
 325 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
 326
 327         * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
 328
 329 2013-01-28  Alexis Deruelle  <alexis.deruelle@gmail.com>
 330
 331         PR gas/15069
 332         * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
 333
 334 2013-01-24  Nick Clifton  <nickc@redhat.com>
 335
 336         * v850.h: Add e3v5 support.
 337
 338 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
 339
 340         * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
 341
 342 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
 343
 344         * ppc.h (PPC_OPCODE_POWER8): New define.
 345         (PPC_OPCODE_HTM): Likewise.
 346
 347 2013-01-10  Will Newton <will.newton@imgtec.com>
 348
 349         * metag.h: New file.
 350
 351 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 352
 353         * cr16.h (make_instruction): Rename to cr16_make_instruction.
 354         (match_opcode): Rename to cr16_match_opcode.
 355
 356 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
 357
 358         * mips.h: Add support for r5900 instructions including lq and sq.
 359
 360 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 361
 362         * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
 363         (make_instruction,match_opcode): Added function prototypes.
 364         (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
 365
 366 2012-11-23  Alan Modra  <amodra@gmail.com>
 367
 368         * ppc.h (ppc_parse_cpu): Update prototype.
 369
 370 2012-10-14  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 371
 372         * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
 373         opcodes.  Likewise, use "cM" instead of "cm" in fstqs opcodes.
 374
 375 2012-10-04  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 376
 377         * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
 378
 379 2012-09-04  Sergey A. Guriev <sergey.a.guriev@intel.com>
 380
 381         * ia64.h (ia64_opnd): Add new operand types.
 382
 383 2012-08-21  David S. Miller  <davem@davemloft.net>
 384
 385         * sparc.h (F3F4): New macro.
 386
 387 2012-08-13  Ian Bolton  <ian.bolton@arm.com>
 388             Laurent Desnogues  <laurent.desnogues@arm.com>
 389             Jim MacArthur  <jim.macarthur@arm.com>
 390             Marcus Shawcroft  <marcus.shawcroft@arm.com>
 391             Nigel Stephens  <nigel.stephens@arm.com>
 392             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 393             Richard Earnshaw  <rearnsha@arm.com>
 394             Sofiane Naci  <sofiane.naci@arm.com>
 395             Tejas Belagod  <tejas.belagod@arm.com>
 396             Yufeng Zhang  <yufeng.zhang@arm.com>
 397
 398         * aarch64.h: New file.
 399
 400 2012-08-13  Richard Sandiford  <rdsandiford@googlemail.com>
 401             Maciej W. Rozycki  <macro@codesourcery.com>
 402
 403         * mips.h (mips_opcode): Add the exclusions field.
 404         (OPCODE_IS_MEMBER): Remove macro.
 405         (cpu_is_member): New inline function.
 406         (opcode_is_member): Likewise.
 407
 408 2012-07-31  Chao-Ying Fu  <fu@mips.com>
 409             Catherine Moore  <clm@codesourcery.com>
 410             Maciej W. Rozycki  <macro@codesourcery.com>
 411
 412         * mips.h: Document microMIPS DSP ASE usage.
 413         (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
 414         microMIPS DSP ASE support.
 415         (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
 416         (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
 417         (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
 418         (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
 419         (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
 420         (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
 421         (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
 422
 423 2012-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 424
 425         * mips.h: Fix a typo in description.
 426
 427 2012-06-07  Georg-Johann Lay  <avr@gjlay.de>
 428
 429         * avr.h: (AVR_ISA_XCH): New define.
 430         (AVR_ISA_XMEGA): Use it.
 431         (XCH, LAS, LAT, LAC): New XMEGA opcodes.
 432
 433 2012-05-15  James Murray <jsm@jsm-net.demon.co.uk>
 434
 435         * m68hc11.h: Add XGate definitions.
 436         (struct m68hc11_opcode): Add xg_mask field.
 437
 438 2012-05-14  Catherine Moore  <clm@codesourcery.com>
 439             Maciej W. Rozycki  <macro@codesourcery.com>
 440             Rhonda Wittels  <rhonda@codesourcery.com>
 441
 442         * ppc.h (PPC_OPCODE_VLE): New definition.
 443         (PPC_OP_SA): New macro.
 444         (PPC_OP_SE_VLE): New macro.
 445         (PPC_OP): Use a variable shift amount.
 446         (powerpc_operand): Update comments.
 447         (PPC_OPSHIFT_INV): New macro.
 448         (PPC_OPERAND_CR): Replace with...
 449         (PPC_OPERAND_CR_BIT): ...this and
 450         (PPC_OPERAND_CR_REG): ...this.
 451
 452
 453 2012-05-03  Sean Keys  <skeys@ipdatasys.com>
 454
 455         * xgate.h: Header file for XGATE assembler.
 456
 457 2012-04-27  David S. Miller  <davem@davemloft.net>
 458
 459         * sparc.h: Document new arg code' )' for crypto RS3
 460         immediates.
 461
 462         * sparc.h (struct sparc_opcode): New field 'hwcaps'.
 463         F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
 464         F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
 465         F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
 466         (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
 467         HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
 468         HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
 469         HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
 470         HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
 471         HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
 472         HWCAP_CBCOND, HWCAP_CRC32): New defines.
 473
 474 2012-03-10  Edmar Wienskoski  <edmar@freescale.com>
 475
 476         * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
 477
 478 2012-02-27  Alan Modra  <amodra@gmail.com>
 479
 480         * crx.h (cst4_map): Update declaration.
 481
 482 2012-02-25  Walter Lee  <walt@tilera.com>
 483
 484         * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
 485         TILEGX_OPC_LD_TLS.
 486         * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
 487         TILEPRO_OPC_LW_TLS_SN.
 488
 489 2012-02-08  H.J. Lu  <hongjiu.lu@intel.com>
 490
 491         * i386.h (XACQUIRE_PREFIX_OPCODE): New.
 492         (XRELEASE_PREFIX_OPCODE): Likewise.
 493
 494 2011-12-08  Andrew Pinski  <apinski@cavium.com>
 495             Adam Nemet  <anemet@caviumnetworks.com>
 496
 497         * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
 498         (INSN_OCTEON2): New macro.
 499         (CPU_OCTEON2): New macro.
 500         (OPCODE_IS_MEMBER): Add Octeon2.
 501
 502 2011-11-29  Andrew Pinski  <apinski@cavium.com>
 503
 504         * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
 505         (INSN_OCTEONP): New macro.
 506         (CPU_OCTEONP): New macro.
 507         (OPCODE_IS_MEMBER): Add Octeon+.
 508         (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
 509
 510 2011-11-01  DJ Delorie  <dj@redhat.com>
 511
 512         * rl78.h: New file.
 513
 514 2011-10-24  Maciej W. Rozycki  <macro@codesourcery.com>
 515
 516         * mips.h: Fix a typo in description.
 517
 518 2011-09-21  David S. Miller  <davem@davemloft.net>
 519
 520         * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
 521         (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
 522         F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
 523         F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
 524
 525 2011-08-09  Chao-ying Fu  <fu@mips.com>
 526             Maciej W. Rozycki  <macro@codesourcery.com>
 527
 528         * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
 529         (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
 530         (INSN_ASE_MASK): Add the MCU bit.
 531         (INSN_MCU): New macro.
 532         (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
 533         (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
 534
 535 2011-08-09  Maciej W. Rozycki  <macro@codesourcery.com>
 536
 537         * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
 538         (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
 539         (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
 540         (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
 541         (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
 542         (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
 543         (INSN2_READ_GPR_MMN): Likewise.
 544         (INSN2_READ_FPR_D): Change the bit used.
 545         (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
 546         (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
 547         (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
 548         (INSN2_COND_BRANCH): Likewise.
 549         (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
 550         (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
 551         (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
 552         (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
 553         (INSN2_MOD_GPR_MN): Likewise.
 554
 555 2011-08-05  David S. Miller  <davem@davemloft.net>
 556
 557         * sparc.h: Document new format codes '4', '5', and '('.
 558         (OPF_LOW4, RS3): New macros.
 559
 560 2011-08-03  Maciej W. Rozycki  <macro@codesourcery.com>
 561
 562         * mips.h: Document the use of FP_D in MIPS16 mode.  Adjust the
 563         order of flags documented.
 564
 565 2011-07-29  Maciej W. Rozycki  <macro@codesourcery.com>
 566
 567         * mips.h: Clarify the description of microMIPS instruction
 568         manipulation macros.
 569         (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
 570
 571 2011-07-24  Chao-ying Fu  <fu@mips.com>
 572             Maciej W. Rozycki  <macro@codesourcery.com>
 573
 574         * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
 575         (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
 576         (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
 577         (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
 578         (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
 579         (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
 580         (OP_MASK_RS3, OP_SH_RS3): Likewise.
 581         (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
 582         (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
 583         (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
 584         (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
 585         (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
 586         (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
 587         (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
 588         (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
 589         (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
 590         (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
 591         (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
 592         (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
 593         (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
 594         (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
 595         (INSN_WRITE_GPR_S): New macro.
 596         (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
 597         (INSN2_READ_FPR_D): Likewise.
 598         (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
 599         (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
 600         (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
 601         (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
 602         (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
 603         (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
 604         (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
 605         (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
 606         (CPU_MICROMIPS): New macro.
 607         (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
 608         (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
 609         (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
 610         (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
 611         (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
 612         (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
 613         (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
 614         (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
 615         (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
 616         (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
 617         (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
 618         (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
 619         (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
 620         (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
 621         (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
 622         (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
 623         (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
 624         (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
 625         (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
 626         (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
 627         (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
 628         (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
 629         (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
 630         (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
 631         (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
 632         (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
 633         (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
 634         (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
 635         (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
 636         (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
 637         (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
 638         (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
 639         (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
 640         (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
 641         (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
 642         (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
 643         (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
 644         (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
 645         (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
 646         (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
 647         (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
 648         (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
 649         (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
 650         (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
 651         (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
 652         (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
 653         (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
 654         (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
 655         (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
 656         (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
 657         (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
 658         (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
 659         (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
 660         (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
 661         (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
 662         (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
 663         (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
 664         (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
 665         (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
 666         (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
 667         (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
 668         (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
 669         (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
 670         (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
 671         (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
 672         (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
 673         (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
 674         (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
 675         (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
 676         (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
 677         (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
 678         (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
 679         (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
 680         (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
 681         (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
 682         (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
 683         (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
 684         (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
 685         (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
 686         (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
 687         (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
 688         (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
 689         (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
 690         (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
 691         (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
 692         (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
 693         (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
 694         (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
 695         (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
 696         (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
 697         (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
 698         (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
 699         (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
 700         (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
 701         (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
 702         (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
 703         (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
 704         (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
 705         (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
 706         (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
 707         (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
 708         (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
 709         (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
 710         (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
 711         (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
 712         (micromips_opcodes): New declaration.
 713         (bfd_micromips_num_opcodes): Likewise.
 714
 715 2011-07-24  Maciej W. Rozycki  <macro@codesourcery.com>
 716
 717         * mips.h (INSN_TRAP): Rename to...
 718         (INSN_NO_DELAY_SLOT): ... this.
 719         (INSN_SYNC): Remove macro.
 720
 721 2011-07-01  Eric B. Weddington  <eric.weddington@atmel.com>
 722
 723         * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
 724         a duplicate of AVR_ISA_SPM.
 725
 726 2011-07-01  Nick Clifton  <nickc@redhat.com>
 727
 728         * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
 729
 730 2011-06-18  Robin Getz  <robin.getz@analog.com>
 731
 732         * bfin.h (is_macmod_signed): New func
 733
 734 2011-06-18  Mike Frysinger  <vapier@gentoo.org>
 735
 736         * bfin.h (is_macmod_pmove): Add missing space before func args.
 737         (is_macmod_hmove): Likewise.
 738
 739 2011-06-13  Walter Lee  <walt@tilera.com>
 740
 741         * tilegx.h: New file.
 742         * tilepro.h: New file.
 743
 744 2011-05-31  Paul Brook  <paul@codesourcery.com>
 745
 746         * arm.h (ARM_ARCH_V7R_IDIV): Define.
 747
 748 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 749
 750         * s390.h: Replace S390_OPERAND_REG_EVEN with
 751         S390_OPERAND_REG_PAIR.
 752
 753 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 754
 755         * s390.h: Add S390_OPCODE_REG_EVEN flag.
 756
 757 2011-04-18  Julian Brown  <julian@codesourcery.com>
 758
 759         * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
 760
 761 2011-04-11  Dan McDonald  <dan@wellkeeper.com>
 762
 763         PR gas/12296
 764         * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
 765
 766 2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>
 767
 768         * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
 769         New instruction set flags.
 770         (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
 771
 772 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 773
 774         * mips.h (M_PREF_AB): New enum value.
 775
 776 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 777
 778         * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
 779         M_IU): Define.
 780         (is_macmod_pmove, is_macmod_hmove): New functions.
 781
 782 2011-02-11  Mike Frysinger  <vapier@gentoo.org>
 783
 784         * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
 785
 786 2011-02-04  Bernd Schmidt  <bernds@codesourcery.com>
 787
 788         * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
 789         * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
 790
 791 2010-12-31  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 792
 793         PR gas/11395
 794         * hppa.h (pa_opcodes): Revert last change.  Exchange 32 and 64-bit
 795         "bb" entries.
 796
 797 2010-12-26  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 798
 799         PR gas/11395
 800         * hppa.h: Clear "d" bit in "add" and "sub" patterns.
 801
 802 2010-12-18  Richard Sandiford  <rdsandiford@googlemail.com>
 803
 804         * mips.h: Update commentary after last commit.
 805
 806 2010-12-18  Mingjie Xing  <mingjie.xing@gmail.com>
 807
 808         * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
 809         (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
 810         (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
 811
 812 2010-11-25  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 813
 814         * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
 815
 816 2010-11-23  Richard Sandiford  <rdsandiford@googlemail.com>
 817
 818         * mips.h: Fix previous commit.
 819
 820 2010-11-23  Maciej W. Rozycki  <macro@linux-mips.org>
 821
 822         * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
 823         (INSN_LOONGSON_3A): Clear bit 31.
 824
 825 2010-11-15  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 826
 827         PR gas/12198
 828         * arm.h (ARM_AEXT_V6M_ONLY): New define.
 829         (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
 830         (ARM_ARCH_V6M_ONLY): New define.
 831
 832 2010-11-11  Mingming Sun  <mingm.sun@gmail.com>
 833
 834         * mips.h (INSN_LOONGSON_3A): Defined.
 835         (CPU_LOONGSON_3A): Defined.
 836         (OPCODE_IS_MEMBER): Add LOONGSON_3A.
 837
 838 2010-10-09  Matt Rice  <ratmice@gmail.com>
 839
 840         * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
 841         (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
 842
 843 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 844
 845         * arm.h (ARM_EXT_VIRT): New define.
 846         (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
 847         (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
 848         Extensions.
 849
 850 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 851
 852         * arm.h (ARM_AEXT_ADIV): New define.
 853         (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
 854
 855 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 856
 857         * arm.h (ARM_EXT_OS): New define.
 858         (ARM_AEXT_V6SM): Likewise.
 859         (ARM_ARCH_V6SM): Likewise.
 860
 861 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 862
 863         * arm.h (ARM_EXT_MP): Add.
 864         (ARM_ARCH_V7A_MP): Likewise.
 865
 866 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 867
 868         * bfin.h: Declare pseudoChr structs/defines.
 869
 870 2010-09-21  Mike Frysinger  <vapier@gentoo.org>
 871
 872         * bfin.h: Strip trailing whitespace.
 873
 874 2010-07-29  DJ Delorie  <dj@redhat.com>
 875
 876         * rx.h (RX_Operand_Type): Add TwoReg.
 877         (RX_Opcode_ID): Remove ediv and ediv2.
 878
 879 2010-07-27  DJ Delorie  <dj@redhat.com>
 880
 881         * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
 882
 883 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
 884             Ina Pandit  <ina.pandit@kpitcummins.com>
 885
 886         * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
 887         PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
 888         PROCESSOR_V850E2_ALL.
 889         Remove PROCESSOR_V850EA support.
 890         (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
 891         V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
 892         V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
 893         V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
 894         V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
 895         V850_OPERAND_PERCENT.
 896         Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
 897         V850_NOT_R0.
 898         Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
 899         and V850E_PUSH_POP
 900
 901 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 902
 903         * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
 904         (MIPS16_INSN_BRANCH): Rename to...
 905         (MIPS16_INSN_COND_BRANCH): ... this.
 906
 907 2010-07-03  Alan Modra  <amodra@gmail.com>
 908
 909         * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
 910         Renumber other PPC_OPCODE defines.
 911
 912 2010-07-03  Alan Modra  <amodra@gmail.com>
 913
 914         * ppc.h (PPC_OPCODE_COMMON): Expand comment.
 915
 916 2010-06-29  Alan Modra  <amodra@gmail.com>
 917
 918         * maxq.h: Delete file.
 919
 920 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 921
 922         * ppc.h (PPC_OPCODE_E500): Define.
 923
 924 2010-05-26  Catherine Moore  <clm@codesourcery.com>
 925
 926         * opcode/mips.h (INSN_MIPS16): Remove.
 927
 928 2010-04-21  Joseph Myers  <joseph@codesourcery.com>
 929
 930         * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
 931
 932 2010-04-15  Nick Clifton  <nickc@redhat.com>
 933
 934         * alpha.h: Update copyright notice to use GPLv3.
 935         * arc.h: Likewise.
 936         * arm.h: Likewise.
 937         * avr.h: Likewise.
 938         * bfin.h: Likewise.
 939         * cgen.h: Likewise.
 940         * convex.h: Likewise.
 941         * cr16.h: Likewise.
 942         * cris.h: Likewise.
 943         * crx.h: Likewise.
 944         * d10v.h: Likewise.
 945         * d30v.h: Likewise.
 946         * dlx.h: Likewise.
 947         * h8300.h: Likewise.
 948         * hppa.h: Likewise.
 949         * i370.h: Likewise.
 950         * i386.h: Likewise.
 951         * i860.h: Likewise.
 952         * i960.h: Likewise.
 953         * ia64.h: Likewise.
 954         * m68hc11.h: Likewise.
 955         * m68k.h: Likewise.
 956         * m88k.h: Likewise.
 957         * maxq.h: Likewise.
 958         * mips.h: Likewise.
 959         * mmix.h: Likewise.
 960         * mn10200.h: Likewise.
 961         * mn10300.h: Likewise.
 962         * msp430.h: Likewise.
 963         * np1.h: Likewise.
 964         * ns32k.h: Likewise.
 965         * or32.h: Likewise.
 966         * pdp11.h: Likewise.
 967         * pj.h: Likewise.
 968         * pn.h: Likewise.
 969         * ppc.h: Likewise.
 970         * pyr.h: Likewise.
 971         * rx.h: Likewise.
 972         * s390.h: Likewise.
 973         * score-datadep.h: Likewise.
 974         * score-inst.h: Likewise.
 975         * sparc.h: Likewise.
 976         * spu-insns.h: Likewise.
 977         * spu.h: Likewise.
 978         * tic30.h: Likewise.
 979         * tic4x.h: Likewise.
 980         * tic54x.h: Likewise.
 981         * tic80.h: Likewise.
 982         * v850.h: Likewise.
 983         * vax.h: Likewise.
 984
 985 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
 986
 987         * tic6x-control-registers.h, tic6x-insn-formats.h,
 988         tic6x-opcode-table.h, tic6x.h: New.
 989
 990 2010-02-25  Wu Zhangjin  <wuzhangjin@gmail.com>
 991
 992         * mips.h: (LOONGSON2F_NOP_INSN): New macro.
 993
 994 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
 995
 996         * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
 997
 998 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 999
1000         * ia64.h (ia64_find_opcode): Remove argument name.
1001         (ia64_find_next_opcode): Likewise.
1002         (ia64_dis_opcode): Likewise.
1003         (ia64_free_opcode): Likewise.
1004         (ia64_find_dependency): Likewise.
1005
1006 2009-11-22  Doug Evans  <dje@sebabeach.org>
1007
1008         * cgen.h: Include bfd_stdint.h.
1009         (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1010
1011 2009-11-18  Paul Brook  <paul@codesourcery.com>
1012
1013         * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1014
1015 2009-11-17  Paul Brook  <paul@codesourcery.com>
1016         Daniel Jacobowitz  <dan@codesourcery.com>
1017
1018         * arm.h (ARM_EXT_V6_DSP): Define.
1019         (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1020         (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1021
1022 2009-11-04  DJ Delorie  <dj@redhat.com>
1023
1024         * rx.h (rx_decode_opcode) (mvtipl): Add.
1025         (mvtcp, mvfcp, opecp): Remove.
1026
1027 2009-11-02  Paul Brook  <paul@codesourcery.com>
1028
1029         * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1030         FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1031         (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1032         FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1033         FPU_ARCH_NEON_VFP_V4): Define.
1034
1035 2009-10-23  Doug Evans  <dje@sebabeach.org>
1036
1037         * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1038         * cgen.h: Update.  Improve multi-inclusion macro name.
1039
1040 2009-10-02  Peter Bergner  <bergner@vnet.ibm.com>
1041
1042         * ppc.h (PPC_OPCODE_476): Define.
1043
1044 2009-10-01  Peter Bergner  <bergner@vnet.ibm.com>
1045
1046         * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1047
1048 2009-09-29  DJ Delorie  <dj@redhat.com>
1049
1050         * rx.h: New file.
1051
1052 2009-09-22  Peter Bergner  <bergner@vnet.ibm.com>
1053
1054         * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1055
1056 2009-09-21  Ben Elliston  <bje@au.ibm.com>
1057
1058         * ppc.h (PPC_OPCODE_PPCA2): New.
1059
1060 2009-09-05  Martin Thuresson  <martin@mtme.org>
1061
1062         * ia64.h (struct ia64_operand): Renamed member class to op_class.
1063
1064 2009-08-29  Martin Thuresson  <martin@mtme.org>
1065
1066         * tic30.h (template): Rename type template to
1067         insn_template. Updated code to use new name.
1068         * tic54x.h (template): Rename type template to
1069         insn_template.
1070
1071 2009-08-20  Nick Hudson  <nick.hudson@gmx.co.uk>
1072
1073         * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1074
1075 2009-06-11  Anthony Green  <green@moxielogic.com>
1076
1077         * moxie.h (MOXIE_F3_PCREL): Define.
1078         (moxie_form3_opc_info): Grow.
1079
1080 2009-06-06  Anthony Green  <green@moxielogic.com>
1081
1082         * moxie.h (MOXIE_F1_M): Define.
1083
1084 2009-04-15  Anthony Green  <green@moxielogic.com>
1085
1086         * moxie.h: Created.
1087
1088 2009-04-06  DJ Delorie  <dj@redhat.com>
1089
1090         * h8300.h: Add relaxation attributes to MOVA opcodes.
1091
1092 2009-03-10  Alan Modra  <amodra@bigpond.net.au>
1093
1094         * ppc.h (ppc_parse_cpu): Declare.
1095
1096 2009-03-02  Qinwei  <qinwei@sunnorth.com.cn>
1097
1098         * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1099         and _IMM11 for mbitclr and mbitset.
1100         * score-datadep.h: Update dependency information.
1101
1102 2009-02-26  Peter Bergner  <bergner@vnet.ibm.com>
1103
1104         * ppc.h (PPC_OPCODE_POWER7): New.
1105
1106 2009-02-06  Doug Evans  <dje@google.com>
1107
1108         * i386.h: Add comment regarding sse* insns and prefixes.
1109
1110 2009-02-03  Sandip Matte  <sandip@rmicorp.com>
1111
1112         * mips.h (INSN_XLR): Define.
1113         (INSN_CHIP_MASK): Update.
1114         (CPU_XLR): Define.
1115         (OPCODE_IS_MEMBER): Update.
1116         (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1117
1118 2009-01-28  Doug Evans  <dje@google.com>
1119
1120         * opcode/i386.h: Add multiple inclusion protection.
1121         (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1122         (EDI_REG_NUM): New macros.
1123         (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1124         (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1125         (REX_PREFIX_P): New macro.
1126
1127 2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
1128
1129         * ppc.h (struct powerpc_opcode): New field "deprecated".
1130         (PPC_OPCODE_NOPOWER4): Delete.
1131
1132 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
1133
1134         * mips.h: Define CPU_R14000, CPU_R16000.
1135         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1136
1137 2008-11-18  Catherine Moore  <clm@codesourcery.com>
1138
1139         * arm.h (FPU_NEON_FP16): New.
1140         (FPU_ARCH_NEON_FP16): New.
1141
1142 2008-11-06  Chao-ying Fu  <fu@mips.com>
1143
1144         * mips.h: Doucument '1' for 5-bit sync type.
1145
1146 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
1147
1148         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
1149         IA64_RS_CR.
1150
1151 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
1152
1153         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1154
1155 2008-07-30  Michael J. Eager  <eager@eagercon.com>
1156
1157         * ppc.h (PPC_OPCODE_405): Define.
1158         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1159
1160 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
1161
1162         * ppc.h (ppc_cpu_t): New typedef.
1163         (struct powerpc_opcode <flags>): Use it.
1164         (struct powerpc_operand <insert, extract>): Likewise.
1165         (struct powerpc_macro <flags>): Likewise.
1166
1167 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
1168
1169         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1170         Update comment before MIPS16 field descriptors to mention MIPS16.
1171         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1172         BBIT.
1173         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1174         New bit masks and shift counts for cins and exts.
1175
1176         * mips.h: Document new field descriptors +Q.
1177         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1178
1179 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
1180
1181         * mips.h (INSN_MACRO): Move it up to the pinfo macros.
1182         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1183
1184 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
1185
1186         * ppc.h: (PPC_OPCODE_E500MC): New.
1187
1188 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
1189
1190         * i386.h (MAX_OPERANDS): Set to 5.
1191         (MAX_MNEM_SIZE): Changed to 20.
1192
1193 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
1194
1195         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1196
1197 2008-03-09  Paul Brook  <paul@codesourcery.com>
1198
1199         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1200
1201 2008-03-04  Paul Brook  <paul@codesourcery.com>
1202
1203         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1204         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1205         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1206
1207 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
1208             Nick Clifton  <nickc@redhat.com>
1209
1210         PR 3134
1211         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1212         with a 32-bit displacement but without the top bit of the 4th byte
1213         set.
1214
1215 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1216
1217         * cr16.h (cr16_num_optab): Declared.
1218
1219 2008-02-14  Hakan Ardo  <hakan@debian.org>
1220
1221         PR gas/2626
1222         * avr.h (AVR_ISA_2xxe): Define.
1223
1224 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
1225
1226         * mips.h: Update copyright.
1227         (INSN_CHIP_MASK): New macro.
1228         (INSN_OCTEON): New macro.
1229         (CPU_OCTEON): New macro.
1230         (OPCODE_IS_MEMBER): Handle Octeon instructions.
1231
1232 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
1233
1234         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1235
1236 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
1237
1238         * avr.h (AVR_ISA_USB162): Add new opcode set.
1239         (AVR_ISA_AVR3): Likewise.
1240
1241 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
1242
1243         * mips.h (INSN_LOONGSON_2E): New.
1244         (INSN_LOONGSON_2F): New.
1245         (CPU_LOONGSON_2E): New.
1246         (CPU_LOONGSON_2F): New.
1247         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1248
1249 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
1250
1251         * mips.h (INSN_ISA*): Redefine certain values as an
1252         enumeration.  Update comments.
1253         (mips_isa_table): New.
1254         (ISA_MIPS*): Redefine to match enumeration.
1255         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1256         values.
1257
1258 2007-08-08  Ben Elliston  <bje@au.ibm.com>
1259
1260         * ppc.h (PPC_OPCODE_PPCPS): New.
1261
1262 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
1263
1264         * m68k.h: Document j K & E.
1265
1266 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
1267
1268         * cr16.h: New file for CR16 target.
1269
1270 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
1271
1272         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1273
1274 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
1275
1276         * m68k.h (mcfisa_c): New.
1277         (mcfusp, mcf_mask): Adjust.
1278
1279 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
1280
1281         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1282         (num_powerpc_operands): Declare.
1283         (PPC_OPERAND_SIGNED et al): Redefine as hex.
1284         (PPC_OPERAND_PLUS1): Define.
1285
1286 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
1287
1288         * i386.h (REX_MODE64): Renamed to ...
1289         (REX_W): This.
1290         (REX_EXTX): Renamed to ...
1291         (REX_R): This.
1292         (REX_EXTY): Renamed to ...
1293         (REX_X): This.
1294         (REX_EXTZ): Renamed to ...
1295         (REX_B): This.
1296
1297 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
1298
1299         * i386.h: Add entries from config/tc-i386.h and move tables
1300         to opcodes/i386-opc.h.
1301
1302 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
1303
1304         * i386.h (FloatDR): Removed.
1305         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1306
1307 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
1308
1309         * spu-insns.h: Add soma double-float insns.
1310
1311 2007-02-20  Thiemo Seufer  <ths@mips.com>
1312             Chao-Ying Fu  <fu@mips.com>
1313
1314         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1315         (INSN_DSPR2): Add flag for DSP R2 instructions.
1316         (M_BALIGN): New macro.
1317
1318 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
1319
1320         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1321         and Seg3ShortFrom with Shortform.
1322
1323 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
1324
1325         PR gas/4027
1326         * i386.h (i386_optab): Put the real "test" before the pseudo
1327         one.
1328
1329 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
1330
1331         * m68k.h (m68010up): OR fido_a.
1332
1333 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
1334
1335         * m68k.h (fido_a): New.
1336
1337 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
1338
1339         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1340         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1341         values.
1342
1343 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
1344
1345         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1346
1347 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
1348
1349         * score-inst.h (enum score_insn_type): Add Insn_internal.
1350
1351 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
1352             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
1353             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
1354             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
1355             Alan Modra  <amodra@bigpond.net.au>
1356
1357         * spu-insns.h: New file.
1358         * spu.h: New file.
1359
1360 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
1361
1362         * ppc.h (PPC_OPCODE_CELL): Define.
1363
1364 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
1365
1366         * i386.h :  Modify opcode to support for the change in POPCNT opcode
1367         in amdfam10 architecture.
1368
1369 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
1370
1371         * i386.h: Replace CpuMNI with CpuSSSE3.
1372
1373 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
1374             Joseph Myers  <joseph@codesourcery.com>
1375             Ian Lance Taylor  <ian@wasabisystems.com>
1376             Ben Elliston  <bje@wasabisystems.com>
1377
1378         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1379
1380 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
1381
1382         * score-datadep.h: New file.
1383         * score-inst.h: New file.
1384
1385 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
1386
1387         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1388         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1389         movdq2q and movq2dq.
1390
1391 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
1392            Michael Meissner             <michael.meissner@amd.com>
1393
1394         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1395
1396 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
1397
1398         * i386.h (i386_optab): Add "nop" with memory reference.
1399
1400 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
1401
1402         * i386.h (i386_optab): Update comment for 64bit NOP.
1403
1404 2006-06-06  Ben Elliston  <bje@au.ibm.com>
1405             Anton Blanchard  <anton@samba.org>
1406
1407         * ppc.h (PPC_OPCODE_POWER6): Define.
1408         Adjust whitespace.
1409
1410 2006-06-05  Thiemo Seufer  <ths@mips.com>
1411
1412         * mips.h: Improve description of MT flags.
1413
1414 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
1415
1416         * m68k.h (mcf_mask): Define.
1417
1418 2006-05-05  Thiemo Seufer  <ths@mips.com>
1419             David Ung  <davidu@mips.com>
1420
1421         * mips.h (enum): Add macro M_CACHE_AB.
1422
1423 2006-05-04  Thiemo Seufer  <ths@mips.com>
1424             Nigel Stephens  <nigel@mips.com>
1425             David Ung  <davidu@mips.com>
1426
1427         * mips.h: Add INSN_SMARTMIPS define.
1428
1429 2006-04-30  Thiemo Seufer  <ths@mips.com>
1430             David Ung  <davidu@mips.com>
1431
1432         * mips.h: Defines udi bits and masks.  Add description of
1433         characters which may appear in the args field of udi
1434         instructions.
1435
1436 2006-04-26  Thiemo Seufer  <ths@networkno.de>
1437
1438         * mips.h: Improve comments describing the bitfield instruction
1439         fields.
1440
1441 2006-04-26  Julian Brown  <julian@codesourcery.com>
1442
1443         * arm.h (FPU_VFP_EXT_V3): Define constant.
1444         (FPU_NEON_EXT_V1): Likewise.
1445         (FPU_VFP_HARD): Update.
1446         (FPU_VFP_V3): Define macro.
1447         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1448
1449 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
1450
1451         * avr.h (AVR_ISA_PWMx): New.
1452
1453 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
1454
1455         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1456         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1457         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1458         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1459         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1460
1461 2006-03-10  Paul Brook  <paul@codesourcery.com>
1462
1463         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1464
1465 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1466
1467         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1468         first.  Correct mask of bb "B" opcode.
1469
1470 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
1471
1472         * i386.h (i386_optab): Support Intel Merom New Instructions.
1473
1474 2006-02-24  Paul Brook  <paul@codesourcery.com>
1475
1476         * arm.h: Add V7 feature bits.
1477
1478 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
1479
1480         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1481
1482 2006-01-31  Paul Brook  <paul@codesourcery.com>
1483         Richard Earnshaw <rearnsha@arm.com>
1484
1485         * arm.h: Use ARM_CPU_FEATURE.
1486         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1487         (arm_feature_set): Change to a structure.
1488         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1489         ARM_FEATURE): New macros.
1490
1491 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
1492
1493         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1494         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1495         (ADD_PC_INCR_OPCODE): Don't define.
1496
1497 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
1498
1499         PR gas/1874
1500         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1501
1502 2005-11-14  David Ung  <davidu@mips.com>
1503
1504         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1505         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1506         save/restore encoding of the args field.
1507
1508 2005-10-28  Dave Brolley  <brolley@redhat.com>
1509
1510         Contribute the following changes:
1511         2005-02-16  Dave Brolley  <brolley@redhat.com>
1512
1513         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1514         cgen_isa_mask_* to cgen_bitset_*.
1515         * cgen.h: Likewise.
1516
1517         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
1518
1519         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1520         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1521         (CGEN_CPU_TABLE): Make isas a ponter.
1522
1523         2003-09-29  Dave Brolley  <brolley@redhat.com>
1524
1525         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1526         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1527         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1528
1529         2002-12-13  Dave Brolley  <brolley@redhat.com>
1530
1531         * cgen.h (symcat.h): #include it.
1532         (cgen-bitset.h): #include it.
1533         (CGEN_ATTR_VALUE_TYPE): Now a union.
1534         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1535         (CGEN_ATTR_ENTRY): 'value' now unsigned.
1536         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1537         * cgen-bitset.h: New file.
1538
1539 2005-09-30  Catherine Moore  <clm@cm00re.com>
1540
1541         * bfin.h: New file.
1542
1543 2005-10-24  Jan Beulich  <jbeulich@novell.com>
1544
1545         * ia64.h (enum ia64_opnd): Move memory operand out of set of
1546         indirect operands.
1547
1548 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1549
1550         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
1551         Add FLAG_STRICT to pa10 ftest opcode.
1552
1553 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1554
1555         * hppa.h (pa_opcodes): Remove lha entries.
1556
1557 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1558
1559         * hppa.h (FLAG_STRICT): Revise comment.
1560         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
1561         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
1562         entries for "fdc".
1563
1564 2005-09-30  Catherine Moore  <clm@cm00re.com>
1565
1566         * bfin.h: New file.
1567
1568 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1569
1570         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1571
1572 2005-09-06  Chao-ying Fu  <fu@mips.com>
1573
1574         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1575         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1576         define.
1577         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1578         (INSN_ASE_MASK): Update to include INSN_MT.
1579         (INSN_MT): New define for MT ASE.
1580
1581 2005-08-25  Chao-ying Fu  <fu@mips.com>
1582
1583         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1584         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1585         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1586         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1587         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1588         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1589         instructions.
1590         (INSN_DSP): New define for DSP ASE.
1591
1592 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
1593
1594         * a29k.h: Delete.
1595
1596 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
1597
1598         * ppc.h (PPC_OPCODE_E300): Define.
1599
1600 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
1601
1602         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1603
1604 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1605
1606         PR gas/336
1607         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1608         and pitlb.
1609
1610 2005-07-27  Jan Beulich  <jbeulich@novell.com>
1611
1612         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1613         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1614         Add movq-s as 64-bit variants of movd-s.
1615
1616 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1617
1618         * hppa.h: Fix punctuation in comment.
1619
1620         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
1621         implicit space-register addressing.  Set space-register bits on opcodes
1622         using implicit space-register addressing.  Add various missing pa20
1623         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
1624         space-register addressing.  Use "fE" instead of "fe" in various
1625         fstw opcodes.
1626
1627 2005-07-18  Jan Beulich  <jbeulich@novell.com>
1628
1629         * i386.h (i386_optab): Operands of aam and aad are unsigned.
1630
1631 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
1632
1633         * i386.h (i386_optab): Support Intel VMX Instructions.
1634
1635 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1636
1637         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1638
1639 2005-07-05  Jan Beulich  <jbeulich@novell.com>
1640
1641         * i386.h (i386_optab): Add new insns.
1642
1643 2005-07-01  Nick Clifton  <nickc@redhat.com>
1644
1645         * sparc.h: Add typedefs to structure declarations.
1646
1647 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
1648
1649         PR 1013
1650         * i386.h (i386_optab): Update comments for 64bit addressing on
1651         mov. Allow 64bit addressing for mov and movq.
1652
1653 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1654
1655         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1656         respectively, in various floating-point load and store patterns.
1657
1658 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1659
1660         * hppa.h (FLAG_STRICT): Correct comment.
1661         (pa_opcodes): Update load and store entries to allow both PA 1.X and
1662         PA 2.0 mneumonics when equivalent.  Entries with cache control
1663         completers now require PA 1.1.  Adjust whitespace.
1664
1665 2005-05-19  Anton Blanchard  <anton@samba.org>
1666
1667         * ppc.h (PPC_OPCODE_POWER5): Define.
1668
1669 2005-05-10  Nick Clifton  <nickc@redhat.com>
1670
1671         * Update the address and phone number of the FSF organization in
1672         the GPL notices in the following files:
1673         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1674         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1675         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1676         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1677         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1678         tic54x.h, tic80.h, v850.h, vax.h
1679
1680 2005-05-09  Jan Beulich  <jbeulich@novell.com>
1681
1682         * i386.h (i386_optab): Add ht and hnt.
1683
1684 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
1685
1686         * i386.h: Insert hyphens into selected VIA PadLock extensions.
1687         Add xcrypt-ctr.  Provide aliases without hyphens.
1688
1689 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
1690
1691         Moved from ../ChangeLog
1692
1693         2005-04-12  Paul Brook  <paul@codesourcery.com>
1694         * m88k.h: Rename psr macros to avoid conflicts.
1695
1696         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
1697         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1698         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1699         and ARM_ARCH_V6ZKT2.
1700
1701         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
1702         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1703         Remove redundant instruction types.
1704         (struct argument): X_op - new field.
1705         (struct cst4_entry): Remove.
1706         (no_op_insn): Declare.
1707
1708         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
1709         * crx.h (enum argtype): Rename types, remove unused types.
1710
1711         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
1712         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1713         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1714         (enum operand_type): Rearrange operands, edit comments.
1715         replace us<N> with ui<N> for unsigned immediate.
1716         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1717         displacements (respectively).
1718         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1719         (instruction type): Add NO_TYPE_INS.
1720         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1721         (operand_entry): New field - 'flags'.
1722         (operand flags): New.
1723
1724         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
1725         * crx.h (operand_type): Remove redundant types i3, i4,
1726         i5, i8, i12.
1727         Add new unsigned immediate types us3, us4, us5, us16.
1728
1729 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
1730
1731         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1732         adjust them accordingly.
1733
1734 2005-04-01  Jan Beulich  <jbeulich@novell.com>
1735
1736         * i386.h (i386_optab): Add rdtscp.
1737
1738 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
1739
1740         * i386.h (i386_optab): Don't allow the `l' suffix for moving
1741         between memory and segment register. Allow movq for moving between
1742         general-purpose register and segment register.
1743
1744 2005-02-09  Jan Beulich  <jbeulich@novell.com>
1745
1746         PR gas/707
1747         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1748         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1749         fnstsw.
1750
1751 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
1752
1753         * m68k.h (m68008, m68ec030, m68882): Remove.
1754         (m68k_mask): New.
1755         (cpu_m68k, cpu_cf): New.
1756         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1757         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1758
1759 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
1760
1761         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
1762         * cgen.h (enum cgen_parse_operand_type): Add
1763         CGEN_PARSE_OPERAND_SYMBOLIC.
1764
1765 2005-01-21  Fred Fish  <fnf@specifixinc.com>
1766
1767         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1768         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1769         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1770
1771 2005-01-19  Fred Fish  <fnf@specifixinc.com>
1772
1773         * mips.h (struct mips_opcode): Add new pinfo2 member.
1774         (INSN_ALIAS): New define for opcode table entries that are
1775         specific instances of another entry, such as 'move' for an 'or'
1776         with a zero operand.
1777         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1778         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1779
1780 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
1781
1782         * mips.h (CPU_RM9000): Define.
1783         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1784
1785 2004-11-25 Jan Beulich  <jbeulich@novell.com>
1786
1787         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1788         to/from test registers are illegal in 64-bit mode. Add missing
1789         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1790         (previously one had to explicitly encode a rex64 prefix). Re-enable
1791         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1792         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1793
1794 2004-11-23 Jan Beulich  <jbeulich@novell.com>
1795
1796         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1797         available only with SSE2. Change the MMX additions introduced by SSE
1798         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1799         instructions by their now designated identifier (since combining i686
1800         and 3DNow! does not really imply 3DNow!A).
1801
1802 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
1803
1804         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1805         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1806
1807 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
1808             Vineet Sharma      <vineets@noida.hcltech.com>
1809
1810         * maxq.h: New file: Disassembly information for the maxq port.
1811
1812 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
1813
1814         * i386.h (i386_optab): Put back "movzb".
1815
1816 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
1817
1818         * cris.h (enum cris_insn_version_usage): Tweak formatting and
1819         comments.  Remove member cris_ver_sim.  Add members
1820         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1821         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1822         (struct cris_support_reg, struct cris_cond15): New types.
1823         (cris_conds15): Declare.
1824         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1825         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1826         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1827         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1828         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1829         SIZE_FIELD_UNSIGNED.
1830
1831 2004-11-04 Jan Beulich  <jbeulich@novell.com>
1832
1833         * i386.h (sldx_Suf): Remove.
1834         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1835         (q_FP): Define, implying no REX64.
1836         (x_FP, sl_FP): Imply FloatMF.
1837         (i386_optab): Split reg and mem forms of moving from segment registers
1838         so that the memory forms can ignore the 16-/32-bit operand size
1839         distinction. Adjust a few others for Intel mode. Remove *FP uses from
1840         all non-floating-point instructions. Unite 32- and 64-bit forms of
1841         movsx, movzx, and movd. Adjust floating point operations for the above
1842         changes to the *FP macros. Add DefaultSize to floating point control
1843         insns operating on larger memory ranges. Remove left over comments
1844         hinting at certain insns being Intel-syntax ones where the ones
1845         actually meant are already gone.
1846
1847 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
1848
1849         * crx.h: Add COPS_REG_INS - Coprocessor Special register
1850         instruction type.
1851
1852 2004-09-30  Paul Brook  <paul@codesourcery.com>
1853
1854         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1855         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1856
1857 2004-09-11  Theodore A. Roth  <troth@openavr.org>
1858
1859         * avr.h: Add support for
1860         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1861
1862 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
1863
1864         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1865
1866 2004-08-24  Dmitry Diky  <diwil@spec.ru>
1867
1868         * msp430.h (msp430_opc): Add new instructions.
1869         (msp430_rcodes): Declare new instructions.
1870         (msp430_hcodes): Likewise..
1871
1872 2004-08-13  Nick Clifton  <nickc@redhat.com>
1873
1874         PR/301
1875         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1876         processors.
1877
1878 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
1879
1880         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1881
1882 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
1883
1884         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1885
1886 2004-07-21  Jan Beulich  <jbeulich@novell.com>
1887
1888         * i386.h: Adjust instruction descriptions to better match the
1889         specification.
1890
1891 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
1892
1893         * arm.h: Remove all old content.  Replace with architecture defines
1894         from gas/config/tc-arm.c.
1895
1896 2004-07-09  Andreas Schwab  <schwab@suse.de>
1897
1898         * m68k.h: Fix comment.
1899
1900 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
1901
1902         * crx.h: New file.
1903
1904 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
1905
1906         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1907
1908 2004-05-24  Peter Barada  <peter@the-baradas.com>
1909
1910         * m68k.h: Add 'size' to m68k_opcode.
1911
1912 2004-05-05  Peter Barada  <peter@the-baradas.com>
1913
1914         * m68k.h: Switch from ColdFire chip name to core variant.
1915
1916 2004-04-22  Peter Barada  <peter@the-baradas.com>
1917
1918         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
1919         descriptions for new EMAC cases.
1920         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1921         handle Motorola MAC syntax.
1922         Allow disassembly of ColdFire V4e object files.
1923
1924 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
1925
1926         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
1927
1928 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
1929
1930         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1931
1932 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1933
1934         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1935
1936 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1937
1938         * i386.h (i386_optab): Added xstore/xcrypt insns.
1939
1940 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1941
1942         * h8300.h (32bit ldc/stc): Add relaxing support.
1943
1944 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
1945
1946         * h8300.h (BITOP): Pass MEMRELAX flag.
1947
1948 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1949
1950         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1951         except for the H8S.
1952
1953 For older changes see ChangeLog-9103
1954 \f
1955 Copyright (C) 2004-2012 Free Software Foundation, Inc.
1956
1957 Copying and distribution of this file, with or without modification,
1958 are permitted in any medium without royalty provided the copyright
1959 notice and this notice are preserved.
1960
1961 Local Variables:
1962 mode: change-log
1963 left-margin: 8
1964 fill-column: 74
1965 version-control: never
1966 End: