include/opcode/ChangeLog

   1 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
   2
   3         * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
   4         (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
   5         (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
   6         (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
   7         (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
   8         (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
   9         (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
  10         (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
  11         (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
  12         (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
  13         (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
  14         (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
  15         (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
  16         Rename to...
  17         (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
  18         (M_USD_AB): ...these.
  19
  20 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  21
  22         * mips.h: Remove documentation of "[" and "]".  Update documentation
  23         of "k" and the MDMX formats.
  24
  25 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  26
  27         * mips.h: Update documentation of "+s" and "+S".
  28
  29 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  30
  31         * mips.h: Document "+i".
  32
  33 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  34
  35         * mips.h: Remove "mi" documentation.  Update "mh" documentation.
  36         (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
  37         Delete.
  38         (INSN2_WRITE_GPR_MHI): Rename to...
  39         (INSN2_WRITE_GPR_MH): ...this.
  40
  41 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  42
  43         * mips.h: Remove documentation of "+D" and "+T".
  44
  45 2013-06-26  Richard Sandiford  <rdsandiford@googlemail.com>
  46
  47         * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
  48         Use "source" rather than "destination" for microMIPS "G".
  49
  50 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
  51
  52         * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
  53         values.
  54
  55 2013-06-23  Richard Sandiford  <rdsandiford@googlemail.com>
  56
  57         * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
  58
  59 2013-06-17  Catherine Moore  <clm@codesourcery.com>
  60             Maciej W. Rozycki  <macro@codesourcery.com>
  61             Chao-Ying Fu  <fu@mips.com>
  62
  63         * mips.h (OP_SH_EVAOFFSET): Define.
  64         (OP_MASK_EVAOFFSET): Define.
  65         (INSN_ASE_MASK): Delete.
  66         (ASE_EVA): Define.
  67         (M_CACHEE_AB, M_CACHEE_OB): New.
  68         (M_LBE_OB, M_LBE_AB): New.
  69         (M_LBUE_OB, M_LBUE_AB): New.
  70         (M_LHE_OB, M_LHE_AB): New.
  71         (M_LHUE_OB, M_LHUE_AB): New.
  72         (M_LLE_AB, M_LLE_OB): New.
  73         (M_LWE_OB, M_LWE_AB): New.
  74         (M_LWLE_AB, M_LWLE_OB): New.
  75         (M_LWRE_AB, M_LWRE_OB): New.
  76         (M_PREFE_AB, M_PREFE_OB): New.
  77         (M_SCE_AB, M_SCE_OB): New.
  78         (M_SBE_OB, M_SBE_AB): New.
  79         (M_SHE_OB, M_SHE_AB): New.
  80         (M_SWE_OB, M_SWE_AB): New.
  81         (M_SWLE_AB, M_SWLE_OB): New.
  82         (M_SWRE_AB, M_SWRE_OB): New.
  83         (MICROMIPSOP_SH_EVAOFFSET): Define.
  84         (MICROMIPSOP_MASK_EVAOFFSET): Define.
  85
  86 2013-06-12  Sandra Loosemore  <sandra@codesourcery.com>
  87
  88         * nios2.h (OP_MATCH_ERET): Correct eret encoding.
  89
  90 2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
  91
  92         * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
  93
  94 2013-05-09  Andrew Pinski  <apinski@cavium.com>
  95
  96         * mips.h (OP_MASK_CODE10): Correct definition.
  97         (OP_SH_CODE10): Likewise.
  98         Add a comment that "+J" is used now for OP_*CODE10.
  99         (INSN_ASE_MASK): Update.
 100         (INSN_VIRT): New macro.
 101         (INSN_VIRT64): New macro
 102
 103 2013-05-02  Nick Clifton  <nickc@redhat.com>
 104
 105         * msp430.h: Add patterns for MSP430X instructions.
 106
 107 2013-04-06  David S. Miller  <davem@davemloft.net>
 108
 109         * sparc.h (F_PREFERRED): Define.
 110         (F_PREF_ALIAS): Define.
 111
 112 2013-04-03  Nick Clifton  <nickc@redhat.com>
 113
 114         * v850.h (V850_INVERSE_PCREL): Define.
 115
 116 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 117
 118         PR binutils/15068
 119         * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
 120
 121 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 122
 123         PR binutils/15068
 124         * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
 125         Add 16-bit opcodes.
 126         * tic6xc-opcode-table.h: Add 16-bit insns.
 127         * tic6x.h: Add support for 16-bit insns.
 128
 129 2013-03-21  Michael Schewe  <michael.schewe@gmx.net>
 130
 131         * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
 132         and mov.b/w/l Rs,@(d:32,ERd).
 133
 134 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 135
 136         PR gas/15082
 137         * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
 138         from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
 139         tic6x_operand_xregpair operand coding type.
 140         Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
 141         opcode field, usu ORXREGD1324 for the src2 operand and remove the
 142         TIC6X_FLAG_NO_CROSS.
 143
 144 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 145
 146         PR gas/15095
 147         * tic6x.h (enum tic6x_coding_method): Add
 148         tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
 149         separately the msb and lsb of a register pair.  This is needed to
 150         encode the opcodes in the same way as TI assembler does.
 151         * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
 152         and rsqrdp opcodes to use the new field coding types.
 153
 154 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 155
 156         * arm.h (CRC_EXT_ARMV8): New constant.
 157         (ARCH_CRC_ARMV8): New macro.
 158
 159 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
 160
 161         * aarch64.h (AARCH64_FEATURE_CRC): New macro.
 162
 163 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
 164             Andrew Jenner <andrew@codesourcery.com>
 165
 166         Based on patches from Altera Corporation.
 167
 168         * nios2.h: New file.
 169
 170 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
 171
 172         * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
 173
 174 2013-01-28  Alexis Deruelle  <alexis.deruelle@gmail.com>
 175
 176         PR gas/15069
 177         * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
 178
 179 2013-01-24  Nick Clifton  <nickc@redhat.com>
 180
 181         * v850.h: Add e3v5 support.
 182
 183 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
 184
 185         * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
 186
 187 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
 188
 189         * ppc.h (PPC_OPCODE_POWER8): New define.
 190         (PPC_OPCODE_HTM): Likewise.
 191
 192 2013-01-10  Will Newton <will.newton@imgtec.com>
 193
 194         * metag.h: New file.
 195
 196 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 197
 198         * cr16.h (make_instruction): Rename to cr16_make_instruction.
 199         (match_opcode): Rename to cr16_match_opcode.
 200
 201 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
 202
 203         * mips.h: Add support for r5900 instructions including lq and sq.
 204
 205 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 206
 207         * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
 208         (make_instruction,match_opcode): Added function prototypes.
 209         (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
 210
 211 2012-11-23  Alan Modra  <amodra@gmail.com>
 212
 213         * ppc.h (ppc_parse_cpu): Update prototype.
 214
 215 2012-10-14  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 216
 217         * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
 218         opcodes.  Likewise, use "cM" instead of "cm" in fstqs opcodes.
 219
 220 2012-10-04  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 221
 222         * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
 223
 224 2012-09-04  Sergey A. Guriev <sergey.a.guriev@intel.com>
 225
 226         * ia64.h (ia64_opnd): Add new operand types.
 227
 228 2012-08-21  David S. Miller  <davem@davemloft.net>
 229
 230         * sparc.h (F3F4): New macro.
 231
 232 2012-08-13  Ian Bolton  <ian.bolton@arm.com>
 233             Laurent Desnogues  <laurent.desnogues@arm.com>
 234             Jim MacArthur  <jim.macarthur@arm.com>
 235             Marcus Shawcroft  <marcus.shawcroft@arm.com>
 236             Nigel Stephens  <nigel.stephens@arm.com>
 237             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 238             Richard Earnshaw  <rearnsha@arm.com>
 239             Sofiane Naci  <sofiane.naci@arm.com>
 240             Tejas Belagod  <tejas.belagod@arm.com>
 241             Yufeng Zhang  <yufeng.zhang@arm.com>
 242
 243         * aarch64.h: New file.
 244
 245 2012-08-13  Richard Sandiford  <rdsandiford@googlemail.com>
 246             Maciej W. Rozycki  <macro@codesourcery.com>
 247
 248         * mips.h (mips_opcode): Add the exclusions field.
 249         (OPCODE_IS_MEMBER): Remove macro.
 250         (cpu_is_member): New inline function.
 251         (opcode_is_member): Likewise.
 252
 253 2012-07-31  Chao-Ying Fu  <fu@mips.com>
 254             Catherine Moore  <clm@codesourcery.com>
 255             Maciej W. Rozycki  <macro@codesourcery.com>
 256
 257         * mips.h: Document microMIPS DSP ASE usage.
 258         (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
 259         microMIPS DSP ASE support.
 260         (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
 261         (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
 262         (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
 263         (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
 264         (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
 265         (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
 266         (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
 267
 268 2012-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 269
 270         * mips.h: Fix a typo in description.
 271
 272 2012-06-07  Georg-Johann Lay  <avr@gjlay.de>
 273
 274         * avr.h: (AVR_ISA_XCH): New define.
 275         (AVR_ISA_XMEGA): Use it.
 276         (XCH, LAS, LAT, LAC): New XMEGA opcodes.
 277
 278 2012-05-15  James Murray <jsm@jsm-net.demon.co.uk>
 279
 280         * m68hc11.h: Add XGate definitions.
 281         (struct m68hc11_opcode): Add xg_mask field.
 282
 283 2012-05-14  Catherine Moore  <clm@codesourcery.com>
 284             Maciej W. Rozycki  <macro@codesourcery.com>
 285             Rhonda Wittels  <rhonda@codesourcery.com>
 286
 287         * ppc.h (PPC_OPCODE_VLE): New definition.
 288         (PPC_OP_SA): New macro.
 289         (PPC_OP_SE_VLE): New macro.
 290         (PPC_OP): Use a variable shift amount.
 291         (powerpc_operand): Update comments.
 292         (PPC_OPSHIFT_INV): New macro.
 293         (PPC_OPERAND_CR): Replace with...
 294         (PPC_OPERAND_CR_BIT): ...this and
 295         (PPC_OPERAND_CR_REG): ...this.
 296
 297
 298 2012-05-03  Sean Keys  <skeys@ipdatasys.com>
 299
 300         * xgate.h: Header file for XGATE assembler.
 301
 302 2012-04-27  David S. Miller  <davem@davemloft.net>
 303
 304         * sparc.h: Document new arg code' )' for crypto RS3
 305         immediates.
 306
 307         * sparc.h (struct sparc_opcode): New field 'hwcaps'.
 308         F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
 309         F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
 310         F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
 311         (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
 312         HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
 313         HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
 314         HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
 315         HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
 316         HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
 317         HWCAP_CBCOND, HWCAP_CRC32): New defines.
 318
 319 2012-03-10  Edmar Wienskoski  <edmar@freescale.com>
 320
 321         * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
 322
 323 2012-02-27  Alan Modra  <amodra@gmail.com>
 324
 325         * crx.h (cst4_map): Update declaration.
 326
 327 2012-02-25  Walter Lee  <walt@tilera.com>
 328
 329         * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
 330         TILEGX_OPC_LD_TLS.
 331         * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
 332         TILEPRO_OPC_LW_TLS_SN.
 333
 334 2012-02-08  H.J. Lu  <hongjiu.lu@intel.com>
 335
 336         * i386.h (XACQUIRE_PREFIX_OPCODE): New.
 337         (XRELEASE_PREFIX_OPCODE): Likewise.
 338
 339 2011-12-08  Andrew Pinski  <apinski@cavium.com>
 340             Adam Nemet  <anemet@caviumnetworks.com>
 341
 342         * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
 343         (INSN_OCTEON2): New macro.
 344         (CPU_OCTEON2): New macro.
 345         (OPCODE_IS_MEMBER): Add Octeon2.
 346
 347 2011-11-29  Andrew Pinski  <apinski@cavium.com>
 348
 349         * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
 350         (INSN_OCTEONP): New macro.
 351         (CPU_OCTEONP): New macro.
 352         (OPCODE_IS_MEMBER): Add Octeon+.
 353         (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
 354
 355 2011-11-01  DJ Delorie  <dj@redhat.com>
 356
 357         * rl78.h: New file.
 358
 359 2011-10-24  Maciej W. Rozycki  <macro@codesourcery.com>
 360
 361         * mips.h: Fix a typo in description.
 362
 363 2011-09-21  David S. Miller  <davem@davemloft.net>
 364
 365         * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
 366         (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
 367         F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
 368         F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
 369
 370 2011-08-09  Chao-ying Fu  <fu@mips.com>
 371             Maciej W. Rozycki  <macro@codesourcery.com>
 372
 373         * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
 374         (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
 375         (INSN_ASE_MASK): Add the MCU bit.
 376         (INSN_MCU): New macro.
 377         (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
 378         (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
 379
 380 2011-08-09  Maciej W. Rozycki  <macro@codesourcery.com>
 381
 382         * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
 383         (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
 384         (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
 385         (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
 386         (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
 387         (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
 388         (INSN2_READ_GPR_MMN): Likewise.
 389         (INSN2_READ_FPR_D): Change the bit used.
 390         (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
 391         (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
 392         (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
 393         (INSN2_COND_BRANCH): Likewise.
 394         (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
 395         (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
 396         (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
 397         (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
 398         (INSN2_MOD_GPR_MN): Likewise.
 399
 400 2011-08-05  David S. Miller  <davem@davemloft.net>
 401
 402         * sparc.h: Document new format codes '4', '5', and '('.
 403         (OPF_LOW4, RS3): New macros.
 404
 405 2011-08-03  Maciej W. Rozycki  <macro@codesourcery.com>
 406
 407         * mips.h: Document the use of FP_D in MIPS16 mode.  Adjust the
 408         order of flags documented.
 409
 410 2011-07-29  Maciej W. Rozycki  <macro@codesourcery.com>
 411
 412         * mips.h: Clarify the description of microMIPS instruction
 413         manipulation macros.
 414         (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
 415
 416 2011-07-24  Chao-ying Fu  <fu@mips.com>
 417             Maciej W. Rozycki  <macro@codesourcery.com>
 418
 419         * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
 420         (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
 421         (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
 422         (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
 423         (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
 424         (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
 425         (OP_MASK_RS3, OP_SH_RS3): Likewise.
 426         (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
 427         (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
 428         (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
 429         (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
 430         (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
 431         (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
 432         (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
 433         (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
 434         (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
 435         (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
 436         (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
 437         (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
 438         (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
 439         (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
 440         (INSN_WRITE_GPR_S): New macro.
 441         (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
 442         (INSN2_READ_FPR_D): Likewise.
 443         (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
 444         (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
 445         (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
 446         (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
 447         (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
 448         (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
 449         (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
 450         (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
 451         (CPU_MICROMIPS): New macro.
 452         (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
 453         (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
 454         (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
 455         (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
 456         (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
 457         (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
 458         (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
 459         (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
 460         (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
 461         (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
 462         (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
 463         (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
 464         (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
 465         (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
 466         (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
 467         (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
 468         (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
 469         (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
 470         (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
 471         (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
 472         (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
 473         (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
 474         (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
 475         (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
 476         (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
 477         (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
 478         (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
 479         (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
 480         (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
 481         (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
 482         (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
 483         (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
 484         (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
 485         (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
 486         (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
 487         (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
 488         (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
 489         (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
 490         (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
 491         (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
 492         (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
 493         (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
 494         (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
 495         (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
 496         (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
 497         (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
 498         (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
 499         (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
 500         (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
 501         (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
 502         (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
 503         (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
 504         (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
 505         (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
 506         (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
 507         (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
 508         (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
 509         (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
 510         (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
 511         (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
 512         (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
 513         (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
 514         (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
 515         (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
 516         (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
 517         (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
 518         (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
 519         (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
 520         (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
 521         (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
 522         (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
 523         (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
 524         (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
 525         (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
 526         (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
 527         (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
 528         (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
 529         (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
 530         (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
 531         (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
 532         (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
 533         (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
 534         (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
 535         (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
 536         (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
 537         (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
 538         (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
 539         (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
 540         (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
 541         (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
 542         (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
 543         (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
 544         (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
 545         (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
 546         (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
 547         (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
 548         (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
 549         (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
 550         (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
 551         (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
 552         (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
 553         (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
 554         (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
 555         (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
 556         (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
 557         (micromips_opcodes): New declaration.
 558         (bfd_micromips_num_opcodes): Likewise.
 559
 560 2011-07-24  Maciej W. Rozycki  <macro@codesourcery.com>
 561
 562         * mips.h (INSN_TRAP): Rename to...
 563         (INSN_NO_DELAY_SLOT): ... this.
 564         (INSN_SYNC): Remove macro.
 565
 566 2011-07-01  Eric B. Weddington  <eric.weddington@atmel.com>
 567
 568         * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
 569         a duplicate of AVR_ISA_SPM.
 570
 571 2011-07-01  Nick Clifton  <nickc@redhat.com>
 572
 573         * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
 574
 575 2011-06-18  Robin Getz  <robin.getz@analog.com>
 576
 577         * bfin.h (is_macmod_signed): New func
 578
 579 2011-06-18  Mike Frysinger  <vapier@gentoo.org>
 580
 581         * bfin.h (is_macmod_pmove): Add missing space before func args.
 582         (is_macmod_hmove): Likewise.
 583
 584 2011-06-13  Walter Lee  <walt@tilera.com>
 585
 586         * tilegx.h: New file.
 587         * tilepro.h: New file.
 588
 589 2011-05-31  Paul Brook  <paul@codesourcery.com>
 590
 591         * arm.h (ARM_ARCH_V7R_IDIV): Define.
 592
 593 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 594
 595         * s390.h: Replace S390_OPERAND_REG_EVEN with
 596         S390_OPERAND_REG_PAIR.
 597
 598 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 599
 600         * s390.h: Add S390_OPCODE_REG_EVEN flag.
 601
 602 2011-04-18  Julian Brown  <julian@codesourcery.com>
 603
 604         * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
 605
 606 2011-04-11  Dan McDonald  <dan@wellkeeper.com>
 607
 608         PR gas/12296
 609         * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
 610
 611 2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>
 612
 613         * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
 614         New instruction set flags.
 615         (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
 616
 617 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 618
 619         * mips.h (M_PREF_AB): New enum value.
 620
 621 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 622
 623         * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
 624         M_IU): Define.
 625         (is_macmod_pmove, is_macmod_hmove): New functions.
 626
 627 2011-02-11  Mike Frysinger  <vapier@gentoo.org>
 628
 629         * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
 630
 631 2011-02-04  Bernd Schmidt  <bernds@codesourcery.com>
 632
 633         * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
 634         * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
 635
 636 2010-12-31  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 637
 638         PR gas/11395
 639         * hppa.h (pa_opcodes): Revert last change.  Exchange 32 and 64-bit
 640         "bb" entries.
 641
 642 2010-12-26  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 643
 644         PR gas/11395
 645         * hppa.h: Clear "d" bit in "add" and "sub" patterns.
 646
 647 2010-12-18  Richard Sandiford  <rdsandiford@googlemail.com>
 648
 649         * mips.h: Update commentary after last commit.
 650
 651 2010-12-18  Mingjie Xing  <mingjie.xing@gmail.com>
 652
 653         * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
 654         (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
 655         (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
 656
 657 2010-11-25  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 658
 659         * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
 660
 661 2010-11-23  Richard Sandiford  <rdsandiford@googlemail.com>
 662
 663         * mips.h: Fix previous commit.
 664
 665 2010-11-23  Maciej W. Rozycki  <macro@linux-mips.org>
 666
 667         * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
 668         (INSN_LOONGSON_3A): Clear bit 31.
 669
 670 2010-11-15  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 671
 672         PR gas/12198
 673         * arm.h (ARM_AEXT_V6M_ONLY): New define.
 674         (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
 675         (ARM_ARCH_V6M_ONLY): New define.
 676
 677 2010-11-11  Mingming Sun  <mingm.sun@gmail.com>
 678
 679         * mips.h (INSN_LOONGSON_3A): Defined.
 680         (CPU_LOONGSON_3A): Defined.
 681         (OPCODE_IS_MEMBER): Add LOONGSON_3A.
 682
 683 2010-10-09  Matt Rice  <ratmice@gmail.com>
 684
 685         * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
 686         (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
 687
 688 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 689
 690         * arm.h (ARM_EXT_VIRT): New define.
 691         (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
 692         (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
 693         Extensions.
 694
 695 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 696
 697         * arm.h (ARM_AEXT_ADIV): New define.
 698         (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
 699
 700 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 701
 702         * arm.h (ARM_EXT_OS): New define.
 703         (ARM_AEXT_V6SM): Likewise.
 704         (ARM_ARCH_V6SM): Likewise.
 705
 706 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 707
 708         * arm.h (ARM_EXT_MP): Add.
 709         (ARM_ARCH_V7A_MP): Likewise.
 710
 711 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 712
 713         * bfin.h: Declare pseudoChr structs/defines.
 714
 715 2010-09-21  Mike Frysinger  <vapier@gentoo.org>
 716
 717         * bfin.h: Strip trailing whitespace.
 718
 719 2010-07-29  DJ Delorie  <dj@redhat.com>
 720
 721         * rx.h (RX_Operand_Type): Add TwoReg.
 722         (RX_Opcode_ID): Remove ediv and ediv2.
 723
 724 2010-07-27  DJ Delorie  <dj@redhat.com>
 725
 726         * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
 727
 728 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
 729             Ina Pandit  <ina.pandit@kpitcummins.com>
 730
 731         * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
 732         PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
 733         PROCESSOR_V850E2_ALL.
 734         Remove PROCESSOR_V850EA support.
 735         (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
 736         V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
 737         V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
 738         V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
 739         V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
 740         V850_OPERAND_PERCENT.
 741         Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
 742         V850_NOT_R0.
 743         Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
 744         and V850E_PUSH_POP
 745
 746 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 747
 748         * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
 749         (MIPS16_INSN_BRANCH): Rename to...
 750         (MIPS16_INSN_COND_BRANCH): ... this.
 751
 752 2010-07-03  Alan Modra  <amodra@gmail.com>
 753
 754         * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
 755         Renumber other PPC_OPCODE defines.
 756
 757 2010-07-03  Alan Modra  <amodra@gmail.com>
 758
 759         * ppc.h (PPC_OPCODE_COMMON): Expand comment.
 760
 761 2010-06-29  Alan Modra  <amodra@gmail.com>
 762
 763         * maxq.h: Delete file.
 764
 765 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 766
 767         * ppc.h (PPC_OPCODE_E500): Define.
 768
 769 2010-05-26  Catherine Moore  <clm@codesourcery.com>
 770
 771         * opcode/mips.h (INSN_MIPS16): Remove.
 772
 773 2010-04-21  Joseph Myers  <joseph@codesourcery.com>
 774
 775         * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
 776
 777 2010-04-15  Nick Clifton  <nickc@redhat.com>
 778
 779         * alpha.h: Update copyright notice to use GPLv3.
 780         * arc.h: Likewise.
 781         * arm.h: Likewise.
 782         * avr.h: Likewise.
 783         * bfin.h: Likewise.
 784         * cgen.h: Likewise.
 785         * convex.h: Likewise.
 786         * cr16.h: Likewise.
 787         * cris.h: Likewise.
 788         * crx.h: Likewise.
 789         * d10v.h: Likewise.
 790         * d30v.h: Likewise.
 791         * dlx.h: Likewise.
 792         * h8300.h: Likewise.
 793         * hppa.h: Likewise.
 794         * i370.h: Likewise.
 795         * i386.h: Likewise.
 796         * i860.h: Likewise.
 797         * i960.h: Likewise.
 798         * ia64.h: Likewise.
 799         * m68hc11.h: Likewise.
 800         * m68k.h: Likewise.
 801         * m88k.h: Likewise.
 802         * maxq.h: Likewise.
 803         * mips.h: Likewise.
 804         * mmix.h: Likewise.
 805         * mn10200.h: Likewise.
 806         * mn10300.h: Likewise.
 807         * msp430.h: Likewise.
 808         * np1.h: Likewise.
 809         * ns32k.h: Likewise.
 810         * or32.h: Likewise.
 811         * pdp11.h: Likewise.
 812         * pj.h: Likewise.
 813         * pn.h: Likewise.
 814         * ppc.h: Likewise.
 815         * pyr.h: Likewise.
 816         * rx.h: Likewise.
 817         * s390.h: Likewise.
 818         * score-datadep.h: Likewise.
 819         * score-inst.h: Likewise.
 820         * sparc.h: Likewise.
 821         * spu-insns.h: Likewise.
 822         * spu.h: Likewise.
 823         * tic30.h: Likewise.
 824         * tic4x.h: Likewise.
 825         * tic54x.h: Likewise.
 826         * tic80.h: Likewise.
 827         * v850.h: Likewise.
 828         * vax.h: Likewise.
 829
 830 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
 831
 832         * tic6x-control-registers.h, tic6x-insn-formats.h,
 833         tic6x-opcode-table.h, tic6x.h: New.
 834
 835 2010-02-25  Wu Zhangjin  <wuzhangjin@gmail.com>
 836
 837         * mips.h: (LOONGSON2F_NOP_INSN): New macro.
 838
 839 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
 840
 841         * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
 842
 843 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 844
 845         * ia64.h (ia64_find_opcode): Remove argument name.
 846         (ia64_find_next_opcode): Likewise.
 847         (ia64_dis_opcode): Likewise.
 848         (ia64_free_opcode): Likewise.
 849         (ia64_find_dependency): Likewise.
 850
 851 2009-11-22  Doug Evans  <dje@sebabeach.org>
 852
 853         * cgen.h: Include bfd_stdint.h.
 854         (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
 855
 856 2009-11-18  Paul Brook  <paul@codesourcery.com>
 857
 858         * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
 859
 860 2009-11-17  Paul Brook  <paul@codesourcery.com>
 861         Daniel Jacobowitz  <dan@codesourcery.com>
 862
 863         * arm.h (ARM_EXT_V6_DSP): Define.
 864         (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
 865         (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
 866
 867 2009-11-04  DJ Delorie  <dj@redhat.com>
 868
 869         * rx.h (rx_decode_opcode) (mvtipl): Add.
 870         (mvtcp, mvfcp, opecp): Remove.
 871
 872 2009-11-02  Paul Brook  <paul@codesourcery.com>
 873
 874         * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
 875         FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
 876         (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
 877         FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
 878         FPU_ARCH_NEON_VFP_V4): Define.
 879
 880 2009-10-23  Doug Evans  <dje@sebabeach.org>
 881
 882         * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
 883         * cgen.h: Update.  Improve multi-inclusion macro name.
 884
 885 2009-10-02  Peter Bergner  <bergner@vnet.ibm.com>
 886
 887         * ppc.h (PPC_OPCODE_476): Define.
 888
 889 2009-10-01  Peter Bergner  <bergner@vnet.ibm.com>
 890
 891         * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
 892
 893 2009-09-29  DJ Delorie  <dj@redhat.com>
 894
 895         * rx.h: New file.
 896
 897 2009-09-22  Peter Bergner  <bergner@vnet.ibm.com>
 898
 899         * ppc.h (ppc_cpu_t): Typedef to uint64_t.
 900
 901 2009-09-21  Ben Elliston  <bje@au.ibm.com>
 902
 903         * ppc.h (PPC_OPCODE_PPCA2): New.
 904
 905 2009-09-05  Martin Thuresson  <martin@mtme.org>
 906
 907         * ia64.h (struct ia64_operand): Renamed member class to op_class.
 908
 909 2009-08-29  Martin Thuresson  <martin@mtme.org>
 910
 911         * tic30.h (template): Rename type template to
 912         insn_template. Updated code to use new name.
 913         * tic54x.h (template): Rename type template to
 914         insn_template.
 915
 916 2009-08-20  Nick Hudson  <nick.hudson@gmx.co.uk>
 917
 918         * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
 919
 920 2009-06-11  Anthony Green  <green@moxielogic.com>
 921
 922         * moxie.h (MOXIE_F3_PCREL): Define.
 923         (moxie_form3_opc_info): Grow.
 924
 925 2009-06-06  Anthony Green  <green@moxielogic.com>
 926
 927         * moxie.h (MOXIE_F1_M): Define.
 928
 929 2009-04-15  Anthony Green  <green@moxielogic.com>
 930
 931         * moxie.h: Created.
 932
 933 2009-04-06  DJ Delorie  <dj@redhat.com>
 934
 935         * h8300.h: Add relaxation attributes to MOVA opcodes.
 936
 937 2009-03-10  Alan Modra  <amodra@bigpond.net.au>
 938
 939         * ppc.h (ppc_parse_cpu): Declare.
 940
 941 2009-03-02  Qinwei  <qinwei@sunnorth.com.cn>
 942
 943         * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
 944         and _IMM11 for mbitclr and mbitset.
 945         * score-datadep.h: Update dependency information.
 946
 947 2009-02-26  Peter Bergner  <bergner@vnet.ibm.com>
 948
 949         * ppc.h (PPC_OPCODE_POWER7): New.
 950
 951 2009-02-06  Doug Evans  <dje@google.com>
 952
 953         * i386.h: Add comment regarding sse* insns and prefixes.
 954
 955 2009-02-03  Sandip Matte  <sandip@rmicorp.com>
 956
 957         * mips.h (INSN_XLR): Define.
 958         (INSN_CHIP_MASK): Update.
 959         (CPU_XLR): Define.
 960         (OPCODE_IS_MEMBER): Update.
 961         (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
 962
 963 2009-01-28  Doug Evans  <dje@google.com>
 964
 965         * opcode/i386.h: Add multiple inclusion protection.
 966         (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
 967         (EDI_REG_NUM): New macros.
 968         (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
 969         (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
 970         (REX_PREFIX_P): New macro.
 971
 972 2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
 973
 974         * ppc.h (struct powerpc_opcode): New field "deprecated".
 975         (PPC_OPCODE_NOPOWER4): Delete.
 976
 977 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
 978
 979         * mips.h: Define CPU_R14000, CPU_R16000.
 980         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
 981
 982 2008-11-18  Catherine Moore  <clm@codesourcery.com>
 983
 984         * arm.h (FPU_NEON_FP16): New.
 985         (FPU_ARCH_NEON_FP16): New.
 986
 987 2008-11-06  Chao-ying Fu  <fu@mips.com>
 988
 989         * mips.h: Doucument '1' for 5-bit sync type.
 990
 991 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
 992
 993         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
 994         IA64_RS_CR.
 995
 996 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
 997
 998         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
 999
1000 2008-07-30  Michael J. Eager  <eager@eagercon.com>
1001
1002         * ppc.h (PPC_OPCODE_405): Define.
1003         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1004
1005 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
1006
1007         * ppc.h (ppc_cpu_t): New typedef.
1008         (struct powerpc_opcode <flags>): Use it.
1009         (struct powerpc_operand <insert, extract>): Likewise.
1010         (struct powerpc_macro <flags>): Likewise.
1011
1012 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
1013
1014         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1015         Update comment before MIPS16 field descriptors to mention MIPS16.
1016         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1017         BBIT.
1018         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1019         New bit masks and shift counts for cins and exts.
1020
1021         * mips.h: Document new field descriptors +Q.
1022         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1023
1024 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
1025
1026         * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
1027         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1028
1029 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
1030
1031         * ppc.h: (PPC_OPCODE_E500MC): New.
1032
1033 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
1034
1035         * i386.h (MAX_OPERANDS): Set to 5.
1036         (MAX_MNEM_SIZE): Changed to 20.
1037
1038 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
1039
1040         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1041
1042 2008-03-09  Paul Brook  <paul@codesourcery.com>
1043
1044         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1045
1046 2008-03-04  Paul Brook  <paul@codesourcery.com>
1047
1048         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1049         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1050         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1051
1052 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
1053             Nick Clifton  <nickc@redhat.com>
1054
1055         PR 3134
1056         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1057         with a 32-bit displacement but without the top bit of the 4th byte
1058         set.
1059
1060 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1061
1062         * cr16.h (cr16_num_optab): Declared.
1063
1064 2008-02-14  Hakan Ardo  <hakan@debian.org>
1065
1066         PR gas/2626
1067         * avr.h (AVR_ISA_2xxe): Define.
1068
1069 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
1070
1071         * mips.h: Update copyright.
1072         (INSN_CHIP_MASK): New macro.
1073         (INSN_OCTEON): New macro.
1074         (CPU_OCTEON): New macro.
1075         (OPCODE_IS_MEMBER): Handle Octeon instructions.
1076
1077 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
1078
1079         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1080
1081 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
1082
1083         * avr.h (AVR_ISA_USB162): Add new opcode set.
1084         (AVR_ISA_AVR3): Likewise.
1085
1086 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
1087
1088         * mips.h (INSN_LOONGSON_2E): New.
1089         (INSN_LOONGSON_2F): New.
1090         (CPU_LOONGSON_2E): New.
1091         (CPU_LOONGSON_2F): New.
1092         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1093
1094 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
1095
1096         * mips.h (INSN_ISA*): Redefine certain values as an
1097         enumeration.  Update comments.
1098         (mips_isa_table): New.
1099         (ISA_MIPS*): Redefine to match enumeration.
1100         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1101         values.
1102
1103 2007-08-08  Ben Elliston  <bje@au.ibm.com>
1104
1105         * ppc.h (PPC_OPCODE_PPCPS): New.
1106
1107 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
1108
1109         * m68k.h: Document j K & E.
1110
1111 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
1112
1113         * cr16.h: New file for CR16 target.
1114
1115 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
1116
1117         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1118
1119 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
1120
1121         * m68k.h (mcfisa_c): New.
1122         (mcfusp, mcf_mask): Adjust.
1123
1124 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
1125
1126         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1127         (num_powerpc_operands): Declare.
1128         (PPC_OPERAND_SIGNED et al): Redefine as hex.
1129         (PPC_OPERAND_PLUS1): Define.
1130
1131 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
1132
1133         * i386.h (REX_MODE64): Renamed to ...
1134         (REX_W): This.
1135         (REX_EXTX): Renamed to ...
1136         (REX_R): This.
1137         (REX_EXTY): Renamed to ...
1138         (REX_X): This.
1139         (REX_EXTZ): Renamed to ...
1140         (REX_B): This.
1141
1142 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
1143
1144         * i386.h: Add entries from config/tc-i386.h and move tables
1145         to opcodes/i386-opc.h.
1146
1147 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
1148
1149         * i386.h (FloatDR): Removed.
1150         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1151
1152 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
1153
1154         * spu-insns.h: Add soma double-float insns.
1155
1156 2007-02-20  Thiemo Seufer  <ths@mips.com>
1157             Chao-Ying Fu  <fu@mips.com>
1158
1159         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1160         (INSN_DSPR2): Add flag for DSP R2 instructions.
1161         (M_BALIGN): New macro.
1162
1163 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
1164
1165         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1166         and Seg3ShortFrom with Shortform.
1167
1168 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
1169
1170         PR gas/4027
1171         * i386.h (i386_optab): Put the real "test" before the pseudo
1172         one.
1173
1174 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
1175
1176         * m68k.h (m68010up): OR fido_a.
1177
1178 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
1179
1180         * m68k.h (fido_a): New.
1181
1182 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
1183
1184         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1185         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1186         values.
1187
1188 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
1189
1190         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1191
1192 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
1193
1194         * score-inst.h (enum score_insn_type): Add Insn_internal.
1195
1196 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
1197             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
1198             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
1199             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
1200             Alan Modra  <amodra@bigpond.net.au>
1201
1202         * spu-insns.h: New file.
1203         * spu.h: New file.
1204
1205 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
1206
1207         * ppc.h (PPC_OPCODE_CELL): Define.
1208
1209 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
1210
1211         * i386.h :  Modify opcode to support for the change in POPCNT opcode
1212         in amdfam10 architecture.
1213
1214 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
1215
1216         * i386.h: Replace CpuMNI with CpuSSSE3.
1217
1218 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
1219             Joseph Myers  <joseph@codesourcery.com>
1220             Ian Lance Taylor  <ian@wasabisystems.com>
1221             Ben Elliston  <bje@wasabisystems.com>
1222
1223         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1224
1225 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
1226
1227         * score-datadep.h: New file.
1228         * score-inst.h: New file.
1229
1230 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
1231
1232         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1233         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1234         movdq2q and movq2dq.
1235
1236 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
1237            Michael Meissner             <michael.meissner@amd.com>
1238
1239         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1240
1241 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
1242
1243         * i386.h (i386_optab): Add "nop" with memory reference.
1244
1245 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
1246
1247         * i386.h (i386_optab): Update comment for 64bit NOP.
1248
1249 2006-06-06  Ben Elliston  <bje@au.ibm.com>
1250             Anton Blanchard  <anton@samba.org>
1251
1252         * ppc.h (PPC_OPCODE_POWER6): Define.
1253         Adjust whitespace.
1254
1255 2006-06-05  Thiemo Seufer  <ths@mips.com>
1256
1257         * mips.h: Improve description of MT flags.
1258
1259 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
1260
1261         * m68k.h (mcf_mask): Define.
1262
1263 2006-05-05  Thiemo Seufer  <ths@mips.com>
1264             David Ung  <davidu@mips.com>
1265
1266         * mips.h (enum): Add macro M_CACHE_AB.
1267
1268 2006-05-04  Thiemo Seufer  <ths@mips.com>
1269             Nigel Stephens  <nigel@mips.com>
1270             David Ung  <davidu@mips.com>
1271
1272         * mips.h: Add INSN_SMARTMIPS define.
1273
1274 2006-04-30  Thiemo Seufer  <ths@mips.com>
1275             David Ung  <davidu@mips.com>
1276
1277         * mips.h: Defines udi bits and masks.  Add description of
1278         characters which may appear in the args field of udi
1279         instructions.
1280
1281 2006-04-26  Thiemo Seufer  <ths@networkno.de>
1282
1283         * mips.h: Improve comments describing the bitfield instruction
1284         fields.
1285
1286 2006-04-26  Julian Brown  <julian@codesourcery.com>
1287
1288         * arm.h (FPU_VFP_EXT_V3): Define constant.
1289         (FPU_NEON_EXT_V1): Likewise.
1290         (FPU_VFP_HARD): Update.
1291         (FPU_VFP_V3): Define macro.
1292         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1293
1294 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
1295
1296         * avr.h (AVR_ISA_PWMx): New.
1297
1298 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
1299
1300         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1301         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1302         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1303         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1304         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1305
1306 2006-03-10  Paul Brook  <paul@codesourcery.com>
1307
1308         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1309
1310 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1311
1312         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1313         first.  Correct mask of bb "B" opcode.
1314
1315 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
1316
1317         * i386.h (i386_optab): Support Intel Merom New Instructions.
1318
1319 2006-02-24  Paul Brook  <paul@codesourcery.com>
1320
1321         * arm.h: Add V7 feature bits.
1322
1323 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
1324
1325         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1326
1327 2006-01-31  Paul Brook  <paul@codesourcery.com>
1328         Richard Earnshaw <rearnsha@arm.com>
1329
1330         * arm.h: Use ARM_CPU_FEATURE.
1331         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1332         (arm_feature_set): Change to a structure.
1333         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1334         ARM_FEATURE): New macros.
1335
1336 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
1337
1338         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1339         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1340         (ADD_PC_INCR_OPCODE): Don't define.
1341
1342 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
1343
1344         PR gas/1874
1345         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1346
1347 2005-11-14  David Ung  <davidu@mips.com>
1348
1349         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1350         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1351         save/restore encoding of the args field.
1352
1353 2005-10-28  Dave Brolley  <brolley@redhat.com>
1354
1355         Contribute the following changes:
1356         2005-02-16  Dave Brolley  <brolley@redhat.com>
1357
1358         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1359         cgen_isa_mask_* to cgen_bitset_*.
1360         * cgen.h: Likewise.
1361
1362         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
1363
1364         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1365         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1366         (CGEN_CPU_TABLE): Make isas a ponter.
1367
1368         2003-09-29  Dave Brolley  <brolley@redhat.com>
1369
1370         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1371         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1372         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1373
1374         2002-12-13  Dave Brolley  <brolley@redhat.com>
1375
1376         * cgen.h (symcat.h): #include it.
1377         (cgen-bitset.h): #include it.
1378         (CGEN_ATTR_VALUE_TYPE): Now a union.
1379         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1380         (CGEN_ATTR_ENTRY): 'value' now unsigned.
1381         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1382         * cgen-bitset.h: New file.
1383
1384 2005-09-30  Catherine Moore  <clm@cm00re.com>
1385
1386         * bfin.h: New file.
1387
1388 2005-10-24  Jan Beulich  <jbeulich@novell.com>
1389
1390         * ia64.h (enum ia64_opnd): Move memory operand out of set of
1391         indirect operands.
1392
1393 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1394
1395         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
1396         Add FLAG_STRICT to pa10 ftest opcode.
1397
1398 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1399
1400         * hppa.h (pa_opcodes): Remove lha entries.
1401
1402 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1403
1404         * hppa.h (FLAG_STRICT): Revise comment.
1405         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
1406         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
1407         entries for "fdc".
1408
1409 2005-09-30  Catherine Moore  <clm@cm00re.com>
1410
1411         * bfin.h: New file.
1412
1413 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1414
1415         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1416
1417 2005-09-06  Chao-ying Fu  <fu@mips.com>
1418
1419         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1420         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1421         define.
1422         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1423         (INSN_ASE_MASK): Update to include INSN_MT.
1424         (INSN_MT): New define for MT ASE.
1425
1426 2005-08-25  Chao-ying Fu  <fu@mips.com>
1427
1428         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1429         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1430         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1431         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1432         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1433         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1434         instructions.
1435         (INSN_DSP): New define for DSP ASE.
1436
1437 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
1438
1439         * a29k.h: Delete.
1440
1441 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
1442
1443         * ppc.h (PPC_OPCODE_E300): Define.
1444
1445 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
1446
1447         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1448
1449 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1450
1451         PR gas/336
1452         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1453         and pitlb.
1454
1455 2005-07-27  Jan Beulich  <jbeulich@novell.com>
1456
1457         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1458         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1459         Add movq-s as 64-bit variants of movd-s.
1460
1461 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1462
1463         * hppa.h: Fix punctuation in comment.
1464
1465         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
1466         implicit space-register addressing.  Set space-register bits on opcodes
1467         using implicit space-register addressing.  Add various missing pa20
1468         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
1469         space-register addressing.  Use "fE" instead of "fe" in various
1470         fstw opcodes.
1471
1472 2005-07-18  Jan Beulich  <jbeulich@novell.com>
1473
1474         * i386.h (i386_optab): Operands of aam and aad are unsigned.
1475
1476 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
1477
1478         * i386.h (i386_optab): Support Intel VMX Instructions.
1479
1480 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1481
1482         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1483
1484 2005-07-05  Jan Beulich  <jbeulich@novell.com>
1485
1486         * i386.h (i386_optab): Add new insns.
1487
1488 2005-07-01  Nick Clifton  <nickc@redhat.com>
1489
1490         * sparc.h: Add typedefs to structure declarations.
1491
1492 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
1493
1494         PR 1013
1495         * i386.h (i386_optab): Update comments for 64bit addressing on
1496         mov. Allow 64bit addressing for mov and movq.
1497
1498 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1499
1500         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1501         respectively, in various floating-point load and store patterns.
1502
1503 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1504
1505         * hppa.h (FLAG_STRICT): Correct comment.
1506         (pa_opcodes): Update load and store entries to allow both PA 1.X and
1507         PA 2.0 mneumonics when equivalent.  Entries with cache control
1508         completers now require PA 1.1.  Adjust whitespace.
1509
1510 2005-05-19  Anton Blanchard  <anton@samba.org>
1511
1512         * ppc.h (PPC_OPCODE_POWER5): Define.
1513
1514 2005-05-10  Nick Clifton  <nickc@redhat.com>
1515
1516         * Update the address and phone number of the FSF organization in
1517         the GPL notices in the following files:
1518         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1519         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1520         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1521         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1522         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1523         tic54x.h, tic80.h, v850.h, vax.h
1524
1525 2005-05-09  Jan Beulich  <jbeulich@novell.com>
1526
1527         * i386.h (i386_optab): Add ht and hnt.
1528
1529 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
1530
1531         * i386.h: Insert hyphens into selected VIA PadLock extensions.
1532         Add xcrypt-ctr.  Provide aliases without hyphens.
1533
1534 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
1535
1536         Moved from ../ChangeLog
1537
1538         2005-04-12  Paul Brook  <paul@codesourcery.com>
1539         * m88k.h: Rename psr macros to avoid conflicts.
1540
1541         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
1542         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1543         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1544         and ARM_ARCH_V6ZKT2.
1545
1546         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
1547         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1548         Remove redundant instruction types.
1549         (struct argument): X_op - new field.
1550         (struct cst4_entry): Remove.
1551         (no_op_insn): Declare.
1552
1553         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
1554         * crx.h (enum argtype): Rename types, remove unused types.
1555
1556         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
1557         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1558         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1559         (enum operand_type): Rearrange operands, edit comments.
1560         replace us<N> with ui<N> for unsigned immediate.
1561         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1562         displacements (respectively).
1563         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1564         (instruction type): Add NO_TYPE_INS.
1565         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1566         (operand_entry): New field - 'flags'.
1567         (operand flags): New.
1568
1569         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
1570         * crx.h (operand_type): Remove redundant types i3, i4,
1571         i5, i8, i12.
1572         Add new unsigned immediate types us3, us4, us5, us16.
1573
1574 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
1575
1576         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1577         adjust them accordingly.
1578
1579 2005-04-01  Jan Beulich  <jbeulich@novell.com>
1580
1581         * i386.h (i386_optab): Add rdtscp.
1582
1583 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
1584
1585         * i386.h (i386_optab): Don't allow the `l' suffix for moving
1586         between memory and segment register. Allow movq for moving between
1587         general-purpose register and segment register.
1588
1589 2005-02-09  Jan Beulich  <jbeulich@novell.com>
1590
1591         PR gas/707
1592         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1593         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1594         fnstsw.
1595
1596 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
1597
1598         * m68k.h (m68008, m68ec030, m68882): Remove.
1599         (m68k_mask): New.
1600         (cpu_m68k, cpu_cf): New.
1601         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1602         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1603
1604 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
1605
1606         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
1607         * cgen.h (enum cgen_parse_operand_type): Add
1608         CGEN_PARSE_OPERAND_SYMBOLIC.
1609
1610 2005-01-21  Fred Fish  <fnf@specifixinc.com>
1611
1612         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1613         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1614         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1615
1616 2005-01-19  Fred Fish  <fnf@specifixinc.com>
1617
1618         * mips.h (struct mips_opcode): Add new pinfo2 member.
1619         (INSN_ALIAS): New define for opcode table entries that are
1620         specific instances of another entry, such as 'move' for an 'or'
1621         with a zero operand.
1622         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1623         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1624
1625 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
1626
1627         * mips.h (CPU_RM9000): Define.
1628         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1629
1630 2004-11-25 Jan Beulich  <jbeulich@novell.com>
1631
1632         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1633         to/from test registers are illegal in 64-bit mode. Add missing
1634         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1635         (previously one had to explicitly encode a rex64 prefix). Re-enable
1636         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1637         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1638
1639 2004-11-23 Jan Beulich  <jbeulich@novell.com>
1640
1641         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1642         available only with SSE2. Change the MMX additions introduced by SSE
1643         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1644         instructions by their now designated identifier (since combining i686
1645         and 3DNow! does not really imply 3DNow!A).
1646
1647 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
1648
1649         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1650         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1651
1652 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
1653             Vineet Sharma      <vineets@noida.hcltech.com>
1654
1655         * maxq.h: New file: Disassembly information for the maxq port.
1656
1657 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
1658
1659         * i386.h (i386_optab): Put back "movzb".
1660
1661 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
1662
1663         * cris.h (enum cris_insn_version_usage): Tweak formatting and
1664         comments.  Remove member cris_ver_sim.  Add members
1665         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1666         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1667         (struct cris_support_reg, struct cris_cond15): New types.
1668         (cris_conds15): Declare.
1669         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1670         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1671         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1672         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1673         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1674         SIZE_FIELD_UNSIGNED.
1675
1676 2004-11-04 Jan Beulich  <jbeulich@novell.com>
1677
1678         * i386.h (sldx_Suf): Remove.
1679         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1680         (q_FP): Define, implying no REX64.
1681         (x_FP, sl_FP): Imply FloatMF.
1682         (i386_optab): Split reg and mem forms of moving from segment registers
1683         so that the memory forms can ignore the 16-/32-bit operand size
1684         distinction. Adjust a few others for Intel mode. Remove *FP uses from
1685         all non-floating-point instructions. Unite 32- and 64-bit forms of
1686         movsx, movzx, and movd. Adjust floating point operations for the above
1687         changes to the *FP macros. Add DefaultSize to floating point control
1688         insns operating on larger memory ranges. Remove left over comments
1689         hinting at certain insns being Intel-syntax ones where the ones
1690         actually meant are already gone.
1691
1692 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
1693
1694         * crx.h: Add COPS_REG_INS - Coprocessor Special register
1695         instruction type.
1696
1697 2004-09-30  Paul Brook  <paul@codesourcery.com>
1698
1699         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1700         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1701
1702 2004-09-11  Theodore A. Roth  <troth@openavr.org>
1703
1704         * avr.h: Add support for
1705         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1706
1707 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
1708
1709         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1710
1711 2004-08-24  Dmitry Diky  <diwil@spec.ru>
1712
1713         * msp430.h (msp430_opc): Add new instructions.
1714         (msp430_rcodes): Declare new instructions.
1715         (msp430_hcodes): Likewise..
1716
1717 2004-08-13  Nick Clifton  <nickc@redhat.com>
1718
1719         PR/301
1720         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1721         processors.
1722
1723 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
1724
1725         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1726
1727 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
1728
1729         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1730
1731 2004-07-21  Jan Beulich  <jbeulich@novell.com>
1732
1733         * i386.h: Adjust instruction descriptions to better match the
1734         specification.
1735
1736 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
1737
1738         * arm.h: Remove all old content.  Replace with architecture defines
1739         from gas/config/tc-arm.c.
1740
1741 2004-07-09  Andreas Schwab  <schwab@suse.de>
1742
1743         * m68k.h: Fix comment.
1744
1745 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
1746
1747         * crx.h: New file.
1748
1749 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
1750
1751         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1752
1753 2004-05-24  Peter Barada  <peter@the-baradas.com>
1754
1755         * m68k.h: Add 'size' to m68k_opcode.
1756
1757 2004-05-05  Peter Barada  <peter@the-baradas.com>
1758
1759         * m68k.h: Switch from ColdFire chip name to core variant.
1760
1761 2004-04-22  Peter Barada  <peter@the-baradas.com>
1762
1763         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
1764         descriptions for new EMAC cases.
1765         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1766         handle Motorola MAC syntax.
1767         Allow disassembly of ColdFire V4e object files.
1768
1769 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
1770
1771         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
1772
1773 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
1774
1775         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1776
1777 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1778
1779         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1780
1781 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1782
1783         * i386.h (i386_optab): Added xstore/xcrypt insns.
1784
1785 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1786
1787         * h8300.h (32bit ldc/stc): Add relaxing support.
1788
1789 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
1790
1791         * h8300.h (BITOP): Pass MEMRELAX flag.
1792
1793 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1794
1795         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1796         except for the H8S.
1797
1798 For older changes see ChangeLog-9103
1799 \f
1800 Copyright (C) 2004-2012 Free Software Foundation, Inc.
1801
1802 Copying and distribution of this file, with or without modification,
1803 are permitted in any medium without royalty provided the copyright
1804 notice and this notice are preserved.
1805
1806 Local Variables:
1807 mode: change-log
1808 left-margin: 8
1809 fill-column: 74
1810 version-control: never
1811 End: