include/opcode/aarch64.h

   1 /* AArch64 assembler/disassembler support.
   2
   3    Copyright (C) 2009-2018 Free Software Foundation, Inc.
   4    Contributed by ARM Ltd.
   5
   6    This file is part of GNU Binutils.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the license, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; see the file COPYING3. If not,
  20    see <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef OPCODE_AARCH64_H
  23 #define OPCODE_AARCH64_H
  24
  25 #include "bfd.h"
  26 #include "bfd_stdint.h"
  27 #include <assert.h>
  28 #include <stdlib.h>
  29
  30 #ifdef __cplusplus
  31 extern "C" {
  32 #endif
  33
  34 /* The offset for pc-relative addressing is currently defined to be 0.  */
  35 #define AARCH64_PCREL_OFFSET            0
  36
  37 typedef uint32_t aarch64_insn;
  38
  39 /* The following bitmasks control CPU features.  */
  40 #define AARCH64_FEATURE_SHA2    0x200000000ULL  /* SHA2 instructions.  */
  41 #define AARCH64_FEATURE_AES     0x800000000ULL  /* AES instructions.  */
  42 #define AARCH64_FEATURE_V8_4    0x000000800ULL  /* ARMv8.4 processors.  */
  43 #define AARCH64_FEATURE_SM4     0x100000000ULL  /* SM3 & SM4 instructions.  */
  44 #define AARCH64_FEATURE_SHA3    0x400000000ULL  /* SHA3 instructions.  */
  45 #define AARCH64_FEATURE_V8      0x00000001      /* All processors.  */
  46 #define AARCH64_FEATURE_V8_2    0x00000020      /* ARMv8.2 processors.  */
  47 #define AARCH64_FEATURE_V8_3    0x00000040      /* ARMv8.3 processors.  */
  48 #define AARCH64_FEATURE_CRYPTO  0x00010000      /* Crypto instructions.  */
  49 #define AARCH64_FEATURE_FP      0x00020000      /* FP instructions.  */
  50 #define AARCH64_FEATURE_SIMD    0x00040000      /* SIMD instructions.  */
  51 #define AARCH64_FEATURE_CRC     0x00080000      /* CRC instructions.  */
  52 #define AARCH64_FEATURE_LSE     0x00100000      /* LSE instructions.  */
  53 #define AARCH64_FEATURE_PAN     0x00200000      /* PAN instructions.  */
  54 #define AARCH64_FEATURE_LOR     0x00400000      /* LOR instructions.  */
  55 #define AARCH64_FEATURE_RDMA    0x00800000      /* v8.1 SIMD instructions.  */
  56 #define AARCH64_FEATURE_V8_1    0x01000000      /* v8.1 features.  */
  57 #define AARCH64_FEATURE_F16     0x02000000      /* v8.2 FP16 instructions.  */
  58 #define AARCH64_FEATURE_RAS     0x04000000      /* RAS Extensions.  */
  59 #define AARCH64_FEATURE_PROFILE 0x08000000      /* Statistical Profiling.  */
  60 #define AARCH64_FEATURE_SVE     0x10000000      /* SVE instructions.  */
  61 #define AARCH64_FEATURE_RCPC    0x20000000      /* RCPC instructions.  */
  62 #define AARCH64_FEATURE_COMPNUM 0x40000000      /* Complex # instructions.  */
  63 #define AARCH64_FEATURE_DOTPROD 0x080000000     /* Dot Product instructions.  */
  64 #define AARCH64_FEATURE_F16_FML 0x1000000000ULL /* v8.2 FP16FML ins.  */
  65
  66 /* Architectures are the sum of the base and extensions.  */
  67 #define AARCH64_ARCH_V8         AARCH64_FEATURE (AARCH64_FEATURE_V8, \
  68                                                  AARCH64_FEATURE_FP  \
  69                                                  | AARCH64_FEATURE_SIMD)
  70 #define AARCH64_ARCH_V8_1       AARCH64_FEATURE (AARCH64_ARCH_V8, \
  71                                                  AARCH64_FEATURE_CRC    \
  72                                                  | AARCH64_FEATURE_V8_1 \
  73                                                  | AARCH64_FEATURE_LSE  \
  74                                                  | AARCH64_FEATURE_PAN  \
  75                                                  | AARCH64_FEATURE_LOR  \
  76                                                  | AARCH64_FEATURE_RDMA)
  77 #define AARCH64_ARCH_V8_2       AARCH64_FEATURE (AARCH64_ARCH_V8_1,     \
  78                                                  AARCH64_FEATURE_V8_2   \
  79                                                  | AARCH64_FEATURE_RAS)
  80 #define AARCH64_ARCH_V8_3       AARCH64_FEATURE (AARCH64_ARCH_V8_2,     \
  81                                                  AARCH64_FEATURE_V8_3   \
  82                                                  | AARCH64_FEATURE_RCPC \
  83                                                  | AARCH64_FEATURE_COMPNUM)
  84 #define AARCH64_ARCH_V8_4       AARCH64_FEATURE (AARCH64_ARCH_V8_3,     \
  85                                                  AARCH64_FEATURE_V8_4   \
  86                                                  | AARCH64_FEATURE_DOTPROD \
  87                                                  | AARCH64_FEATURE_F16_FML)
  88
  89 #define AARCH64_ARCH_NONE       AARCH64_FEATURE (0, 0)
  90 #define AARCH64_ANY             AARCH64_FEATURE (-1, 0) /* Any basic core.  */
  91
  92 /* CPU-specific features.  */
  93 typedef unsigned long long aarch64_feature_set;
  94
  95 #define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT)  \
  96   ((~(CPU) & (FEAT)) == 0)
  97
  98 #define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT)  \
  99   (((CPU) & (FEAT)) != 0)
 100
 101 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT)       \
 102   AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
 103
 104 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2)  \
 105   do                                            \
 106     {                                           \
 107       (TARG) = (F1) | (F2);                     \
 108     }                                           \
 109   while (0)
 110
 111 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2)       \
 112   do                                            \
 113     {                                           \
 114       (TARG) = (F1) &~ (F2);                    \
 115     }                                           \
 116   while (0)
 117
 118 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
 119
 120 enum aarch64_operand_class
 121 {
 122   AARCH64_OPND_CLASS_NIL,
 123   AARCH64_OPND_CLASS_INT_REG,
 124   AARCH64_OPND_CLASS_MODIFIED_REG,
 125   AARCH64_OPND_CLASS_FP_REG,
 126   AARCH64_OPND_CLASS_SIMD_REG,
 127   AARCH64_OPND_CLASS_SIMD_ELEMENT,
 128   AARCH64_OPND_CLASS_SISD_REG,
 129   AARCH64_OPND_CLASS_SIMD_REGLIST,
 130   AARCH64_OPND_CLASS_SVE_REG,
 131   AARCH64_OPND_CLASS_PRED_REG,
 132   AARCH64_OPND_CLASS_ADDRESS,
 133   AARCH64_OPND_CLASS_IMMEDIATE,
 134   AARCH64_OPND_CLASS_SYSTEM,
 135   AARCH64_OPND_CLASS_COND,
 136 };
 137
 138 /* Operand code that helps both parsing and coding.
 139    Keep AARCH64_OPERANDS synced.  */
 140
 141 enum aarch64_opnd
 142 {
 143   AARCH64_OPND_NIL,     /* no operand---MUST BE FIRST!*/
 144
 145   AARCH64_OPND_Rd,      /* Integer register as destination.  */
 146   AARCH64_OPND_Rn,      /* Integer register as source.  */
 147   AARCH64_OPND_Rm,      /* Integer register as source.  */
 148   AARCH64_OPND_Rt,      /* Integer register used in ld/st instructions.  */
 149   AARCH64_OPND_Rt2,     /* Integer register used in ld/st pair instructions.  */
 150   AARCH64_OPND_Rs,      /* Integer register used in ld/st exclusive.  */
 151   AARCH64_OPND_Ra,      /* Integer register used in ddp_3src instructions.  */
 152   AARCH64_OPND_Rt_SYS,  /* Integer register used in system instructions.  */
 153
 154   AARCH64_OPND_Rd_SP,   /* Integer Rd or SP.  */
 155   AARCH64_OPND_Rn_SP,   /* Integer Rn or SP.  */
 156   AARCH64_OPND_Rm_SP,   /* Integer Rm or SP.  */
 157   AARCH64_OPND_PAIRREG, /* Paired register operand.  */
 158   AARCH64_OPND_Rm_EXT,  /* Integer Rm extended.  */
 159   AARCH64_OPND_Rm_SFT,  /* Integer Rm shifted.  */
 160
 161   AARCH64_OPND_Fd,      /* Floating-point Fd.  */
 162   AARCH64_OPND_Fn,      /* Floating-point Fn.  */
 163   AARCH64_OPND_Fm,      /* Floating-point Fm.  */
 164   AARCH64_OPND_Fa,      /* Floating-point Fa.  */
 165   AARCH64_OPND_Ft,      /* Floating-point Ft.  */
 166   AARCH64_OPND_Ft2,     /* Floating-point Ft2.  */
 167
 168   AARCH64_OPND_Sd,      /* AdvSIMD Scalar Sd.  */
 169   AARCH64_OPND_Sn,      /* AdvSIMD Scalar Sn.  */
 170   AARCH64_OPND_Sm,      /* AdvSIMD Scalar Sm.  */
 171
 172   AARCH64_OPND_Va,      /* AdvSIMD Vector Va.  */
 173   AARCH64_OPND_Vd,      /* AdvSIMD Vector Vd.  */
 174   AARCH64_OPND_Vn,      /* AdvSIMD Vector Vn.  */
 175   AARCH64_OPND_Vm,      /* AdvSIMD Vector Vm.  */
 176   AARCH64_OPND_VdD1,    /* AdvSIMD <Vd>.D[1]; for FMOV only.  */
 177   AARCH64_OPND_VnD1,    /* AdvSIMD <Vn>.D[1]; for FMOV only.  */
 178   AARCH64_OPND_Ed,      /* AdvSIMD Vector Element Vd.  */
 179   AARCH64_OPND_En,      /* AdvSIMD Vector Element Vn.  */
 180   AARCH64_OPND_Em,      /* AdvSIMD Vector Element Vm.  */
 181   AARCH64_OPND_LVn,     /* AdvSIMD Vector register list used in e.g. TBL.  */
 182   AARCH64_OPND_LVt,     /* AdvSIMD Vector register list used in ld/st.  */
 183   AARCH64_OPND_LVt_AL,  /* AdvSIMD Vector register list for loading single
 184                            structure to all lanes.  */
 185   AARCH64_OPND_LEt,     /* AdvSIMD Vector Element list.  */
 186
 187   AARCH64_OPND_CRn,     /* Co-processor register in CRn field.  */
 188   AARCH64_OPND_CRm,     /* Co-processor register in CRm field.  */
 189
 190   AARCH64_OPND_IDX,     /* AdvSIMD EXT index operand.  */
 191   AARCH64_OPND_MASK,    /* AdvSIMD EXT index operand.  */
 192   AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left.  */
 193   AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right.  */
 194   AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift.  */
 195   AARCH64_OPND_SIMD_IMM_SFT,    /* AdvSIMD modified immediate with shift.  */
 196   AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate.  */
 197   AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
 198                            (no encoding).  */
 199   AARCH64_OPND_IMM0,    /* Immediate for #0.  */
 200   AARCH64_OPND_FPIMM0,  /* Immediate for #0.0.  */
 201   AARCH64_OPND_FPIMM,   /* Floating-point Immediate.  */
 202   AARCH64_OPND_IMMR,    /* Immediate #<immr> in e.g. BFM.  */
 203   AARCH64_OPND_IMMS,    /* Immediate #<imms> in e.g. BFM.  */
 204   AARCH64_OPND_WIDTH,   /* Immediate #<width> in e.g. BFI.  */
 205   AARCH64_OPND_IMM,     /* Immediate.  */
 206   AARCH64_OPND_IMM_2,   /* Immediate.  */
 207   AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field.  */
 208   AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field.  */
 209   AARCH64_OPND_UIMM4,   /* Unsigned 4-bit immediate in the CRm field.  */
 210   AARCH64_OPND_UIMM7,   /* Unsigned 7-bit immediate in the CRm:op2 fields.  */
 211   AARCH64_OPND_BIT_NUM, /* Immediate.  */
 212   AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions.  */
 213   AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions.  */
 214   AARCH64_OPND_SIMM5,   /* 5-bit signed immediate in the imm5 field.  */
 215   AARCH64_OPND_NZCV,    /* Flag bit specifier giving an alternative value for
 216                            each condition flag.  */
 217
 218   AARCH64_OPND_LIMM,    /* Logical Immediate.  */
 219   AARCH64_OPND_AIMM,    /* Arithmetic immediate.  */
 220   AARCH64_OPND_HALF,    /* #<imm16>{, LSL #<shift>} operand in move wide.  */
 221   AARCH64_OPND_FBITS,   /* FP #<fbits> operand in e.g. SCVTF */
 222   AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias.  */
 223   AARCH64_OPND_IMM_ROT1,        /* Immediate rotate operand for FCMLA.  */
 224   AARCH64_OPND_IMM_ROT2,        /* Immediate rotate operand for indexed FCMLA.  */
 225   AARCH64_OPND_IMM_ROT3,        /* Immediate rotate operand for FCADD.  */
 226
 227   AARCH64_OPND_COND,    /* Standard condition as the last operand.  */
 228   AARCH64_OPND_COND1,   /* Same as the above, but excluding AL and NV.  */
 229
 230   AARCH64_OPND_ADDR_ADRP,       /* Memory address for ADRP */
 231   AARCH64_OPND_ADDR_PCREL14,    /* 14-bit PC-relative address for e.g. TBZ.  */
 232   AARCH64_OPND_ADDR_PCREL19,    /* 19-bit PC-relative address for e.g. LDR.  */
 233   AARCH64_OPND_ADDR_PCREL21,    /* 21-bit PC-relative address for e.g. ADR.  */
 234   AARCH64_OPND_ADDR_PCREL26,    /* 26-bit PC-relative address for e.g. BL.  */
 235
 236   AARCH64_OPND_ADDR_SIMPLE,     /* Address of ld/st exclusive.  */
 237   AARCH64_OPND_ADDR_REGOFF,     /* Address of register offset.  */
 238   AARCH64_OPND_ADDR_SIMM7,      /* Address of signed 7-bit immediate.  */
 239   AARCH64_OPND_ADDR_SIMM9,      /* Address of signed 9-bit immediate.  */
 240   AARCH64_OPND_ADDR_SIMM9_2,    /* Same as the above, but the immediate is
 241                                    negative or unaligned and there is
 242                                    no writeback allowed.  This operand code
 243                                    is only used to support the programmer-
 244                                    friendly feature of using LDR/STR as the
 245                                    the mnemonic name for LDUR/STUR instructions
 246                                    wherever there is no ambiguity.  */
 247   AARCH64_OPND_ADDR_SIMM10,     /* Address of signed 10-bit immediate.  */
 248   AARCH64_OPND_ADDR_UIMM12,     /* Address of unsigned 12-bit immediate.  */
 249   AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures.  */
 250   AARCH64_OPND_ADDR_OFFSET,     /* Address with an optional 9-bit immediate.  */
 251   AARCH64_OPND_SIMD_ADDR_POST,  /* Address of ld/st multiple post-indexed.  */
 252
 253   AARCH64_OPND_SYSREG,          /* System register operand.  */
 254   AARCH64_OPND_PSTATEFIELD,     /* PSTATE field name operand.  */
 255   AARCH64_OPND_SYSREG_AT,       /* System register <at_op> operand.  */
 256   AARCH64_OPND_SYSREG_DC,       /* System register <dc_op> operand.  */
 257   AARCH64_OPND_SYSREG_IC,       /* System register <ic_op> operand.  */
 258   AARCH64_OPND_SYSREG_TLBI,     /* System register <tlbi_op> operand.  */
 259   AARCH64_OPND_BARRIER,         /* Barrier operand.  */
 260   AARCH64_OPND_BARRIER_ISB,     /* Barrier operand for ISB.  */
 261   AARCH64_OPND_PRFOP,           /* Prefetch operation.  */
 262   AARCH64_OPND_BARRIER_PSB,     /* Barrier operand for PSB.  */
 263
 264   AARCH64_OPND_SVE_ADDR_RI_S4x16,   /* SVE [<Xn|SP>, #<simm4>*16].  */
 265   AARCH64_OPND_SVE_ADDR_RI_S4xVL,   /* SVE [<Xn|SP>, #<simm4>, MUL VL].  */
 266   AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL].  */
 267   AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL].  */
 268   AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL].  */
 269   AARCH64_OPND_SVE_ADDR_RI_S6xVL,   /* SVE [<Xn|SP>, #<simm6>, MUL VL].  */
 270   AARCH64_OPND_SVE_ADDR_RI_S9xVL,   /* SVE [<Xn|SP>, #<simm9>, MUL VL].  */
 271   AARCH64_OPND_SVE_ADDR_RI_U6,      /* SVE [<Xn|SP>, #<uimm6>].  */
 272   AARCH64_OPND_SVE_ADDR_RI_U6x2,    /* SVE [<Xn|SP>, #<uimm6>*2].  */
 273   AARCH64_OPND_SVE_ADDR_RI_U6x4,    /* SVE [<Xn|SP>, #<uimm6>*4].  */
 274   AARCH64_OPND_SVE_ADDR_RI_U6x8,    /* SVE [<Xn|SP>, #<uimm6>*8].  */
 275   AARCH64_OPND_SVE_ADDR_RR,         /* SVE [<Xn|SP>, <Xm|XZR>].  */
 276   AARCH64_OPND_SVE_ADDR_RR_LSL1,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1].  */
 277   AARCH64_OPND_SVE_ADDR_RR_LSL2,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2].  */
 278   AARCH64_OPND_SVE_ADDR_RR_LSL3,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3].  */
 279   AARCH64_OPND_SVE_ADDR_RX,         /* SVE [<Xn|SP>, <Xm>].  */
 280   AARCH64_OPND_SVE_ADDR_RX_LSL1,    /* SVE [<Xn|SP>, <Xm>, LSL #1].  */
 281   AARCH64_OPND_SVE_ADDR_RX_LSL2,    /* SVE [<Xn|SP>, <Xm>, LSL #2].  */
 282   AARCH64_OPND_SVE_ADDR_RX_LSL3,    /* SVE [<Xn|SP>, <Xm>, LSL #3].  */
 283   AARCH64_OPND_SVE_ADDR_RZ,         /* SVE [<Xn|SP>, Zm.D].  */
 284   AARCH64_OPND_SVE_ADDR_RZ_LSL1,    /* SVE [<Xn|SP>, Zm.D, LSL #1].  */
 285   AARCH64_OPND_SVE_ADDR_RZ_LSL2,    /* SVE [<Xn|SP>, Zm.D, LSL #2].  */
 286   AARCH64_OPND_SVE_ADDR_RZ_LSL3,    /* SVE [<Xn|SP>, Zm.D, LSL #3].  */
 287   AARCH64_OPND_SVE_ADDR_RZ_XTW_14,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 288                                        Bit 14 controls S/U choice.  */
 289   AARCH64_OPND_SVE_ADDR_RZ_XTW_22,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 290                                        Bit 22 controls S/U choice.  */
 291   AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 292                                        Bit 14 controls S/U choice.  */
 293   AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 294                                        Bit 22 controls S/U choice.  */
 295   AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 296                                        Bit 14 controls S/U choice.  */
 297   AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 298                                        Bit 22 controls S/U choice.  */
 299   AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 300                                        Bit 14 controls S/U choice.  */
 301   AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 302                                        Bit 22 controls S/U choice.  */
 303   AARCH64_OPND_SVE_ADDR_ZI_U5,      /* SVE [Zn.<T>, #<uimm5>].  */
 304   AARCH64_OPND_SVE_ADDR_ZI_U5x2,    /* SVE [Zn.<T>, #<uimm5>*2].  */
 305   AARCH64_OPND_SVE_ADDR_ZI_U5x4,    /* SVE [Zn.<T>, #<uimm5>*4].  */
 306   AARCH64_OPND_SVE_ADDR_ZI_U5x8,    /* SVE [Zn.<T>, #<uimm5>*8].  */
 307   AARCH64_OPND_SVE_ADDR_ZZ_LSL,     /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>].  */
 308   AARCH64_OPND_SVE_ADDR_ZZ_SXTW,    /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>].  */
 309   AARCH64_OPND_SVE_ADDR_ZZ_UXTW,    /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>].  */
 310   AARCH64_OPND_SVE_AIMM,        /* SVE unsigned arithmetic immediate.  */
 311   AARCH64_OPND_SVE_ASIMM,       /* SVE signed arithmetic immediate.  */
 312   AARCH64_OPND_SVE_FPIMM8,      /* SVE 8-bit floating-point immediate.  */
 313   AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0.  */
 314   AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0.  */
 315   AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0.  */
 316   AARCH64_OPND_SVE_IMM_ROT1,    /* SVE 1-bit rotate operand (90 or 270).  */
 317   AARCH64_OPND_SVE_IMM_ROT2,    /* SVE 2-bit rotate operand (N*90).  */
 318   AARCH64_OPND_SVE_INV_LIMM,    /* SVE inverted logical immediate.  */
 319   AARCH64_OPND_SVE_LIMM,        /* SVE logical immediate.  */
 320   AARCH64_OPND_SVE_LIMM_MOV,    /* SVE logical immediate for MOV.  */
 321   AARCH64_OPND_SVE_PATTERN,     /* SVE vector pattern enumeration.  */
 322   AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor.  */
 323   AARCH64_OPND_SVE_PRFOP,       /* SVE prefetch operation.  */
 324   AARCH64_OPND_SVE_Pd,          /* SVE p0-p15 in Pd.  */
 325   AARCH64_OPND_SVE_Pg3,         /* SVE p0-p7 in Pg.  */
 326   AARCH64_OPND_SVE_Pg4_5,       /* SVE p0-p15 in Pg, bits [8,5].  */
 327   AARCH64_OPND_SVE_Pg4_10,      /* SVE p0-p15 in Pg, bits [13,10].  */
 328   AARCH64_OPND_SVE_Pg4_16,      /* SVE p0-p15 in Pg, bits [19,16].  */
 329   AARCH64_OPND_SVE_Pm,          /* SVE p0-p15 in Pm.  */
 330   AARCH64_OPND_SVE_Pn,          /* SVE p0-p15 in Pn.  */
 331   AARCH64_OPND_SVE_Pt,          /* SVE p0-p15 in Pt.  */
 332   AARCH64_OPND_SVE_Rm,          /* Integer Rm or ZR, alt. SVE position.  */
 333   AARCH64_OPND_SVE_Rn_SP,       /* Integer Rn or SP, alt. SVE position.  */
 334   AARCH64_OPND_SVE_SHLIMM_PRED,   /* SVE shift left amount (predicated).  */
 335   AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated).  */
 336   AARCH64_OPND_SVE_SHRIMM_PRED,   /* SVE shift right amount (predicated).  */
 337   AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated).  */
 338   AARCH64_OPND_SVE_SIMM5,       /* SVE signed 5-bit immediate.  */
 339   AARCH64_OPND_SVE_SIMM5B,      /* SVE secondary signed 5-bit immediate.  */
 340   AARCH64_OPND_SVE_SIMM6,       /* SVE signed 6-bit immediate.  */
 341   AARCH64_OPND_SVE_SIMM8,       /* SVE signed 8-bit immediate.  */
 342   AARCH64_OPND_SVE_UIMM3,       /* SVE unsigned 3-bit immediate.  */
 343   AARCH64_OPND_SVE_UIMM7,       /* SVE unsigned 7-bit immediate.  */
 344   AARCH64_OPND_SVE_UIMM8,       /* SVE unsigned 8-bit immediate.  */
 345   AARCH64_OPND_SVE_UIMM8_53,    /* SVE split unsigned 8-bit immediate.  */
 346   AARCH64_OPND_SVE_VZn,         /* Scalar SIMD&FP register in Zn field.  */
 347   AARCH64_OPND_SVE_Vd,          /* Scalar SIMD&FP register in Vd.  */
 348   AARCH64_OPND_SVE_Vm,          /* Scalar SIMD&FP register in Vm.  */
 349   AARCH64_OPND_SVE_Vn,          /* Scalar SIMD&FP register in Vn.  */
 350   AARCH64_OPND_SVE_Za_5,        /* SVE vector register in Za, bits [9,5].  */
 351   AARCH64_OPND_SVE_Za_16,       /* SVE vector register in Za, bits [20,16].  */
 352   AARCH64_OPND_SVE_Zd,          /* SVE vector register in Zd.  */
 353   AARCH64_OPND_SVE_Zm_5,        /* SVE vector register in Zm, bits [9,5].  */
 354   AARCH64_OPND_SVE_Zm_16,       /* SVE vector register in Zm, bits [20,16].  */
 355   AARCH64_OPND_SVE_Zm3_INDEX,   /* z0-z7[0-3] in Zm, bits [20,16].  */
 356   AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22.  */
 357   AARCH64_OPND_SVE_Zm4_INDEX,   /* z0-z15[0-1] in Zm, bits [20,16].  */
 358   AARCH64_OPND_SVE_Zn,          /* SVE vector register in Zn.  */
 359   AARCH64_OPND_SVE_Zn_INDEX,    /* Indexed SVE vector register, for DUP.  */
 360   AARCH64_OPND_SVE_ZnxN,        /* SVE vector register list in Zn.  */
 361   AARCH64_OPND_SVE_Zt,          /* SVE vector register in Zt.  */
 362   AARCH64_OPND_SVE_ZtxN,        /* SVE vector register list in Zt.  */
 363   AARCH64_OPND_SM3_IMM2,        /* SM3 encodes lane in bits [13, 14].  */
 364 };
 365
 366 /* Qualifier constrains an operand.  It either specifies a variant of an
 367    operand type or limits values available to an operand type.
 368
 369    N.B. Order is important; keep aarch64_opnd_qualifiers synced.  */
 370
 371 enum aarch64_opnd_qualifier
 372 {
 373   /* Indicating no further qualification on an operand.  */
 374   AARCH64_OPND_QLF_NIL,
 375
 376   /* Qualifying an operand which is a general purpose (integer) register;
 377      indicating the operand data size or a specific register.  */
 378   AARCH64_OPND_QLF_W,   /* Wn, WZR or WSP.  */
 379   AARCH64_OPND_QLF_X,   /* Xn, XZR or XSP.  */
 380   AARCH64_OPND_QLF_WSP, /* WSP.  */
 381   AARCH64_OPND_QLF_SP,  /* SP.  */
 382
 383   /* Qualifying an operand which is a floating-point register, a SIMD
 384      vector element or a SIMD vector element list; indicating operand data
 385      size or the size of each SIMD vector element in the case of a SIMD
 386      vector element list.
 387      These qualifiers are also used to qualify an address operand to
 388      indicate the size of data element a load/store instruction is
 389      accessing.
 390      They are also used for the immediate shift operand in e.g. SSHR.  Such
 391      a use is only for the ease of operand encoding/decoding and qualifier
 392      sequence matching; such a use should not be applied widely; use the value
 393      constraint qualifiers for immediate operands wherever possible.  */
 394   AARCH64_OPND_QLF_S_B,
 395   AARCH64_OPND_QLF_S_H,
 396   AARCH64_OPND_QLF_S_S,
 397   AARCH64_OPND_QLF_S_D,
 398   AARCH64_OPND_QLF_S_Q,
 399   /* This type qualifier has a special meaning in that it means that 4 x 1 byte
 400      are selected by the instruction.  Other than that it has no difference
 401      with AARCH64_OPND_QLF_S_B in encoding.  It is here purely for syntactical
 402      reasons and is an exception from normal AArch64 disassembly scheme.  */
 403   AARCH64_OPND_QLF_S_4B,
 404
 405   /* Qualifying an operand which is a SIMD vector register or a SIMD vector
 406      register list; indicating register shape.
 407      They are also used for the immediate shift operand in e.g. SSHR.  Such
 408      a use is only for the ease of operand encoding/decoding and qualifier
 409      sequence matching; such a use should not be applied widely; use the value
 410      constraint qualifiers for immediate operands wherever possible.  */
 411   AARCH64_OPND_QLF_V_4B,
 412   AARCH64_OPND_QLF_V_8B,
 413   AARCH64_OPND_QLF_V_16B,
 414   AARCH64_OPND_QLF_V_2H,
 415   AARCH64_OPND_QLF_V_4H,
 416   AARCH64_OPND_QLF_V_8H,
 417   AARCH64_OPND_QLF_V_2S,
 418   AARCH64_OPND_QLF_V_4S,
 419   AARCH64_OPND_QLF_V_1D,
 420   AARCH64_OPND_QLF_V_2D,
 421   AARCH64_OPND_QLF_V_1Q,
 422
 423   AARCH64_OPND_QLF_P_Z,
 424   AARCH64_OPND_QLF_P_M,
 425
 426   /* Constraint on value.  */
 427   AARCH64_OPND_QLF_CR,          /* CRn, CRm. */
 428   AARCH64_OPND_QLF_imm_0_7,
 429   AARCH64_OPND_QLF_imm_0_15,
 430   AARCH64_OPND_QLF_imm_0_31,
 431   AARCH64_OPND_QLF_imm_0_63,
 432   AARCH64_OPND_QLF_imm_1_32,
 433   AARCH64_OPND_QLF_imm_1_64,
 434
 435   /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
 436      or shift-ones.  */
 437   AARCH64_OPND_QLF_LSL,
 438   AARCH64_OPND_QLF_MSL,
 439
 440   /* Special qualifier helping retrieve qualifier information during the
 441      decoding time (currently not in use).  */
 442   AARCH64_OPND_QLF_RETRIEVE,
 443 };
 444 \f
 445 /* Instruction class.  */
 446
 447 enum aarch64_insn_class
 448 {
 449   addsub_carry,
 450   addsub_ext,
 451   addsub_imm,
 452   addsub_shift,
 453   asimdall,
 454   asimddiff,
 455   asimdelem,
 456   asimdext,
 457   asimdimm,
 458   asimdins,
 459   asimdmisc,
 460   asimdperm,
 461   asimdsame,
 462   asimdshf,
 463   asimdtbl,
 464   asisddiff,
 465   asisdelem,
 466   asisdlse,
 467   asisdlsep,
 468   asisdlso,
 469   asisdlsop,
 470   asisdmisc,
 471   asisdone,
 472   asisdpair,
 473   asisdsame,
 474   asisdshf,
 475   bitfield,
 476   branch_imm,
 477   branch_reg,
 478   compbranch,
 479   condbranch,
 480   condcmp_imm,
 481   condcmp_reg,
 482   condsel,
 483   cryptoaes,
 484   cryptosha2,
 485   cryptosha3,
 486   dp_1src,
 487   dp_2src,
 488   dp_3src,
 489   exception,
 490   extract,
 491   float2fix,
 492   float2int,
 493   floatccmp,
 494   floatcmp,
 495   floatdp1,
 496   floatdp2,
 497   floatdp3,
 498   floatimm,
 499   floatsel,
 500   ldst_immpost,
 501   ldst_immpre,
 502   ldst_imm9,    /* immpost or immpre */
 503   ldst_imm10,   /* LDRAA/LDRAB */
 504   ldst_pos,
 505   ldst_regoff,
 506   ldst_unpriv,
 507   ldst_unscaled,
 508   ldstexcl,
 509   ldstnapair_offs,
 510   ldstpair_off,
 511   ldstpair_indexed,
 512   loadlit,
 513   log_imm,
 514   log_shift,
 515   lse_atomic,
 516   movewide,
 517   pcreladdr,
 518   ic_system,
 519   sve_cpy,
 520   sve_index,
 521   sve_limm,
 522   sve_misc,
 523   sve_movprfx,
 524   sve_pred_zm,
 525   sve_shift_pred,
 526   sve_shift_unpred,
 527   sve_size_bhs,
 528   sve_size_bhsd,
 529   sve_size_hsd,
 530   sve_size_sd,
 531   testbranch,
 532   cryptosm3,
 533   cryptosm4,
 534   dotproduct,
 535 };
 536
 537 /* Opcode enumerators.  */
 538
 539 enum aarch64_op
 540 {
 541   OP_NIL,
 542   OP_STRB_POS,
 543   OP_LDRB_POS,
 544   OP_LDRSB_POS,
 545   OP_STRH_POS,
 546   OP_LDRH_POS,
 547   OP_LDRSH_POS,
 548   OP_STR_POS,
 549   OP_LDR_POS,
 550   OP_STRF_POS,
 551   OP_LDRF_POS,
 552   OP_LDRSW_POS,
 553   OP_PRFM_POS,
 554
 555   OP_STURB,
 556   OP_LDURB,
 557   OP_LDURSB,
 558   OP_STURH,
 559   OP_LDURH,
 560   OP_LDURSH,
 561   OP_STUR,
 562   OP_LDUR,
 563   OP_STURV,
 564   OP_LDURV,
 565   OP_LDURSW,
 566   OP_PRFUM,
 567
 568   OP_LDR_LIT,
 569   OP_LDRV_LIT,
 570   OP_LDRSW_LIT,
 571   OP_PRFM_LIT,
 572
 573   OP_ADD,
 574   OP_B,
 575   OP_BL,
 576
 577   OP_MOVN,
 578   OP_MOVZ,
 579   OP_MOVK,
 580
 581   OP_MOV_IMM_LOG,       /* MOV alias for moving bitmask immediate.  */
 582   OP_MOV_IMM_WIDE,      /* MOV alias for moving wide immediate.  */
 583   OP_MOV_IMM_WIDEN,     /* MOV alias for moving wide immediate (negated).  */
 584
 585   OP_MOV_V,             /* MOV alias for moving vector register.  */
 586
 587   OP_ASR_IMM,
 588   OP_LSR_IMM,
 589   OP_LSL_IMM,
 590
 591   OP_BIC,
 592
 593   OP_UBFX,
 594   OP_BFXIL,
 595   OP_SBFX,
 596   OP_SBFIZ,
 597   OP_BFI,
 598   OP_BFC,               /* ARMv8.2.  */
 599   OP_UBFIZ,
 600   OP_UXTB,
 601   OP_UXTH,
 602   OP_UXTW,
 603
 604   OP_CINC,
 605   OP_CINV,
 606   OP_CNEG,
 607   OP_CSET,
 608   OP_CSETM,
 609
 610   OP_FCVT,
 611   OP_FCVTN,
 612   OP_FCVTN2,
 613   OP_FCVTL,
 614   OP_FCVTL2,
 615   OP_FCVTXN_S,          /* Scalar version.  */
 616
 617   OP_ROR_IMM,
 618
 619   OP_SXTL,
 620   OP_SXTL2,
 621   OP_UXTL,
 622   OP_UXTL2,
 623
 624   OP_MOV_P_P,
 625   OP_MOV_Z_P_Z,
 626   OP_MOV_Z_V,
 627   OP_MOV_Z_Z,
 628   OP_MOV_Z_Zi,
 629   OP_MOVM_P_P_P,
 630   OP_MOVS_P_P,
 631   OP_MOVZS_P_P_P,
 632   OP_MOVZ_P_P_P,
 633   OP_NOTS_P_P_P_Z,
 634   OP_NOT_P_P_P_Z,
 635
 636   OP_FCMLA_ELEM,        /* ARMv8.3, indexed element version.  */
 637
 638   OP_TOTAL_NUM,         /* Pseudo.  */
 639 };
 640
 641 /* Maximum number of operands an instruction can have.  */
 642 #define AARCH64_MAX_OPND_NUM 6
 643 /* Maximum number of qualifier sequences an instruction can have.  */
 644 #define AARCH64_MAX_QLF_SEQ_NUM 10
 645 /* Operand qualifier typedef; optimized for the size.  */
 646 typedef unsigned char aarch64_opnd_qualifier_t;
 647 /* Operand qualifier sequence typedef.  */
 648 typedef aarch64_opnd_qualifier_t        \
 649           aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
 650
 651 /* FIXME: improve the efficiency.  */
 652 static inline bfd_boolean
 653 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
 654 {
 655   int i;
 656   for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
 657     if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
 658       return FALSE;
 659   return TRUE;
 660 }
 661
 662 /* This structure holds information for a particular opcode.  */
 663
 664 struct aarch64_opcode
 665 {
 666   /* The name of the mnemonic.  */
 667   const char *name;
 668
 669   /* The opcode itself.  Those bits which will be filled in with
 670      operands are zeroes.  */
 671   aarch64_insn opcode;
 672
 673   /* The opcode mask.  This is used by the disassembler.  This is a
 674      mask containing ones indicating those bits which must match the
 675      opcode field, and zeroes indicating those bits which need not
 676      match (and are presumably filled in by operands).  */
 677   aarch64_insn mask;
 678
 679   /* Instruction class.  */
 680   enum aarch64_insn_class iclass;
 681
 682   /* Enumerator identifier.  */
 683   enum aarch64_op op;
 684
 685   /* Which architecture variant provides this instruction.  */
 686   const aarch64_feature_set *avariant;
 687
 688   /* An array of operand codes.  Each code is an index into the
 689      operand table.  They appear in the order which the operands must
 690      appear in assembly code, and are terminated by a zero.  */
 691   enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
 692
 693   /* A list of operand qualifier code sequence.  Each operand qualifier
 694      code qualifies the corresponding operand code.  Each operand
 695      qualifier sequence specifies a valid opcode variant and related
 696      constraint on operands.  */
 697   aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
 698
 699   /* Flags providing information about this instruction */
 700   uint32_t flags;
 701
 702   /* If nonzero, this operand and operand 0 are both registers and
 703      are required to have the same register number.  */
 704   unsigned char tied_operand;
 705
 706   /* If non-NULL, a function to verify that a given instruction is valid.  */
 707   bfd_boolean (* verifier) (const struct aarch64_opcode *, const aarch64_insn);
 708 };
 709
 710 typedef struct aarch64_opcode aarch64_opcode;
 711
 712 /* Table describing all the AArch64 opcodes.  */
 713 extern aarch64_opcode aarch64_opcode_table[];
 714
 715 /* Opcode flags.  */
 716 #define F_ALIAS (1 << 0)
 717 #define F_HAS_ALIAS (1 << 1)
 718 /* Disassembly preference priority 1-3 (the larger the higher).  If nothing
 719    is specified, it is the priority 0 by default, i.e. the lowest priority.  */
 720 #define F_P1 (1 << 2)
 721 #define F_P2 (2 << 2)
 722 #define F_P3 (3 << 2)
 723 /* Flag an instruction that is truly conditional executed, e.g. b.cond.  */
 724 #define F_COND (1 << 4)
 725 /* Instruction has the field of 'sf'.  */
 726 #define F_SF (1 << 5)
 727 /* Instruction has the field of 'size:Q'.  */
 728 #define F_SIZEQ (1 << 6)
 729 /* Floating-point instruction has the field of 'type'.  */
 730 #define F_FPTYPE (1 << 7)
 731 /* AdvSIMD scalar instruction has the field of 'size'.  */
 732 #define F_SSIZE (1 << 8)
 733 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q".  */
 734 #define F_T (1 << 9)
 735 /* Size of GPR operand in AdvSIMD instructions encoded in Q.  */
 736 #define F_GPRSIZE_IN_Q (1 << 10)
 737 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22.  */
 738 #define F_LDS_SIZE (1 << 11)
 739 /* Optional operand; assume maximum of 1 operand can be optional.  */
 740 #define F_OPD0_OPT (1 << 12)
 741 #define F_OPD1_OPT (2 << 12)
 742 #define F_OPD2_OPT (3 << 12)
 743 #define F_OPD3_OPT (4 << 12)
 744 #define F_OPD4_OPT (5 << 12)
 745 /* Default value for the optional operand when omitted from the assembly.  */
 746 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
 747 /* Instruction that is an alias of another instruction needs to be
 748    encoded/decoded by converting it to/from the real form, followed by
 749    the encoding/decoding according to the rules of the real opcode.
 750    This compares to the direct coding using the alias's information.
 751    N.B. this flag requires F_ALIAS to be used together.  */
 752 #define F_CONV (1 << 20)
 753 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
 754    friendly pseudo instruction available only in the assembly code (thus will
 755    not show up in the disassembly).  */
 756 #define F_PSEUDO (1 << 21)
 757 /* Instruction has miscellaneous encoding/decoding rules.  */
 758 #define F_MISC (1 << 22)
 759 /* Instruction has the field of 'N'; used in conjunction with F_SF.  */
 760 #define F_N (1 << 23)
 761 /* Opcode dependent field.  */
 762 #define F_OD(X) (((X) & 0x7) << 24)
 763 /* Instruction has the field of 'sz'.  */
 764 #define F_LSE_SZ (1 << 27)
 765 /* Require an exact qualifier match, even for NIL qualifiers.  */
 766 #define F_STRICT (1ULL << 28)
 767 /* Next bit is 29.  */
 768
 769 static inline bfd_boolean
 770 alias_opcode_p (const aarch64_opcode *opcode)
 771 {
 772   return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
 773 }
 774
 775 static inline bfd_boolean
 776 opcode_has_alias (const aarch64_opcode *opcode)
 777 {
 778   return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
 779 }
 780
 781 /* Priority for disassembling preference.  */
 782 static inline int
 783 opcode_priority (const aarch64_opcode *opcode)
 784 {
 785   return (opcode->flags >> 2) & 0x3;
 786 }
 787
 788 static inline bfd_boolean
 789 pseudo_opcode_p (const aarch64_opcode *opcode)
 790 {
 791   return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
 792 }
 793
 794 static inline bfd_boolean
 795 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
 796 {
 797   return (((opcode->flags >> 12) & 0x7) == idx + 1)
 798     ? TRUE : FALSE;
 799 }
 800
 801 static inline aarch64_insn
 802 get_optional_operand_default_value (const aarch64_opcode *opcode)
 803 {
 804   return (opcode->flags >> 15) & 0x1f;
 805 }
 806
 807 static inline unsigned int
 808 get_opcode_dependent_value (const aarch64_opcode *opcode)
 809 {
 810   return (opcode->flags >> 24) & 0x7;
 811 }
 812
 813 static inline bfd_boolean
 814 opcode_has_special_coder (const aarch64_opcode *opcode)
 815 {
 816   return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
 817           | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
 818     : FALSE;
 819 }
 820 \f
 821 struct aarch64_name_value_pair
 822 {
 823   const char *  name;
 824   aarch64_insn  value;
 825 };
 826
 827 extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
 828 extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
 829 extern const struct aarch64_name_value_pair aarch64_prfops [32];
 830 extern const struct aarch64_name_value_pair aarch64_hint_options [];
 831
 832 typedef struct
 833 {
 834   const char *  name;
 835   aarch64_insn  value;
 836   uint32_t      flags;
 837 } aarch64_sys_reg;
 838
 839 extern const aarch64_sys_reg aarch64_sys_regs [];
 840 extern const aarch64_sys_reg aarch64_pstatefields [];
 841 extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
 842 extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
 843                                                 const aarch64_sys_reg *);
 844 extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
 845                                                     const aarch64_sys_reg *);
 846
 847 typedef struct
 848 {
 849   const char *name;
 850   uint32_t value;
 851   uint32_t flags ;
 852 } aarch64_sys_ins_reg;
 853
 854 extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
 855 extern bfd_boolean
 856 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
 857                                  const aarch64_sys_ins_reg *);
 858
 859 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
 860 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
 861 extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
 862 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
 863
 864 /* Shift/extending operator kinds.
 865    N.B. order is important; keep aarch64_operand_modifiers synced.  */
 866 enum aarch64_modifier_kind
 867 {
 868   AARCH64_MOD_NONE,
 869   AARCH64_MOD_MSL,
 870   AARCH64_MOD_ROR,
 871   AARCH64_MOD_ASR,
 872   AARCH64_MOD_LSR,
 873   AARCH64_MOD_LSL,
 874   AARCH64_MOD_UXTB,
 875   AARCH64_MOD_UXTH,
 876   AARCH64_MOD_UXTW,
 877   AARCH64_MOD_UXTX,
 878   AARCH64_MOD_SXTB,
 879   AARCH64_MOD_SXTH,
 880   AARCH64_MOD_SXTW,
 881   AARCH64_MOD_SXTX,
 882   AARCH64_MOD_MUL,
 883   AARCH64_MOD_MUL_VL,
 884 };
 885
 886 bfd_boolean
 887 aarch64_extend_operator_p (enum aarch64_modifier_kind);
 888
 889 enum aarch64_modifier_kind
 890 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
 891 /* Condition.  */
 892
 893 typedef struct
 894 {
 895   /* A list of names with the first one as the disassembly preference;
 896      terminated by NULL if fewer than 3.  */
 897   const char *names[4];
 898   aarch64_insn value;
 899 } aarch64_cond;
 900
 901 extern const aarch64_cond aarch64_conds[16];
 902
 903 const aarch64_cond* get_cond_from_value (aarch64_insn value);
 904 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
 905 \f
 906 /* Structure representing an operand.  */
 907
 908 struct aarch64_opnd_info
 909 {
 910   enum aarch64_opnd type;
 911   aarch64_opnd_qualifier_t qualifier;
 912   int idx;
 913
 914   union
 915     {
 916       struct
 917         {
 918           unsigned regno;
 919         } reg;
 920       struct
 921         {
 922           unsigned int regno;
 923           int64_t index;
 924         } reglane;
 925       /* e.g. LVn.  */
 926       struct
 927         {
 928           unsigned first_regno : 5;
 929           unsigned num_regs : 3;
 930           /* 1 if it is a list of reg element.  */
 931           unsigned has_index : 1;
 932           /* Lane index; valid only when has_index is 1.  */
 933           int64_t index;
 934         } reglist;
 935       /* e.g. immediate or pc relative address offset.  */
 936       struct
 937         {
 938           int64_t value;
 939           unsigned is_fp : 1;
 940         } imm;
 941       /* e.g. address in STR (register offset).  */
 942       struct
 943         {
 944           unsigned base_regno;
 945           struct
 946             {
 947               union
 948                 {
 949                   int imm;
 950                   unsigned regno;
 951                 };
 952               unsigned is_reg;
 953             } offset;
 954           unsigned pcrel : 1;           /* PC-relative.  */
 955           unsigned writeback : 1;
 956           unsigned preind : 1;          /* Pre-indexed.  */
 957           unsigned postind : 1;         /* Post-indexed.  */
 958         } addr;
 959       const aarch64_cond *cond;
 960       /* The encoding of the system register.  */
 961       aarch64_insn sysreg;
 962       /* The encoding of the PSTATE field.  */
 963       aarch64_insn pstatefield;
 964       const aarch64_sys_ins_reg *sysins_op;
 965       const struct aarch64_name_value_pair *barrier;
 966       const struct aarch64_name_value_pair *hint_option;
 967       const struct aarch64_name_value_pair *prfop;
 968     };
 969
 970   /* Operand shifter; in use when the operand is a register offset address,
 971      add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}.  */
 972   struct
 973     {
 974       enum aarch64_modifier_kind kind;
 975       unsigned operator_present: 1;     /* Only valid during encoding.  */
 976       /* Value of the 'S' field in ld/st reg offset; used only in decoding.  */
 977       unsigned amount_present: 1;
 978       int64_t amount;
 979     } shifter;
 980
 981   unsigned skip:1;      /* Operand is not completed if there is a fixup needed
 982                            to be done on it.  In some (but not all) of these
 983                            cases, we need to tell libopcodes to skip the
 984                            constraint checking and the encoding for this
 985                            operand, so that the libopcodes can pick up the
 986                            right opcode before the operand is fixed-up.  This
 987                            flag should only be used during the
 988                            assembling/encoding.  */
 989   unsigned present:1;   /* Whether this operand is present in the assembly
 990                            line; not used during the disassembly.  */
 991 };
 992
 993 typedef struct aarch64_opnd_info aarch64_opnd_info;
 994
 995 /* Structure representing an instruction.
 996
 997    It is used during both the assembling and disassembling.  The assembler
 998    fills an aarch64_inst after a successful parsing and then passes it to the
 999    encoding routine to do the encoding.  During the disassembling, the
1000    disassembler calls the decoding routine to decode a binary instruction; on a
1001    successful return, such a structure will be filled with information of the
1002    instruction; then the disassembler uses the information to print out the
1003    instruction.  */
1004
1005 struct aarch64_inst
1006 {
1007   /* The value of the binary instruction.  */
1008   aarch64_insn value;
1009
1010   /* Corresponding opcode entry.  */
1011   const aarch64_opcode *opcode;
1012
1013   /* Condition for a truly conditional-executed instrutions, e.g. b.cond.  */
1014   const aarch64_cond *cond;
1015
1016   /* Operands information.  */
1017   aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
1018 };
1019
1020 typedef struct aarch64_inst aarch64_inst;
1021 \f
1022 /* Diagnosis related declaration and interface.  */
1023
1024 /* Operand error kind enumerators.
1025
1026    AARCH64_OPDE_RECOVERABLE
1027      Less severe error found during the parsing, very possibly because that
1028      GAS has picked up a wrong instruction template for the parsing.
1029
1030    AARCH64_OPDE_SYNTAX_ERROR
1031      General syntax error; it can be either a user error, or simply because
1032      that GAS is trying a wrong instruction template.
1033
1034    AARCH64_OPDE_FATAL_SYNTAX_ERROR
1035      Definitely a user syntax error.
1036
1037    AARCH64_OPDE_INVALID_VARIANT
1038      No syntax error, but the operands are not a valid combination, e.g.
1039      FMOV D0,S0
1040
1041    AARCH64_OPDE_UNTIED_OPERAND
1042      The asm failed to use the same register for a destination operand
1043      and a tied source operand.
1044
1045    AARCH64_OPDE_OUT_OF_RANGE
1046      Error about some immediate value out of a valid range.
1047
1048    AARCH64_OPDE_UNALIGNED
1049      Error about some immediate value not properly aligned (i.e. not being a
1050      multiple times of a certain value).
1051
1052    AARCH64_OPDE_REG_LIST
1053      Error about the register list operand having unexpected number of
1054      registers.
1055
1056    AARCH64_OPDE_OTHER_ERROR
1057      Error of the highest severity and used for any severe issue that does not
1058      fall into any of the above categories.
1059
1060    The enumerators are only interesting to GAS.  They are declared here (in
1061    libopcodes) because that some errors are detected (and then notified to GAS)
1062    by libopcodes (rather than by GAS solely).
1063
1064    The first three errors are only deteced by GAS while the
1065    AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1066    only libopcodes has the information about the valid variants of each
1067    instruction.
1068
1069    The enumerators have an increasing severity.  This is helpful when there are
1070    multiple instruction templates available for a given mnemonic name (e.g.
1071    FMOV); this mechanism will help choose the most suitable template from which
1072    the generated diagnostics can most closely describe the issues, if any.  */
1073
1074 enum aarch64_operand_error_kind
1075 {
1076   AARCH64_OPDE_NIL,
1077   AARCH64_OPDE_RECOVERABLE,
1078   AARCH64_OPDE_SYNTAX_ERROR,
1079   AARCH64_OPDE_FATAL_SYNTAX_ERROR,
1080   AARCH64_OPDE_INVALID_VARIANT,
1081   AARCH64_OPDE_UNTIED_OPERAND,
1082   AARCH64_OPDE_OUT_OF_RANGE,
1083   AARCH64_OPDE_UNALIGNED,
1084   AARCH64_OPDE_REG_LIST,
1085   AARCH64_OPDE_OTHER_ERROR
1086 };
1087
1088 /* N.B. GAS assumes that this structure work well with shallow copy.  */
1089 struct aarch64_operand_error
1090 {
1091   enum aarch64_operand_error_kind kind;
1092   int index;
1093   const char *error;
1094   int data[3];  /* Some data for extra information.  */
1095 };
1096
1097 typedef struct aarch64_operand_error aarch64_operand_error;
1098
1099 /* Encoding entrypoint.  */
1100
1101 extern int
1102 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1103                        aarch64_insn *, aarch64_opnd_qualifier_t *,
1104                        aarch64_operand_error *);
1105
1106 extern const aarch64_opcode *
1107 aarch64_replace_opcode (struct aarch64_inst *,
1108                         const aarch64_opcode *);
1109
1110 /* Given the opcode enumerator OP, return the pointer to the corresponding
1111    opcode entry.  */
1112
1113 extern const aarch64_opcode *
1114 aarch64_get_opcode (enum aarch64_op);
1115
1116 /* Generate the string representation of an operand.  */
1117 extern void
1118 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
1119                        const aarch64_opnd_info *, int, int *, bfd_vma *);
1120
1121 /* Miscellaneous interface.  */
1122
1123 extern int
1124 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1125
1126 extern aarch64_opnd_qualifier_t
1127 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1128                                 const aarch64_opnd_qualifier_t, int);
1129
1130 extern int
1131 aarch64_num_of_operands (const aarch64_opcode *);
1132
1133 extern int
1134 aarch64_stack_pointer_p (const aarch64_opnd_info *);
1135
1136 extern int
1137 aarch64_zero_register_p (const aarch64_opnd_info *);
1138
1139 extern int
1140 aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean);
1141
1142 /* Given an operand qualifier, return the expected data element size
1143    of a qualified operand.  */
1144 extern unsigned char
1145 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1146
1147 extern enum aarch64_operand_class
1148 aarch64_get_operand_class (enum aarch64_opnd);
1149
1150 extern const char *
1151 aarch64_get_operand_name (enum aarch64_opnd);
1152
1153 extern const char *
1154 aarch64_get_operand_desc (enum aarch64_opnd);
1155
1156 extern bfd_boolean
1157 aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1158
1159 #ifdef DEBUG_AARCH64
1160 extern int debug_dump;
1161
1162 extern void
1163 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1164
1165 #define DEBUG_TRACE(M, ...)                                     \
1166   {                                                             \
1167     if (debug_dump)                                             \
1168       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1169   }
1170
1171 #define DEBUG_TRACE_IF(C, M, ...)                               \
1172   {                                                             \
1173     if (debug_dump && (C))                                      \
1174       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1175   }
1176 #else  /* !DEBUG_AARCH64 */
1177 #define DEBUG_TRACE(M, ...) ;
1178 #define DEBUG_TRACE_IF(C, M, ...) ;
1179 #endif /* DEBUG_AARCH64 */
1180
1181 extern const char *const aarch64_sve_pattern_array[32];
1182 extern const char *const aarch64_sve_prfop_array[16];
1183
1184 #ifdef __cplusplus
1185 }
1186 #endif
1187
1188 #endif /* OPCODE_AARCH64_H */