include/opcode/aarch64.h

   1 /* AArch64 assembler/disassembler support.
   2
   3    Copyright (C) 2009-2019 Free Software Foundation, Inc.
   4    Contributed by ARM Ltd.
   5
   6    This file is part of GNU Binutils.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the license, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; see the file COPYING3. If not,
  20    see <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef OPCODE_AARCH64_H
  23 #define OPCODE_AARCH64_H
  24
  25 #include "bfd.h"
  26 #include "bfd_stdint.h"
  27 #include <assert.h>
  28 #include <stdlib.h>
  29
  30 #ifdef __cplusplus
  31 extern "C" {
  32 #endif
  33
  34 /* The offset for pc-relative addressing is currently defined to be 0.  */
  35 #define AARCH64_PCREL_OFFSET            0
  36
  37 typedef uint32_t aarch64_insn;
  38
  39 /* The following bitmasks control CPU features.  */
  40 #define AARCH64_FEATURE_SHA2    0x200000000ULL  /* SHA2 instructions.  */
  41 #define AARCH64_FEATURE_AES     0x800000000ULL  /* AES instructions.  */
  42 #define AARCH64_FEATURE_V8_4    0x000000800ULL  /* ARMv8.4 processors.  */
  43 #define AARCH64_FEATURE_SM4     0x100000000ULL  /* SM3 & SM4 instructions.  */
  44 #define AARCH64_FEATURE_SHA3    0x400000000ULL  /* SHA3 instructions.  */
  45 #define AARCH64_FEATURE_V8      0x00000001      /* All processors.  */
  46 #define AARCH64_FEATURE_V8_2    0x00000020      /* ARMv8.2 processors.  */
  47 #define AARCH64_FEATURE_V8_3    0x00000040      /* ARMv8.3 processors.  */
  48 #define AARCH64_FEATURE_CRYPTO  0x00010000      /* Crypto instructions.  */
  49 #define AARCH64_FEATURE_FP      0x00020000      /* FP instructions.  */
  50 #define AARCH64_FEATURE_SIMD    0x00040000      /* SIMD instructions.  */
  51 #define AARCH64_FEATURE_CRC     0x00080000      /* CRC instructions.  */
  52 #define AARCH64_FEATURE_LSE     0x00100000      /* LSE instructions.  */
  53 #define AARCH64_FEATURE_PAN     0x00200000      /* PAN instructions.  */
  54 #define AARCH64_FEATURE_LOR     0x00400000      /* LOR instructions.  */
  55 #define AARCH64_FEATURE_RDMA    0x00800000      /* v8.1 SIMD instructions.  */
  56 #define AARCH64_FEATURE_V8_1    0x01000000      /* v8.1 features.  */
  57 #define AARCH64_FEATURE_F16     0x02000000      /* v8.2 FP16 instructions.  */
  58 #define AARCH64_FEATURE_RAS     0x04000000      /* RAS Extensions.  */
  59 #define AARCH64_FEATURE_PROFILE 0x08000000      /* Statistical Profiling.  */
  60 #define AARCH64_FEATURE_SVE     0x10000000      /* SVE instructions.  */
  61 #define AARCH64_FEATURE_RCPC    0x20000000      /* RCPC instructions.  */
  62 #define AARCH64_FEATURE_COMPNUM 0x40000000      /* Complex # instructions.  */
  63 #define AARCH64_FEATURE_DOTPROD 0x080000000     /* Dot Product instructions.  */
  64 #define AARCH64_FEATURE_F16_FML 0x1000000000ULL /* v8.2 FP16FML ins.  */
  65 #define AARCH64_FEATURE_V8_5    0x2000000000ULL /* ARMv8.5 processors.  */
  66
  67 /* Flag Manipulation insns.  */
  68 #define AARCH64_FEATURE_FLAGMANIP       0x4000000000ULL
  69 /* FRINT[32,64][Z,X] insns.  */
  70 #define AARCH64_FEATURE_FRINTTS         0x8000000000ULL
  71 /* SB instruction.  */
  72 #define AARCH64_FEATURE_SB              0x10000000000ULL
  73 /* Execution and Data Prediction Restriction instructions.  */
  74 #define AARCH64_FEATURE_PREDRES         0x20000000000ULL
  75 /* DC CVADP.  */
  76 #define AARCH64_FEATURE_CVADP           0x40000000000ULL
  77 /* Random Number instructions.  */
  78 #define AARCH64_FEATURE_RNG             0x80000000000ULL
  79 /* BTI instructions.  */
  80 #define AARCH64_FEATURE_BTI             0x100000000000ULL
  81 /* SCXTNUM_ELx.  */
  82 #define AARCH64_FEATURE_SCXTNUM         0x200000000000ULL
  83 /* ID_PFR2 instructions.  */
  84 #define AARCH64_FEATURE_ID_PFR2         0x400000000000ULL
  85 /* SSBS mechanism enabled.  */
  86 #define AARCH64_FEATURE_SSBS            0x800000000000ULL
  87 /* Memory Tagging Extension.  */
  88 #define AARCH64_FEATURE_MEMTAG          0x1000000000000ULL
  89 /* Transactional Memory Extension.  */
  90 #define AARCH64_FEATURE_TME             0x2000000000000ULL
  91
  92 /* SVE2 instructions.  */
  93 #define AARCH64_FEATURE_SVE2            0x000000010
  94 #define AARCH64_FEATURE_SVE2_AES                0x000000080
  95 #define AARCH64_FEATURE_SVE2_BITPERM    0x000000100
  96 #define AARCH64_FEATURE_SVE2_SM4                0x000000200
  97 #define AARCH64_FEATURE_SVE2_SHA3       0x000000400
  98
  99 /* Architectures are the sum of the base and extensions.  */
 100 #define AARCH64_ARCH_V8         AARCH64_FEATURE (AARCH64_FEATURE_V8, \
 101                                                  AARCH64_FEATURE_FP  \
 102                                                  | AARCH64_FEATURE_SIMD)
 103 #define AARCH64_ARCH_V8_1       AARCH64_FEATURE (AARCH64_ARCH_V8, \
 104                                                  AARCH64_FEATURE_CRC    \
 105                                                  | AARCH64_FEATURE_V8_1 \
 106                                                  | AARCH64_FEATURE_LSE  \
 107                                                  | AARCH64_FEATURE_PAN  \
 108                                                  | AARCH64_FEATURE_LOR  \
 109                                                  | AARCH64_FEATURE_RDMA)
 110 #define AARCH64_ARCH_V8_2       AARCH64_FEATURE (AARCH64_ARCH_V8_1,     \
 111                                                  AARCH64_FEATURE_V8_2   \
 112                                                  | AARCH64_FEATURE_RAS)
 113 #define AARCH64_ARCH_V8_3       AARCH64_FEATURE (AARCH64_ARCH_V8_2,     \
 114                                                  AARCH64_FEATURE_V8_3   \
 115                                                  | AARCH64_FEATURE_RCPC \
 116                                                  | AARCH64_FEATURE_COMPNUM)
 117 #define AARCH64_ARCH_V8_4       AARCH64_FEATURE (AARCH64_ARCH_V8_3,     \
 118                                                  AARCH64_FEATURE_V8_4   \
 119                                                  | AARCH64_FEATURE_DOTPROD \
 120                                                  | AARCH64_FEATURE_F16_FML)
 121 #define AARCH64_ARCH_V8_5       AARCH64_FEATURE (AARCH64_ARCH_V8_4,     \
 122                                                  AARCH64_FEATURE_V8_5   \
 123                                                  | AARCH64_FEATURE_FLAGMANIP \
 124                                                  | AARCH64_FEATURE_FRINTTS \
 125                                                  | AARCH64_FEATURE_SB   \
 126                                                  | AARCH64_FEATURE_PREDRES \
 127                                                  | AARCH64_FEATURE_CVADP \
 128                                                  | AARCH64_FEATURE_BTI  \
 129                                                  | AARCH64_FEATURE_SCXTNUM \
 130                                                  | AARCH64_FEATURE_ID_PFR2 \
 131                                                  | AARCH64_FEATURE_SSBS)
 132
 133
 134 #define AARCH64_ARCH_NONE       AARCH64_FEATURE (0, 0)
 135 #define AARCH64_ANY             AARCH64_FEATURE (-1, 0) /* Any basic core.  */
 136
 137 /* CPU-specific features.  */
 138 typedef unsigned long long aarch64_feature_set;
 139
 140 #define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT)  \
 141   ((~(CPU) & (FEAT)) == 0)
 142
 143 #define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT)  \
 144   (((CPU) & (FEAT)) != 0)
 145
 146 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT)       \
 147   AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
 148
 149 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2)  \
 150   do                                            \
 151     {                                           \
 152       (TARG) = (F1) | (F2);                     \
 153     }                                           \
 154   while (0)
 155
 156 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2)       \
 157   do                                            \
 158     {                                           \
 159       (TARG) = (F1) &~ (F2);                    \
 160     }                                           \
 161   while (0)
 162
 163 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
 164
 165 enum aarch64_operand_class
 166 {
 167   AARCH64_OPND_CLASS_NIL,
 168   AARCH64_OPND_CLASS_INT_REG,
 169   AARCH64_OPND_CLASS_MODIFIED_REG,
 170   AARCH64_OPND_CLASS_FP_REG,
 171   AARCH64_OPND_CLASS_SIMD_REG,
 172   AARCH64_OPND_CLASS_SIMD_ELEMENT,
 173   AARCH64_OPND_CLASS_SISD_REG,
 174   AARCH64_OPND_CLASS_SIMD_REGLIST,
 175   AARCH64_OPND_CLASS_SVE_REG,
 176   AARCH64_OPND_CLASS_PRED_REG,
 177   AARCH64_OPND_CLASS_ADDRESS,
 178   AARCH64_OPND_CLASS_IMMEDIATE,
 179   AARCH64_OPND_CLASS_SYSTEM,
 180   AARCH64_OPND_CLASS_COND,
 181 };
 182
 183 /* Operand code that helps both parsing and coding.
 184    Keep AARCH64_OPERANDS synced.  */
 185
 186 enum aarch64_opnd
 187 {
 188   AARCH64_OPND_NIL,     /* no operand---MUST BE FIRST!*/
 189
 190   AARCH64_OPND_Rd,      /* Integer register as destination.  */
 191   AARCH64_OPND_Rn,      /* Integer register as source.  */
 192   AARCH64_OPND_Rm,      /* Integer register as source.  */
 193   AARCH64_OPND_Rt,      /* Integer register used in ld/st instructions.  */
 194   AARCH64_OPND_Rt2,     /* Integer register used in ld/st pair instructions.  */
 195   AARCH64_OPND_Rt_SP,   /* Integer Rt or SP used in STG instructions.  */
 196   AARCH64_OPND_Rs,      /* Integer register used in ld/st exclusive.  */
 197   AARCH64_OPND_Ra,      /* Integer register used in ddp_3src instructions.  */
 198   AARCH64_OPND_Rt_SYS,  /* Integer register used in system instructions.  */
 199
 200   AARCH64_OPND_Rd_SP,   /* Integer Rd or SP.  */
 201   AARCH64_OPND_Rn_SP,   /* Integer Rn or SP.  */
 202   AARCH64_OPND_Rm_SP,   /* Integer Rm or SP.  */
 203   AARCH64_OPND_PAIRREG, /* Paired register operand.  */
 204   AARCH64_OPND_Rm_EXT,  /* Integer Rm extended.  */
 205   AARCH64_OPND_Rm_SFT,  /* Integer Rm shifted.  */
 206
 207   AARCH64_OPND_Fd,      /* Floating-point Fd.  */
 208   AARCH64_OPND_Fn,      /* Floating-point Fn.  */
 209   AARCH64_OPND_Fm,      /* Floating-point Fm.  */
 210   AARCH64_OPND_Fa,      /* Floating-point Fa.  */
 211   AARCH64_OPND_Ft,      /* Floating-point Ft.  */
 212   AARCH64_OPND_Ft2,     /* Floating-point Ft2.  */
 213
 214   AARCH64_OPND_Sd,      /* AdvSIMD Scalar Sd.  */
 215   AARCH64_OPND_Sn,      /* AdvSIMD Scalar Sn.  */
 216   AARCH64_OPND_Sm,      /* AdvSIMD Scalar Sm.  */
 217
 218   AARCH64_OPND_Va,      /* AdvSIMD Vector Va.  */
 219   AARCH64_OPND_Vd,      /* AdvSIMD Vector Vd.  */
 220   AARCH64_OPND_Vn,      /* AdvSIMD Vector Vn.  */
 221   AARCH64_OPND_Vm,      /* AdvSIMD Vector Vm.  */
 222   AARCH64_OPND_VdD1,    /* AdvSIMD <Vd>.D[1]; for FMOV only.  */
 223   AARCH64_OPND_VnD1,    /* AdvSIMD <Vn>.D[1]; for FMOV only.  */
 224   AARCH64_OPND_Ed,      /* AdvSIMD Vector Element Vd.  */
 225   AARCH64_OPND_En,      /* AdvSIMD Vector Element Vn.  */
 226   AARCH64_OPND_Em,      /* AdvSIMD Vector Element Vm.  */
 227   AARCH64_OPND_Em16,    /* AdvSIMD Vector Element Vm restricted to V0 - V15 when
 228                            qualifier is S_H.  */
 229   AARCH64_OPND_LVn,     /* AdvSIMD Vector register list used in e.g. TBL.  */
 230   AARCH64_OPND_LVt,     /* AdvSIMD Vector register list used in ld/st.  */
 231   AARCH64_OPND_LVt_AL,  /* AdvSIMD Vector register list for loading single
 232                            structure to all lanes.  */
 233   AARCH64_OPND_LEt,     /* AdvSIMD Vector Element list.  */
 234
 235   AARCH64_OPND_CRn,     /* Co-processor register in CRn field.  */
 236   AARCH64_OPND_CRm,     /* Co-processor register in CRm field.  */
 237
 238   AARCH64_OPND_IDX,     /* AdvSIMD EXT index operand.  */
 239   AARCH64_OPND_MASK,    /* AdvSIMD EXT index operand.  */
 240   AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left.  */
 241   AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right.  */
 242   AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift.  */
 243   AARCH64_OPND_SIMD_IMM_SFT,    /* AdvSIMD modified immediate with shift.  */
 244   AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate.  */
 245   AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
 246                            (no encoding).  */
 247   AARCH64_OPND_IMM0,    /* Immediate for #0.  */
 248   AARCH64_OPND_FPIMM0,  /* Immediate for #0.0.  */
 249   AARCH64_OPND_FPIMM,   /* Floating-point Immediate.  */
 250   AARCH64_OPND_IMMR,    /* Immediate #<immr> in e.g. BFM.  */
 251   AARCH64_OPND_IMMS,    /* Immediate #<imms> in e.g. BFM.  */
 252   AARCH64_OPND_WIDTH,   /* Immediate #<width> in e.g. BFI.  */
 253   AARCH64_OPND_IMM,     /* Immediate.  */
 254   AARCH64_OPND_IMM_2,   /* Immediate.  */
 255   AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field.  */
 256   AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field.  */
 257   AARCH64_OPND_UIMM4,   /* Unsigned 4-bit immediate in the CRm field.  */
 258   AARCH64_OPND_UIMM4_ADDG,/* Unsigned 4-bit immediate in addg/subg.  */
 259   AARCH64_OPND_UIMM7,   /* Unsigned 7-bit immediate in the CRm:op2 fields.  */
 260   AARCH64_OPND_UIMM10,  /* Unsigned 10-bit immediate in addg/subg.  */
 261   AARCH64_OPND_BIT_NUM, /* Immediate.  */
 262   AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions.  */
 263   AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions.  */
 264   AARCH64_OPND_SIMM5,   /* 5-bit signed immediate in the imm5 field.  */
 265   AARCH64_OPND_NZCV,    /* Flag bit specifier giving an alternative value for
 266                            each condition flag.  */
 267
 268   AARCH64_OPND_LIMM,    /* Logical Immediate.  */
 269   AARCH64_OPND_AIMM,    /* Arithmetic immediate.  */
 270   AARCH64_OPND_HALF,    /* #<imm16>{, LSL #<shift>} operand in move wide.  */
 271   AARCH64_OPND_FBITS,   /* FP #<fbits> operand in e.g. SCVTF */
 272   AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias.  */
 273   AARCH64_OPND_IMM_ROT1,        /* Immediate rotate operand for FCMLA.  */
 274   AARCH64_OPND_IMM_ROT2,        /* Immediate rotate operand for indexed FCMLA.  */
 275   AARCH64_OPND_IMM_ROT3,        /* Immediate rotate operand for FCADD.  */
 276
 277   AARCH64_OPND_COND,    /* Standard condition as the last operand.  */
 278   AARCH64_OPND_COND1,   /* Same as the above, but excluding AL and NV.  */
 279
 280   AARCH64_OPND_ADDR_ADRP,       /* Memory address for ADRP */
 281   AARCH64_OPND_ADDR_PCREL14,    /* 14-bit PC-relative address for e.g. TBZ.  */
 282   AARCH64_OPND_ADDR_PCREL19,    /* 19-bit PC-relative address for e.g. LDR.  */
 283   AARCH64_OPND_ADDR_PCREL21,    /* 21-bit PC-relative address for e.g. ADR.  */
 284   AARCH64_OPND_ADDR_PCREL26,    /* 26-bit PC-relative address for e.g. BL.  */
 285
 286   AARCH64_OPND_ADDR_SIMPLE,     /* Address of ld/st exclusive.  */
 287   AARCH64_OPND_ADDR_REGOFF,     /* Address of register offset.  */
 288   AARCH64_OPND_ADDR_SIMM7,      /* Address of signed 7-bit immediate.  */
 289   AARCH64_OPND_ADDR_SIMM9,      /* Address of signed 9-bit immediate.  */
 290   AARCH64_OPND_ADDR_SIMM9_2,    /* Same as the above, but the immediate is
 291                                    negative or unaligned and there is
 292                                    no writeback allowed.  This operand code
 293                                    is only used to support the programmer-
 294                                    friendly feature of using LDR/STR as the
 295                                    the mnemonic name for LDUR/STUR instructions
 296                                    wherever there is no ambiguity.  */
 297   AARCH64_OPND_ADDR_SIMM10,     /* Address of signed 10-bit immediate.  */
 298   AARCH64_OPND_ADDR_SIMM11,     /* Address with a signed 11-bit (multiple of
 299                                    16) immediate.  */
 300   AARCH64_OPND_ADDR_UIMM12,     /* Address of unsigned 12-bit immediate.  */
 301   AARCH64_OPND_ADDR_SIMM13,     /* Address with a signed 13-bit (multiple of
 302                                    16) immediate.  */
 303   AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures.  */
 304   AARCH64_OPND_ADDR_OFFSET,     /* Address with an optional 9-bit immediate.  */
 305   AARCH64_OPND_SIMD_ADDR_POST,  /* Address of ld/st multiple post-indexed.  */
 306
 307   AARCH64_OPND_SYSREG,          /* System register operand.  */
 308   AARCH64_OPND_PSTATEFIELD,     /* PSTATE field name operand.  */
 309   AARCH64_OPND_SYSREG_AT,       /* System register <at_op> operand.  */
 310   AARCH64_OPND_SYSREG_DC,       /* System register <dc_op> operand.  */
 311   AARCH64_OPND_SYSREG_IC,       /* System register <ic_op> operand.  */
 312   AARCH64_OPND_SYSREG_TLBI,     /* System register <tlbi_op> operand.  */
 313   AARCH64_OPND_SYSREG_SR,       /* System register RCTX operand.  */
 314   AARCH64_OPND_BARRIER,         /* Barrier operand.  */
 315   AARCH64_OPND_BARRIER_ISB,     /* Barrier operand for ISB.  */
 316   AARCH64_OPND_PRFOP,           /* Prefetch operation.  */
 317   AARCH64_OPND_BARRIER_PSB,     /* Barrier operand for PSB.  */
 318   AARCH64_OPND_BTI_TARGET,      /* BTI {<target>}.  */
 319
 320   AARCH64_OPND_SVE_ADDR_RI_S4x16,   /* SVE [<Xn|SP>, #<simm4>*16].  */
 321   AARCH64_OPND_SVE_ADDR_RI_S4xVL,   /* SVE [<Xn|SP>, #<simm4>, MUL VL].  */
 322   AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL].  */
 323   AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL].  */
 324   AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL].  */
 325   AARCH64_OPND_SVE_ADDR_RI_S6xVL,   /* SVE [<Xn|SP>, #<simm6>, MUL VL].  */
 326   AARCH64_OPND_SVE_ADDR_RI_S9xVL,   /* SVE [<Xn|SP>, #<simm9>, MUL VL].  */
 327   AARCH64_OPND_SVE_ADDR_RI_U6,      /* SVE [<Xn|SP>, #<uimm6>].  */
 328   AARCH64_OPND_SVE_ADDR_RI_U6x2,    /* SVE [<Xn|SP>, #<uimm6>*2].  */
 329   AARCH64_OPND_SVE_ADDR_RI_U6x4,    /* SVE [<Xn|SP>, #<uimm6>*4].  */
 330   AARCH64_OPND_SVE_ADDR_RI_U6x8,    /* SVE [<Xn|SP>, #<uimm6>*8].  */
 331   AARCH64_OPND_SVE_ADDR_R,          /* SVE [<Xn|SP>].  */
 332   AARCH64_OPND_SVE_ADDR_RR,         /* SVE [<Xn|SP>, <Xm|XZR>].  */
 333   AARCH64_OPND_SVE_ADDR_RR_LSL1,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1].  */
 334   AARCH64_OPND_SVE_ADDR_RR_LSL2,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2].  */
 335   AARCH64_OPND_SVE_ADDR_RR_LSL3,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3].  */
 336   AARCH64_OPND_SVE_ADDR_RX,         /* SVE [<Xn|SP>, <Xm>].  */
 337   AARCH64_OPND_SVE_ADDR_RX_LSL1,    /* SVE [<Xn|SP>, <Xm>, LSL #1].  */
 338   AARCH64_OPND_SVE_ADDR_RX_LSL2,    /* SVE [<Xn|SP>, <Xm>, LSL #2].  */
 339   AARCH64_OPND_SVE_ADDR_RX_LSL3,    /* SVE [<Xn|SP>, <Xm>, LSL #3].  */
 340   AARCH64_OPND_SVE_ADDR_RZ,         /* SVE [<Xn|SP>, Zm.D].  */
 341   AARCH64_OPND_SVE_ADDR_RZ_LSL1,    /* SVE [<Xn|SP>, Zm.D, LSL #1].  */
 342   AARCH64_OPND_SVE_ADDR_RZ_LSL2,    /* SVE [<Xn|SP>, Zm.D, LSL #2].  */
 343   AARCH64_OPND_SVE_ADDR_RZ_LSL3,    /* SVE [<Xn|SP>, Zm.D, LSL #3].  */
 344   AARCH64_OPND_SVE_ADDR_RZ_XTW_14,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 345                                        Bit 14 controls S/U choice.  */
 346   AARCH64_OPND_SVE_ADDR_RZ_XTW_22,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 347                                        Bit 22 controls S/U choice.  */
 348   AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 349                                        Bit 14 controls S/U choice.  */
 350   AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 351                                        Bit 22 controls S/U choice.  */
 352   AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 353                                        Bit 14 controls S/U choice.  */
 354   AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 355                                        Bit 22 controls S/U choice.  */
 356   AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 357                                        Bit 14 controls S/U choice.  */
 358   AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 359                                        Bit 22 controls S/U choice.  */
 360   AARCH64_OPND_SVE_ADDR_ZI_U5,      /* SVE [Zn.<T>, #<uimm5>].  */
 361   AARCH64_OPND_SVE_ADDR_ZI_U5x2,    /* SVE [Zn.<T>, #<uimm5>*2].  */
 362   AARCH64_OPND_SVE_ADDR_ZI_U5x4,    /* SVE [Zn.<T>, #<uimm5>*4].  */
 363   AARCH64_OPND_SVE_ADDR_ZI_U5x8,    /* SVE [Zn.<T>, #<uimm5>*8].  */
 364   AARCH64_OPND_SVE_ADDR_ZZ_LSL,     /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>].  */
 365   AARCH64_OPND_SVE_ADDR_ZZ_SXTW,    /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>].  */
 366   AARCH64_OPND_SVE_ADDR_ZZ_UXTW,    /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>].  */
 367   AARCH64_OPND_SVE_AIMM,        /* SVE unsigned arithmetic immediate.  */
 368   AARCH64_OPND_SVE_ASIMM,       /* SVE signed arithmetic immediate.  */
 369   AARCH64_OPND_SVE_FPIMM8,      /* SVE 8-bit floating-point immediate.  */
 370   AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0.  */
 371   AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0.  */
 372   AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0.  */
 373   AARCH64_OPND_SVE_IMM_ROT1,    /* SVE 1-bit rotate operand (90 or 270).  */
 374   AARCH64_OPND_SVE_IMM_ROT2,    /* SVE 2-bit rotate operand (N*90).  */
 375   AARCH64_OPND_SVE_IMM_ROT3,    /* SVE cadd 1-bit rotate (90 or 270).  */
 376   AARCH64_OPND_SVE_INV_LIMM,    /* SVE inverted logical immediate.  */
 377   AARCH64_OPND_SVE_LIMM,        /* SVE logical immediate.  */
 378   AARCH64_OPND_SVE_LIMM_MOV,    /* SVE logical immediate for MOV.  */
 379   AARCH64_OPND_SVE_PATTERN,     /* SVE vector pattern enumeration.  */
 380   AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor.  */
 381   AARCH64_OPND_SVE_PRFOP,       /* SVE prefetch operation.  */
 382   AARCH64_OPND_SVE_Pd,          /* SVE p0-p15 in Pd.  */
 383   AARCH64_OPND_SVE_Pg3,         /* SVE p0-p7 in Pg.  */
 384   AARCH64_OPND_SVE_Pg4_5,       /* SVE p0-p15 in Pg, bits [8,5].  */
 385   AARCH64_OPND_SVE_Pg4_10,      /* SVE p0-p15 in Pg, bits [13,10].  */
 386   AARCH64_OPND_SVE_Pg4_16,      /* SVE p0-p15 in Pg, bits [19,16].  */
 387   AARCH64_OPND_SVE_Pm,          /* SVE p0-p15 in Pm.  */
 388   AARCH64_OPND_SVE_Pn,          /* SVE p0-p15 in Pn.  */
 389   AARCH64_OPND_SVE_Pt,          /* SVE p0-p15 in Pt.  */
 390   AARCH64_OPND_SVE_Rm,          /* Integer Rm or ZR, alt. SVE position.  */
 391   AARCH64_OPND_SVE_Rn_SP,       /* Integer Rn or SP, alt. SVE position.  */
 392   AARCH64_OPND_SVE_SHLIMM_PRED,   /* SVE shift left amount (predicated).  */
 393   AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated).  */
 394   AARCH64_OPND_SVE_SHRIMM_PRED,   /* SVE shift right amount (predicated).  */
 395   AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated).  */
 396   AARCH64_OPND_SVE_SIMM5,       /* SVE signed 5-bit immediate.  */
 397   AARCH64_OPND_SVE_SIMM5B,      /* SVE secondary signed 5-bit immediate.  */
 398   AARCH64_OPND_SVE_SIMM6,       /* SVE signed 6-bit immediate.  */
 399   AARCH64_OPND_SVE_SIMM8,       /* SVE signed 8-bit immediate.  */
 400   AARCH64_OPND_SVE_UIMM3,       /* SVE unsigned 3-bit immediate.  */
 401   AARCH64_OPND_SVE_UIMM7,       /* SVE unsigned 7-bit immediate.  */
 402   AARCH64_OPND_SVE_UIMM8,       /* SVE unsigned 8-bit immediate.  */
 403   AARCH64_OPND_SVE_UIMM8_53,    /* SVE split unsigned 8-bit immediate.  */
 404   AARCH64_OPND_SVE_VZn,         /* Scalar SIMD&FP register in Zn field.  */
 405   AARCH64_OPND_SVE_Vd,          /* Scalar SIMD&FP register in Vd.  */
 406   AARCH64_OPND_SVE_Vm,          /* Scalar SIMD&FP register in Vm.  */
 407   AARCH64_OPND_SVE_Vn,          /* Scalar SIMD&FP register in Vn.  */
 408   AARCH64_OPND_SVE_Za_5,        /* SVE vector register in Za, bits [9,5].  */
 409   AARCH64_OPND_SVE_Za_16,       /* SVE vector register in Za, bits [20,16].  */
 410   AARCH64_OPND_SVE_Zd,          /* SVE vector register in Zd.  */
 411   AARCH64_OPND_SVE_Zm_5,        /* SVE vector register in Zm, bits [9,5].  */
 412   AARCH64_OPND_SVE_Zm_16,       /* SVE vector register in Zm, bits [20,16].  */
 413   AARCH64_OPND_SVE_Zm3_INDEX,   /* z0-z7[0-3] in Zm, bits [20,16].  */
 414   AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22.  */
 415   AARCH64_OPND_SVE_Zm4_INDEX,   /* z0-z15[0-1] in Zm, bits [20,16].  */
 416   AARCH64_OPND_SVE_Zn,          /* SVE vector register in Zn.  */
 417   AARCH64_OPND_SVE_Zn_INDEX,    /* Indexed SVE vector register, for DUP.  */
 418   AARCH64_OPND_SVE_ZnxN,        /* SVE vector register list in Zn.  */
 419   AARCH64_OPND_SVE_Zt,          /* SVE vector register in Zt.  */
 420   AARCH64_OPND_SVE_ZtxN,        /* SVE vector register list in Zt.  */
 421   AARCH64_OPND_TME_UIMM16,      /* TME unsigned 16-bit immediate.  */
 422   AARCH64_OPND_SM3_IMM2,        /* SM3 encodes lane in bits [13, 14].  */
 423 };
 424
 425 /* Qualifier constrains an operand.  It either specifies a variant of an
 426    operand type or limits values available to an operand type.
 427
 428    N.B. Order is important; keep aarch64_opnd_qualifiers synced.  */
 429
 430 enum aarch64_opnd_qualifier
 431 {
 432   /* Indicating no further qualification on an operand.  */
 433   AARCH64_OPND_QLF_NIL,
 434
 435   /* Qualifying an operand which is a general purpose (integer) register;
 436      indicating the operand data size or a specific register.  */
 437   AARCH64_OPND_QLF_W,   /* Wn, WZR or WSP.  */
 438   AARCH64_OPND_QLF_X,   /* Xn, XZR or XSP.  */
 439   AARCH64_OPND_QLF_WSP, /* WSP.  */
 440   AARCH64_OPND_QLF_SP,  /* SP.  */
 441
 442   /* Qualifying an operand which is a floating-point register, a SIMD
 443      vector element or a SIMD vector element list; indicating operand data
 444      size or the size of each SIMD vector element in the case of a SIMD
 445      vector element list.
 446      These qualifiers are also used to qualify an address operand to
 447      indicate the size of data element a load/store instruction is
 448      accessing.
 449      They are also used for the immediate shift operand in e.g. SSHR.  Such
 450      a use is only for the ease of operand encoding/decoding and qualifier
 451      sequence matching; such a use should not be applied widely; use the value
 452      constraint qualifiers for immediate operands wherever possible.  */
 453   AARCH64_OPND_QLF_S_B,
 454   AARCH64_OPND_QLF_S_H,
 455   AARCH64_OPND_QLF_S_S,
 456   AARCH64_OPND_QLF_S_D,
 457   AARCH64_OPND_QLF_S_Q,
 458   /* This type qualifier has a special meaning in that it means that 4 x 1 byte
 459      are selected by the instruction.  Other than that it has no difference
 460      with AARCH64_OPND_QLF_S_B in encoding.  It is here purely for syntactical
 461      reasons and is an exception from normal AArch64 disassembly scheme.  */
 462   AARCH64_OPND_QLF_S_4B,
 463
 464   /* Qualifying an operand which is a SIMD vector register or a SIMD vector
 465      register list; indicating register shape.
 466      They are also used for the immediate shift operand in e.g. SSHR.  Such
 467      a use is only for the ease of operand encoding/decoding and qualifier
 468      sequence matching; such a use should not be applied widely; use the value
 469      constraint qualifiers for immediate operands wherever possible.  */
 470   AARCH64_OPND_QLF_V_4B,
 471   AARCH64_OPND_QLF_V_8B,
 472   AARCH64_OPND_QLF_V_16B,
 473   AARCH64_OPND_QLF_V_2H,
 474   AARCH64_OPND_QLF_V_4H,
 475   AARCH64_OPND_QLF_V_8H,
 476   AARCH64_OPND_QLF_V_2S,
 477   AARCH64_OPND_QLF_V_4S,
 478   AARCH64_OPND_QLF_V_1D,
 479   AARCH64_OPND_QLF_V_2D,
 480   AARCH64_OPND_QLF_V_1Q,
 481
 482   AARCH64_OPND_QLF_P_Z,
 483   AARCH64_OPND_QLF_P_M,
 484
 485   /* Used in scaled signed immediate that are scaled by a Tag granule
 486      like in stg, st2g, etc.   */
 487   AARCH64_OPND_QLF_imm_tag,
 488
 489   /* Constraint on value.  */
 490   AARCH64_OPND_QLF_CR,          /* CRn, CRm. */
 491   AARCH64_OPND_QLF_imm_0_7,
 492   AARCH64_OPND_QLF_imm_0_15,
 493   AARCH64_OPND_QLF_imm_0_31,
 494   AARCH64_OPND_QLF_imm_0_63,
 495   AARCH64_OPND_QLF_imm_1_32,
 496   AARCH64_OPND_QLF_imm_1_64,
 497
 498   /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
 499      or shift-ones.  */
 500   AARCH64_OPND_QLF_LSL,
 501   AARCH64_OPND_QLF_MSL,
 502
 503   /* Special qualifier helping retrieve qualifier information during the
 504      decoding time (currently not in use).  */
 505   AARCH64_OPND_QLF_RETRIEVE,
 506 };
 507 \f
 508 /* Instruction class.  */
 509
 510 enum aarch64_insn_class
 511 {
 512   addsub_carry,
 513   addsub_ext,
 514   addsub_imm,
 515   addsub_shift,
 516   asimdall,
 517   asimddiff,
 518   asimdelem,
 519   asimdext,
 520   asimdimm,
 521   asimdins,
 522   asimdmisc,
 523   asimdperm,
 524   asimdsame,
 525   asimdshf,
 526   asimdtbl,
 527   asisddiff,
 528   asisdelem,
 529   asisdlse,
 530   asisdlsep,
 531   asisdlso,
 532   asisdlsop,
 533   asisdmisc,
 534   asisdone,
 535   asisdpair,
 536   asisdsame,
 537   asisdshf,
 538   bitfield,
 539   branch_imm,
 540   branch_reg,
 541   compbranch,
 542   condbranch,
 543   condcmp_imm,
 544   condcmp_reg,
 545   condsel,
 546   cryptoaes,
 547   cryptosha2,
 548   cryptosha3,
 549   dp_1src,
 550   dp_2src,
 551   dp_3src,
 552   exception,
 553   extract,
 554   float2fix,
 555   float2int,
 556   floatccmp,
 557   floatcmp,
 558   floatdp1,
 559   floatdp2,
 560   floatdp3,
 561   floatimm,
 562   floatsel,
 563   ldst_immpost,
 564   ldst_immpre,
 565   ldst_imm9,    /* immpost or immpre */
 566   ldst_imm10,   /* LDRAA/LDRAB */
 567   ldst_pos,
 568   ldst_regoff,
 569   ldst_unpriv,
 570   ldst_unscaled,
 571   ldstexcl,
 572   ldstnapair_offs,
 573   ldstpair_off,
 574   ldstpair_indexed,
 575   loadlit,
 576   log_imm,
 577   log_shift,
 578   lse_atomic,
 579   movewide,
 580   pcreladdr,
 581   ic_system,
 582   sve_cpy,
 583   sve_index,
 584   sve_limm,
 585   sve_misc,
 586   sve_movprfx,
 587   sve_pred_zm,
 588   sve_shift_pred,
 589   sve_shift_unpred,
 590   sve_size_bhs,
 591   sve_size_bhsd,
 592   sve_size_hsd,
 593   sve_size_hsd2,
 594   sve_size_sd,
 595   testbranch,
 596   cryptosm3,
 597   cryptosm4,
 598   dotproduct,
 599 };
 600
 601 /* Opcode enumerators.  */
 602
 603 enum aarch64_op
 604 {
 605   OP_NIL,
 606   OP_STRB_POS,
 607   OP_LDRB_POS,
 608   OP_LDRSB_POS,
 609   OP_STRH_POS,
 610   OP_LDRH_POS,
 611   OP_LDRSH_POS,
 612   OP_STR_POS,
 613   OP_LDR_POS,
 614   OP_STRF_POS,
 615   OP_LDRF_POS,
 616   OP_LDRSW_POS,
 617   OP_PRFM_POS,
 618
 619   OP_STURB,
 620   OP_LDURB,
 621   OP_LDURSB,
 622   OP_STURH,
 623   OP_LDURH,
 624   OP_LDURSH,
 625   OP_STUR,
 626   OP_LDUR,
 627   OP_STURV,
 628   OP_LDURV,
 629   OP_LDURSW,
 630   OP_PRFUM,
 631
 632   OP_LDR_LIT,
 633   OP_LDRV_LIT,
 634   OP_LDRSW_LIT,
 635   OP_PRFM_LIT,
 636
 637   OP_ADD,
 638   OP_B,
 639   OP_BL,
 640
 641   OP_MOVN,
 642   OP_MOVZ,
 643   OP_MOVK,
 644
 645   OP_MOV_IMM_LOG,       /* MOV alias for moving bitmask immediate.  */
 646   OP_MOV_IMM_WIDE,      /* MOV alias for moving wide immediate.  */
 647   OP_MOV_IMM_WIDEN,     /* MOV alias for moving wide immediate (negated).  */
 648
 649   OP_MOV_V,             /* MOV alias for moving vector register.  */
 650
 651   OP_ASR_IMM,
 652   OP_LSR_IMM,
 653   OP_LSL_IMM,
 654
 655   OP_BIC,
 656
 657   OP_UBFX,
 658   OP_BFXIL,
 659   OP_SBFX,
 660   OP_SBFIZ,
 661   OP_BFI,
 662   OP_BFC,               /* ARMv8.2.  */
 663   OP_UBFIZ,
 664   OP_UXTB,
 665   OP_UXTH,
 666   OP_UXTW,
 667
 668   OP_CINC,
 669   OP_CINV,
 670   OP_CNEG,
 671   OP_CSET,
 672   OP_CSETM,
 673
 674   OP_FCVT,
 675   OP_FCVTN,
 676   OP_FCVTN2,
 677   OP_FCVTL,
 678   OP_FCVTL2,
 679   OP_FCVTXN_S,          /* Scalar version.  */
 680
 681   OP_ROR_IMM,
 682
 683   OP_SXTL,
 684   OP_SXTL2,
 685   OP_UXTL,
 686   OP_UXTL2,
 687
 688   OP_MOV_P_P,
 689   OP_MOV_Z_P_Z,
 690   OP_MOV_Z_V,
 691   OP_MOV_Z_Z,
 692   OP_MOV_Z_Zi,
 693   OP_MOVM_P_P_P,
 694   OP_MOVS_P_P,
 695   OP_MOVZS_P_P_P,
 696   OP_MOVZ_P_P_P,
 697   OP_NOTS_P_P_P_Z,
 698   OP_NOT_P_P_P_Z,
 699
 700   OP_FCMLA_ELEM,        /* ARMv8.3, indexed element version.  */
 701
 702   OP_TOTAL_NUM,         /* Pseudo.  */
 703 };
 704
 705 /* Error types.  */
 706 enum err_type
 707 {
 708   ERR_OK,
 709   ERR_UND,
 710   ERR_UNP,
 711   ERR_NYI,
 712   ERR_VFI,
 713   ERR_NR_ENTRIES
 714 };
 715
 716 /* Maximum number of operands an instruction can have.  */
 717 #define AARCH64_MAX_OPND_NUM 6
 718 /* Maximum number of qualifier sequences an instruction can have.  */
 719 #define AARCH64_MAX_QLF_SEQ_NUM 10
 720 /* Operand qualifier typedef; optimized for the size.  */
 721 typedef unsigned char aarch64_opnd_qualifier_t;
 722 /* Operand qualifier sequence typedef.  */
 723 typedef aarch64_opnd_qualifier_t        \
 724           aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
 725
 726 /* FIXME: improve the efficiency.  */
 727 static inline bfd_boolean
 728 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
 729 {
 730   int i;
 731   for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
 732     if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
 733       return FALSE;
 734   return TRUE;
 735 }
 736
 737 /*  Forward declare error reporting type.  */
 738 typedef struct aarch64_operand_error aarch64_operand_error;
 739 /* Forward declare instruction sequence type.  */
 740 typedef struct aarch64_instr_sequence aarch64_instr_sequence;
 741 /* Forward declare instruction definition.  */
 742 typedef struct aarch64_inst aarch64_inst;
 743
 744 /* This structure holds information for a particular opcode.  */
 745
 746 struct aarch64_opcode
 747 {
 748   /* The name of the mnemonic.  */
 749   const char *name;
 750
 751   /* The opcode itself.  Those bits which will be filled in with
 752      operands are zeroes.  */
 753   aarch64_insn opcode;
 754
 755   /* The opcode mask.  This is used by the disassembler.  This is a
 756      mask containing ones indicating those bits which must match the
 757      opcode field, and zeroes indicating those bits which need not
 758      match (and are presumably filled in by operands).  */
 759   aarch64_insn mask;
 760
 761   /* Instruction class.  */
 762   enum aarch64_insn_class iclass;
 763
 764   /* Enumerator identifier.  */
 765   enum aarch64_op op;
 766
 767   /* Which architecture variant provides this instruction.  */
 768   const aarch64_feature_set *avariant;
 769
 770   /* An array of operand codes.  Each code is an index into the
 771      operand table.  They appear in the order which the operands must
 772      appear in assembly code, and are terminated by a zero.  */
 773   enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
 774
 775   /* A list of operand qualifier code sequence.  Each operand qualifier
 776      code qualifies the corresponding operand code.  Each operand
 777      qualifier sequence specifies a valid opcode variant and related
 778      constraint on operands.  */
 779   aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
 780
 781   /* Flags providing information about this instruction */
 782   uint64_t flags;
 783
 784   /* Extra constraints on the instruction that the verifier checks.  */
 785   uint32_t constraints;
 786
 787   /* If nonzero, this operand and operand 0 are both registers and
 788      are required to have the same register number.  */
 789   unsigned char tied_operand;
 790
 791   /* If non-NULL, a function to verify that a given instruction is valid.  */
 792   enum err_type (* verifier) (const struct aarch64_inst *, const aarch64_insn,
 793                               bfd_vma, bfd_boolean, aarch64_operand_error *,
 794                               struct aarch64_instr_sequence *);
 795 };
 796
 797 typedef struct aarch64_opcode aarch64_opcode;
 798
 799 /* Table describing all the AArch64 opcodes.  */
 800 extern aarch64_opcode aarch64_opcode_table[];
 801
 802 /* Opcode flags.  */
 803 #define F_ALIAS (1 << 0)
 804 #define F_HAS_ALIAS (1 << 1)
 805 /* Disassembly preference priority 1-3 (the larger the higher).  If nothing
 806    is specified, it is the priority 0 by default, i.e. the lowest priority.  */
 807 #define F_P1 (1 << 2)
 808 #define F_P2 (2 << 2)
 809 #define F_P3 (3 << 2)
 810 /* Flag an instruction that is truly conditional executed, e.g. b.cond.  */
 811 #define F_COND (1 << 4)
 812 /* Instruction has the field of 'sf'.  */
 813 #define F_SF (1 << 5)
 814 /* Instruction has the field of 'size:Q'.  */
 815 #define F_SIZEQ (1 << 6)
 816 /* Floating-point instruction has the field of 'type'.  */
 817 #define F_FPTYPE (1 << 7)
 818 /* AdvSIMD scalar instruction has the field of 'size'.  */
 819 #define F_SSIZE (1 << 8)
 820 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q".  */
 821 #define F_T (1 << 9)
 822 /* Size of GPR operand in AdvSIMD instructions encoded in Q.  */
 823 #define F_GPRSIZE_IN_Q (1 << 10)
 824 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22.  */
 825 #define F_LDS_SIZE (1 << 11)
 826 /* Optional operand; assume maximum of 1 operand can be optional.  */
 827 #define F_OPD0_OPT (1 << 12)
 828 #define F_OPD1_OPT (2 << 12)
 829 #define F_OPD2_OPT (3 << 12)
 830 #define F_OPD3_OPT (4 << 12)
 831 #define F_OPD4_OPT (5 << 12)
 832 /* Default value for the optional operand when omitted from the assembly.  */
 833 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
 834 /* Instruction that is an alias of another instruction needs to be
 835    encoded/decoded by converting it to/from the real form, followed by
 836    the encoding/decoding according to the rules of the real opcode.
 837    This compares to the direct coding using the alias's information.
 838    N.B. this flag requires F_ALIAS to be used together.  */
 839 #define F_CONV (1 << 20)
 840 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
 841    friendly pseudo instruction available only in the assembly code (thus will
 842    not show up in the disassembly).  */
 843 #define F_PSEUDO (1 << 21)
 844 /* Instruction has miscellaneous encoding/decoding rules.  */
 845 #define F_MISC (1 << 22)
 846 /* Instruction has the field of 'N'; used in conjunction with F_SF.  */
 847 #define F_N (1 << 23)
 848 /* Opcode dependent field.  */
 849 #define F_OD(X) (((X) & 0x7) << 24)
 850 /* Instruction has the field of 'sz'.  */
 851 #define F_LSE_SZ (1 << 27)
 852 /* Require an exact qualifier match, even for NIL qualifiers.  */
 853 #define F_STRICT (1ULL << 28)
 854 /* This system instruction is used to read system registers.  */
 855 #define F_SYS_READ (1ULL << 29)
 856 /* This system instruction is used to write system registers.  */
 857 #define F_SYS_WRITE (1ULL << 30)
 858 /* This instruction has an extra constraint on it that imposes a requirement on
 859    subsequent instructions.  */
 860 #define F_SCAN (1ULL << 31)
 861 /* Next bit is 32.  */
 862
 863 /* Instruction constraints.  */
 864 /* This instruction has a predication constraint on the instruction at PC+4.  */
 865 #define C_SCAN_MOVPRFX (1U << 0)
 866 /* This instruction's operation width is determined by the operand with the
 867    largest element size.  */
 868 #define C_MAX_ELEM (1U << 1)
 869 /* Next bit is 2.  */
 870
 871 static inline bfd_boolean
 872 alias_opcode_p (const aarch64_opcode *opcode)
 873 {
 874   return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
 875 }
 876
 877 static inline bfd_boolean
 878 opcode_has_alias (const aarch64_opcode *opcode)
 879 {
 880   return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
 881 }
 882
 883 /* Priority for disassembling preference.  */
 884 static inline int
 885 opcode_priority (const aarch64_opcode *opcode)
 886 {
 887   return (opcode->flags >> 2) & 0x3;
 888 }
 889
 890 static inline bfd_boolean
 891 pseudo_opcode_p (const aarch64_opcode *opcode)
 892 {
 893   return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
 894 }
 895
 896 static inline bfd_boolean
 897 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
 898 {
 899   return (((opcode->flags >> 12) & 0x7) == idx + 1)
 900     ? TRUE : FALSE;
 901 }
 902
 903 static inline aarch64_insn
 904 get_optional_operand_default_value (const aarch64_opcode *opcode)
 905 {
 906   return (opcode->flags >> 15) & 0x1f;
 907 }
 908
 909 static inline unsigned int
 910 get_opcode_dependent_value (const aarch64_opcode *opcode)
 911 {
 912   return (opcode->flags >> 24) & 0x7;
 913 }
 914
 915 static inline bfd_boolean
 916 opcode_has_special_coder (const aarch64_opcode *opcode)
 917 {
 918   return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
 919           | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
 920     : FALSE;
 921 }
 922 \f
 923 struct aarch64_name_value_pair
 924 {
 925   const char *  name;
 926   aarch64_insn  value;
 927 };
 928
 929 extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
 930 extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
 931 extern const struct aarch64_name_value_pair aarch64_prfops [32];
 932 extern const struct aarch64_name_value_pair aarch64_hint_options [];
 933
 934 typedef struct
 935 {
 936   const char *  name;
 937   aarch64_insn  value;
 938   uint32_t      flags;
 939 } aarch64_sys_reg;
 940
 941 extern const aarch64_sys_reg aarch64_sys_regs [];
 942 extern const aarch64_sys_reg aarch64_pstatefields [];
 943 extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
 944 extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
 945                                                 const aarch64_sys_reg *);
 946 extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
 947                                                     const aarch64_sys_reg *);
 948
 949 typedef struct
 950 {
 951   const char *name;
 952   uint32_t value;
 953   uint32_t flags ;
 954 } aarch64_sys_ins_reg;
 955
 956 extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
 957 extern bfd_boolean
 958 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
 959                                  const aarch64_sys_ins_reg *);
 960
 961 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
 962 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
 963 extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
 964 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
 965 extern const aarch64_sys_ins_reg aarch64_sys_regs_sr [];
 966
 967 /* Shift/extending operator kinds.
 968    N.B. order is important; keep aarch64_operand_modifiers synced.  */
 969 enum aarch64_modifier_kind
 970 {
 971   AARCH64_MOD_NONE,
 972   AARCH64_MOD_MSL,
 973   AARCH64_MOD_ROR,
 974   AARCH64_MOD_ASR,
 975   AARCH64_MOD_LSR,
 976   AARCH64_MOD_LSL,
 977   AARCH64_MOD_UXTB,
 978   AARCH64_MOD_UXTH,
 979   AARCH64_MOD_UXTW,
 980   AARCH64_MOD_UXTX,
 981   AARCH64_MOD_SXTB,
 982   AARCH64_MOD_SXTH,
 983   AARCH64_MOD_SXTW,
 984   AARCH64_MOD_SXTX,
 985   AARCH64_MOD_MUL,
 986   AARCH64_MOD_MUL_VL,
 987 };
 988
 989 bfd_boolean
 990 aarch64_extend_operator_p (enum aarch64_modifier_kind);
 991
 992 enum aarch64_modifier_kind
 993 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
 994 /* Condition.  */
 995
 996 typedef struct
 997 {
 998   /* A list of names with the first one as the disassembly preference;
 999      terminated by NULL if fewer than 3.  */
1000   const char *names[4];
1001   aarch64_insn value;
1002 } aarch64_cond;
1003
1004 extern const aarch64_cond aarch64_conds[16];
1005
1006 const aarch64_cond* get_cond_from_value (aarch64_insn value);
1007 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
1008 \f
1009 /* Structure representing an operand.  */
1010
1011 struct aarch64_opnd_info
1012 {
1013   enum aarch64_opnd type;
1014   aarch64_opnd_qualifier_t qualifier;
1015   int idx;
1016
1017   union
1018     {
1019       struct
1020         {
1021           unsigned regno;
1022         } reg;
1023       struct
1024         {
1025           unsigned int regno;
1026           int64_t index;
1027         } reglane;
1028       /* e.g. LVn.  */
1029       struct
1030         {
1031           unsigned first_regno : 5;
1032           unsigned num_regs : 3;
1033           /* 1 if it is a list of reg element.  */
1034           unsigned has_index : 1;
1035           /* Lane index; valid only when has_index is 1.  */
1036           int64_t index;
1037         } reglist;
1038       /* e.g. immediate or pc relative address offset.  */
1039       struct
1040         {
1041           int64_t value;
1042           unsigned is_fp : 1;
1043         } imm;
1044       /* e.g. address in STR (register offset).  */
1045       struct
1046         {
1047           unsigned base_regno;
1048           struct
1049             {
1050               union
1051                 {
1052                   int imm;
1053                   unsigned regno;
1054                 };
1055               unsigned is_reg;
1056             } offset;
1057           unsigned pcrel : 1;           /* PC-relative.  */
1058           unsigned writeback : 1;
1059           unsigned preind : 1;          /* Pre-indexed.  */
1060           unsigned postind : 1;         /* Post-indexed.  */
1061         } addr;
1062
1063       struct
1064         {
1065           /* The encoding of the system register.  */
1066           aarch64_insn value;
1067
1068           /* The system register flags.  */
1069           uint32_t flags;
1070         } sysreg;
1071
1072       const aarch64_cond *cond;
1073       /* The encoding of the PSTATE field.  */
1074       aarch64_insn pstatefield;
1075       const aarch64_sys_ins_reg *sysins_op;
1076       const struct aarch64_name_value_pair *barrier;
1077       const struct aarch64_name_value_pair *hint_option;
1078       const struct aarch64_name_value_pair *prfop;
1079     };
1080
1081   /* Operand shifter; in use when the operand is a register offset address,
1082      add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}.  */
1083   struct
1084     {
1085       enum aarch64_modifier_kind kind;
1086       unsigned operator_present: 1;     /* Only valid during encoding.  */
1087       /* Value of the 'S' field in ld/st reg offset; used only in decoding.  */
1088       unsigned amount_present: 1;
1089       int64_t amount;
1090     } shifter;
1091
1092   unsigned skip:1;      /* Operand is not completed if there is a fixup needed
1093                            to be done on it.  In some (but not all) of these
1094                            cases, we need to tell libopcodes to skip the
1095                            constraint checking and the encoding for this
1096                            operand, so that the libopcodes can pick up the
1097                            right opcode before the operand is fixed-up.  This
1098                            flag should only be used during the
1099                            assembling/encoding.  */
1100   unsigned present:1;   /* Whether this operand is present in the assembly
1101                            line; not used during the disassembly.  */
1102 };
1103
1104 typedef struct aarch64_opnd_info aarch64_opnd_info;
1105
1106 /* Structure representing an instruction.
1107
1108    It is used during both the assembling and disassembling.  The assembler
1109    fills an aarch64_inst after a successful parsing and then passes it to the
1110    encoding routine to do the encoding.  During the disassembling, the
1111    disassembler calls the decoding routine to decode a binary instruction; on a
1112    successful return, such a structure will be filled with information of the
1113    instruction; then the disassembler uses the information to print out the
1114    instruction.  */
1115
1116 struct aarch64_inst
1117 {
1118   /* The value of the binary instruction.  */
1119   aarch64_insn value;
1120
1121   /* Corresponding opcode entry.  */
1122   const aarch64_opcode *opcode;
1123
1124   /* Condition for a truly conditional-executed instrutions, e.g. b.cond.  */
1125   const aarch64_cond *cond;
1126
1127   /* Operands information.  */
1128   aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
1129 };
1130
1131 /* Defining the HINT #imm values for the aarch64_hint_options.  */
1132 #define HINT_OPD_CSYNC  0x11
1133 #define HINT_OPD_C      0x22
1134 #define HINT_OPD_J      0x24
1135 #define HINT_OPD_JC     0x26
1136 #define HINT_OPD_NULL   0x00
1137
1138 \f
1139 /* Diagnosis related declaration and interface.  */
1140
1141 /* Operand error kind enumerators.
1142
1143    AARCH64_OPDE_RECOVERABLE
1144      Less severe error found during the parsing, very possibly because that
1145      GAS has picked up a wrong instruction template for the parsing.
1146
1147    AARCH64_OPDE_SYNTAX_ERROR
1148      General syntax error; it can be either a user error, or simply because
1149      that GAS is trying a wrong instruction template.
1150
1151    AARCH64_OPDE_FATAL_SYNTAX_ERROR
1152      Definitely a user syntax error.
1153
1154    AARCH64_OPDE_INVALID_VARIANT
1155      No syntax error, but the operands are not a valid combination, e.g.
1156      FMOV D0,S0
1157
1158    AARCH64_OPDE_UNTIED_OPERAND
1159      The asm failed to use the same register for a destination operand
1160      and a tied source operand.
1161
1162    AARCH64_OPDE_OUT_OF_RANGE
1163      Error about some immediate value out of a valid range.
1164
1165    AARCH64_OPDE_UNALIGNED
1166      Error about some immediate value not properly aligned (i.e. not being a
1167      multiple times of a certain value).
1168
1169    AARCH64_OPDE_REG_LIST
1170      Error about the register list operand having unexpected number of
1171      registers.
1172
1173    AARCH64_OPDE_OTHER_ERROR
1174      Error of the highest severity and used for any severe issue that does not
1175      fall into any of the above categories.
1176
1177    The enumerators are only interesting to GAS.  They are declared here (in
1178    libopcodes) because that some errors are detected (and then notified to GAS)
1179    by libopcodes (rather than by GAS solely).
1180
1181    The first three errors are only deteced by GAS while the
1182    AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1183    only libopcodes has the information about the valid variants of each
1184    instruction.
1185
1186    The enumerators have an increasing severity.  This is helpful when there are
1187    multiple instruction templates available for a given mnemonic name (e.g.
1188    FMOV); this mechanism will help choose the most suitable template from which
1189    the generated diagnostics can most closely describe the issues, if any.  */
1190
1191 enum aarch64_operand_error_kind
1192 {
1193   AARCH64_OPDE_NIL,
1194   AARCH64_OPDE_RECOVERABLE,
1195   AARCH64_OPDE_SYNTAX_ERROR,
1196   AARCH64_OPDE_FATAL_SYNTAX_ERROR,
1197   AARCH64_OPDE_INVALID_VARIANT,
1198   AARCH64_OPDE_UNTIED_OPERAND,
1199   AARCH64_OPDE_OUT_OF_RANGE,
1200   AARCH64_OPDE_UNALIGNED,
1201   AARCH64_OPDE_REG_LIST,
1202   AARCH64_OPDE_OTHER_ERROR
1203 };
1204
1205 /* N.B. GAS assumes that this structure work well with shallow copy.  */
1206 struct aarch64_operand_error
1207 {
1208   enum aarch64_operand_error_kind kind;
1209   int index;
1210   const char *error;
1211   int data[3];  /* Some data for extra information.  */
1212   bfd_boolean non_fatal;
1213 };
1214
1215 /* AArch64 sequence structure used to track instructions with F_SCAN
1216    dependencies for both assembler and disassembler.  */
1217 struct aarch64_instr_sequence
1218 {
1219   /* The instruction that caused this sequence to be opened.  */
1220   aarch64_inst *instr;
1221   /* The number of instructions the above instruction allows to be kept in the
1222      sequence before an automatic close is done.  */
1223   int num_insns;
1224   /* The instructions currently added to the sequence.  */
1225   aarch64_inst **current_insns;
1226   /* The number of instructions already in the sequence.  */
1227   int next_insn;
1228 };
1229
1230 /* Encoding entrypoint.  */
1231
1232 extern int
1233 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1234                        aarch64_insn *, aarch64_opnd_qualifier_t *,
1235                        aarch64_operand_error *, aarch64_instr_sequence *);
1236
1237 extern const aarch64_opcode *
1238 aarch64_replace_opcode (struct aarch64_inst *,
1239                         const aarch64_opcode *);
1240
1241 /* Given the opcode enumerator OP, return the pointer to the corresponding
1242    opcode entry.  */
1243
1244 extern const aarch64_opcode *
1245 aarch64_get_opcode (enum aarch64_op);
1246
1247 /* Generate the string representation of an operand.  */
1248 extern void
1249 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
1250                        const aarch64_opnd_info *, int, int *, bfd_vma *,
1251                        char **);
1252
1253 /* Miscellaneous interface.  */
1254
1255 extern int
1256 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1257
1258 extern aarch64_opnd_qualifier_t
1259 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1260                                 const aarch64_opnd_qualifier_t, int);
1261
1262 extern bfd_boolean
1263 aarch64_is_destructive_by_operands (const aarch64_opcode *);
1264
1265 extern int
1266 aarch64_num_of_operands (const aarch64_opcode *);
1267
1268 extern int
1269 aarch64_stack_pointer_p (const aarch64_opnd_info *);
1270
1271 extern int
1272 aarch64_zero_register_p (const aarch64_opnd_info *);
1273
1274 extern enum err_type
1275 aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean,
1276                      aarch64_operand_error *);
1277
1278 extern void
1279 init_insn_sequence (const struct aarch64_inst *, aarch64_instr_sequence *);
1280
1281 /* Given an operand qualifier, return the expected data element size
1282    of a qualified operand.  */
1283 extern unsigned char
1284 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1285
1286 extern enum aarch64_operand_class
1287 aarch64_get_operand_class (enum aarch64_opnd);
1288
1289 extern const char *
1290 aarch64_get_operand_name (enum aarch64_opnd);
1291
1292 extern const char *
1293 aarch64_get_operand_desc (enum aarch64_opnd);
1294
1295 extern bfd_boolean
1296 aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1297
1298 #ifdef DEBUG_AARCH64
1299 extern int debug_dump;
1300
1301 extern void
1302 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1303
1304 #define DEBUG_TRACE(M, ...)                                     \
1305   {                                                             \
1306     if (debug_dump)                                             \
1307       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1308   }
1309
1310 #define DEBUG_TRACE_IF(C, M, ...)                               \
1311   {                                                             \
1312     if (debug_dump && (C))                                      \
1313       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1314   }
1315 #else  /* !DEBUG_AARCH64 */
1316 #define DEBUG_TRACE(M, ...) ;
1317 #define DEBUG_TRACE_IF(C, M, ...) ;
1318 #endif /* DEBUG_AARCH64 */
1319
1320 extern const char *const aarch64_sve_pattern_array[32];
1321 extern const char *const aarch64_sve_prfop_array[16];
1322
1323 #ifdef __cplusplus
1324 }
1325 #endif
1326
1327 #endif /* OPCODE_AARCH64_H */