include/opcode/aarch64.h

   1 /* AArch64 assembler/disassembler support.
   2
   3    Copyright (C) 2009-2019 Free Software Foundation, Inc.
   4    Contributed by ARM Ltd.
   5
   6    This file is part of GNU Binutils.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the license, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; see the file COPYING3. If not,
  20    see <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef OPCODE_AARCH64_H
  23 #define OPCODE_AARCH64_H
  24
  25 #include "bfd.h"
  26 #include "bfd_stdint.h"
  27 #include <assert.h>
  28 #include <stdlib.h>
  29
  30 #ifdef __cplusplus
  31 extern "C" {
  32 #endif
  33
  34 /* The offset for pc-relative addressing is currently defined to be 0.  */
  35 #define AARCH64_PCREL_OFFSET            0
  36
  37 typedef uint32_t aarch64_insn;
  38
  39 /* The following bitmasks control CPU features.  */
  40 #define AARCH64_FEATURE_SHA2    0x200000000ULL  /* SHA2 instructions.  */
  41 #define AARCH64_FEATURE_AES     0x800000000ULL  /* AES instructions.  */
  42 #define AARCH64_FEATURE_V8_4    0x000000800ULL  /* ARMv8.4 processors.  */
  43 #define AARCH64_FEATURE_SM4     0x100000000ULL  /* SM3 & SM4 instructions.  */
  44 #define AARCH64_FEATURE_SHA3    0x400000000ULL  /* SHA3 instructions.  */
  45 #define AARCH64_FEATURE_V8      0x00000001      /* All processors.  */
  46 #define AARCH64_FEATURE_V8_2    0x00000020      /* ARMv8.2 processors.  */
  47 #define AARCH64_FEATURE_V8_3    0x00000040      /* ARMv8.3 processors.  */
  48 #define AARCH64_FEATURE_CRYPTO  0x00010000      /* Crypto instructions.  */
  49 #define AARCH64_FEATURE_FP      0x00020000      /* FP instructions.  */
  50 #define AARCH64_FEATURE_SIMD    0x00040000      /* SIMD instructions.  */
  51 #define AARCH64_FEATURE_CRC     0x00080000      /* CRC instructions.  */
  52 #define AARCH64_FEATURE_LSE     0x00100000      /* LSE instructions.  */
  53 #define AARCH64_FEATURE_PAN     0x00200000      /* PAN instructions.  */
  54 #define AARCH64_FEATURE_LOR     0x00400000      /* LOR instructions.  */
  55 #define AARCH64_FEATURE_RDMA    0x00800000      /* v8.1 SIMD instructions.  */
  56 #define AARCH64_FEATURE_V8_1    0x01000000      /* v8.1 features.  */
  57 #define AARCH64_FEATURE_F16     0x02000000      /* v8.2 FP16 instructions.  */
  58 #define AARCH64_FEATURE_RAS     0x04000000      /* RAS Extensions.  */
  59 #define AARCH64_FEATURE_PROFILE 0x08000000      /* Statistical Profiling.  */
  60 #define AARCH64_FEATURE_SVE     0x10000000      /* SVE instructions.  */
  61 #define AARCH64_FEATURE_RCPC    0x20000000      /* RCPC instructions.  */
  62 #define AARCH64_FEATURE_COMPNUM 0x40000000      /* Complex # instructions.  */
  63 #define AARCH64_FEATURE_DOTPROD 0x080000000     /* Dot Product instructions.  */
  64 #define AARCH64_FEATURE_F16_FML 0x1000000000ULL /* v8.2 FP16FML ins.  */
  65 #define AARCH64_FEATURE_V8_5    0x2000000000ULL /* ARMv8.5 processors.  */
  66
  67 /* Flag Manipulation insns.  */
  68 #define AARCH64_FEATURE_FLAGMANIP       0x4000000000ULL
  69 /* FRINT[32,64][Z,X] insns.  */
  70 #define AARCH64_FEATURE_FRINTTS         0x8000000000ULL
  71 /* SB instruction.  */
  72 #define AARCH64_FEATURE_SB              0x10000000000ULL
  73 /* Execution and Data Prediction Restriction instructions.  */
  74 #define AARCH64_FEATURE_PREDRES         0x20000000000ULL
  75 /* DC CVADP.  */
  76 #define AARCH64_FEATURE_CVADP           0x40000000000ULL
  77 /* Random Number instructions.  */
  78 #define AARCH64_FEATURE_RNG             0x80000000000ULL
  79 /* BTI instructions.  */
  80 #define AARCH64_FEATURE_BTI             0x100000000000ULL
  81 /* SCXTNUM_ELx.  */
  82 #define AARCH64_FEATURE_SCXTNUM         0x200000000000ULL
  83 /* ID_PFR2 instructions.  */
  84 #define AARCH64_FEATURE_ID_PFR2         0x400000000000ULL
  85 /* SSBS mechanism enabled.  */
  86 #define AARCH64_FEATURE_SSBS            0x800000000000ULL
  87 /* Memory Tagging Extension.  */
  88 #define AARCH64_FEATURE_MEMTAG          0x1000000000000ULL
  89
  90
  91 /* Architectures are the sum of the base and extensions.  */
  92 #define AARCH64_ARCH_V8         AARCH64_FEATURE (AARCH64_FEATURE_V8, \
  93                                                  AARCH64_FEATURE_FP  \
  94                                                  | AARCH64_FEATURE_SIMD)
  95 #define AARCH64_ARCH_V8_1       AARCH64_FEATURE (AARCH64_ARCH_V8, \
  96                                                  AARCH64_FEATURE_CRC    \
  97                                                  | AARCH64_FEATURE_V8_1 \
  98                                                  | AARCH64_FEATURE_LSE  \
  99                                                  | AARCH64_FEATURE_PAN  \
 100                                                  | AARCH64_FEATURE_LOR  \
 101                                                  | AARCH64_FEATURE_RDMA)
 102 #define AARCH64_ARCH_V8_2       AARCH64_FEATURE (AARCH64_ARCH_V8_1,     \
 103                                                  AARCH64_FEATURE_V8_2   \
 104                                                  | AARCH64_FEATURE_RAS)
 105 #define AARCH64_ARCH_V8_3       AARCH64_FEATURE (AARCH64_ARCH_V8_2,     \
 106                                                  AARCH64_FEATURE_V8_3   \
 107                                                  | AARCH64_FEATURE_RCPC \
 108                                                  | AARCH64_FEATURE_COMPNUM)
 109 #define AARCH64_ARCH_V8_4       AARCH64_FEATURE (AARCH64_ARCH_V8_3,     \
 110                                                  AARCH64_FEATURE_V8_4   \
 111                                                  | AARCH64_FEATURE_DOTPROD \
 112                                                  | AARCH64_FEATURE_F16_FML)
 113 #define AARCH64_ARCH_V8_5       AARCH64_FEATURE (AARCH64_ARCH_V8_4,     \
 114                                                  AARCH64_FEATURE_V8_5   \
 115                                                  | AARCH64_FEATURE_FLAGMANIP \
 116                                                  | AARCH64_FEATURE_FRINTTS \
 117                                                  | AARCH64_FEATURE_SB   \
 118                                                  | AARCH64_FEATURE_PREDRES \
 119                                                  | AARCH64_FEATURE_CVADP \
 120                                                  | AARCH64_FEATURE_BTI  \
 121                                                  | AARCH64_FEATURE_SCXTNUM \
 122                                                  | AARCH64_FEATURE_ID_PFR2 \
 123                                                  | AARCH64_FEATURE_SSBS)
 124
 125
 126 #define AARCH64_ARCH_NONE       AARCH64_FEATURE (0, 0)
 127 #define AARCH64_ANY             AARCH64_FEATURE (-1, 0) /* Any basic core.  */
 128
 129 /* CPU-specific features.  */
 130 typedef unsigned long long aarch64_feature_set;
 131
 132 #define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT)  \
 133   ((~(CPU) & (FEAT)) == 0)
 134
 135 #define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT)  \
 136   (((CPU) & (FEAT)) != 0)
 137
 138 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT)       \
 139   AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
 140
 141 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2)  \
 142   do                                            \
 143     {                                           \
 144       (TARG) = (F1) | (F2);                     \
 145     }                                           \
 146   while (0)
 147
 148 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2)       \
 149   do                                            \
 150     {                                           \
 151       (TARG) = (F1) &~ (F2);                    \
 152     }                                           \
 153   while (0)
 154
 155 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
 156
 157 enum aarch64_operand_class
 158 {
 159   AARCH64_OPND_CLASS_NIL,
 160   AARCH64_OPND_CLASS_INT_REG,
 161   AARCH64_OPND_CLASS_MODIFIED_REG,
 162   AARCH64_OPND_CLASS_FP_REG,
 163   AARCH64_OPND_CLASS_SIMD_REG,
 164   AARCH64_OPND_CLASS_SIMD_ELEMENT,
 165   AARCH64_OPND_CLASS_SISD_REG,
 166   AARCH64_OPND_CLASS_SIMD_REGLIST,
 167   AARCH64_OPND_CLASS_SVE_REG,
 168   AARCH64_OPND_CLASS_PRED_REG,
 169   AARCH64_OPND_CLASS_ADDRESS,
 170   AARCH64_OPND_CLASS_IMMEDIATE,
 171   AARCH64_OPND_CLASS_SYSTEM,
 172   AARCH64_OPND_CLASS_COND,
 173 };
 174
 175 /* Operand code that helps both parsing and coding.
 176    Keep AARCH64_OPERANDS synced.  */
 177
 178 enum aarch64_opnd
 179 {
 180   AARCH64_OPND_NIL,     /* no operand---MUST BE FIRST!*/
 181
 182   AARCH64_OPND_Rd,      /* Integer register as destination.  */
 183   AARCH64_OPND_Rn,      /* Integer register as source.  */
 184   AARCH64_OPND_Rm,      /* Integer register as source.  */
 185   AARCH64_OPND_Rt,      /* Integer register used in ld/st instructions.  */
 186   AARCH64_OPND_Rt2,     /* Integer register used in ld/st pair instructions.  */
 187   AARCH64_OPND_Rt_SP,   /* Integer Rt or SP used in STG instructions.  */
 188   AARCH64_OPND_Rs,      /* Integer register used in ld/st exclusive.  */
 189   AARCH64_OPND_Ra,      /* Integer register used in ddp_3src instructions.  */
 190   AARCH64_OPND_Rt_SYS,  /* Integer register used in system instructions.  */
 191
 192   AARCH64_OPND_Rd_SP,   /* Integer Rd or SP.  */
 193   AARCH64_OPND_Rn_SP,   /* Integer Rn or SP.  */
 194   AARCH64_OPND_Rm_SP,   /* Integer Rm or SP.  */
 195   AARCH64_OPND_PAIRREG, /* Paired register operand.  */
 196   AARCH64_OPND_Rm_EXT,  /* Integer Rm extended.  */
 197   AARCH64_OPND_Rm_SFT,  /* Integer Rm shifted.  */
 198
 199   AARCH64_OPND_Fd,      /* Floating-point Fd.  */
 200   AARCH64_OPND_Fn,      /* Floating-point Fn.  */
 201   AARCH64_OPND_Fm,      /* Floating-point Fm.  */
 202   AARCH64_OPND_Fa,      /* Floating-point Fa.  */
 203   AARCH64_OPND_Ft,      /* Floating-point Ft.  */
 204   AARCH64_OPND_Ft2,     /* Floating-point Ft2.  */
 205
 206   AARCH64_OPND_Sd,      /* AdvSIMD Scalar Sd.  */
 207   AARCH64_OPND_Sn,      /* AdvSIMD Scalar Sn.  */
 208   AARCH64_OPND_Sm,      /* AdvSIMD Scalar Sm.  */
 209
 210   AARCH64_OPND_Va,      /* AdvSIMD Vector Va.  */
 211   AARCH64_OPND_Vd,      /* AdvSIMD Vector Vd.  */
 212   AARCH64_OPND_Vn,      /* AdvSIMD Vector Vn.  */
 213   AARCH64_OPND_Vm,      /* AdvSIMD Vector Vm.  */
 214   AARCH64_OPND_VdD1,    /* AdvSIMD <Vd>.D[1]; for FMOV only.  */
 215   AARCH64_OPND_VnD1,    /* AdvSIMD <Vn>.D[1]; for FMOV only.  */
 216   AARCH64_OPND_Ed,      /* AdvSIMD Vector Element Vd.  */
 217   AARCH64_OPND_En,      /* AdvSIMD Vector Element Vn.  */
 218   AARCH64_OPND_Em,      /* AdvSIMD Vector Element Vm.  */
 219   AARCH64_OPND_Em16,    /* AdvSIMD Vector Element Vm restricted to V0 - V15 when
 220                            qualifier is S_H.  */
 221   AARCH64_OPND_LVn,     /* AdvSIMD Vector register list used in e.g. TBL.  */
 222   AARCH64_OPND_LVt,     /* AdvSIMD Vector register list used in ld/st.  */
 223   AARCH64_OPND_LVt_AL,  /* AdvSIMD Vector register list for loading single
 224                            structure to all lanes.  */
 225   AARCH64_OPND_LEt,     /* AdvSIMD Vector Element list.  */
 226
 227   AARCH64_OPND_CRn,     /* Co-processor register in CRn field.  */
 228   AARCH64_OPND_CRm,     /* Co-processor register in CRm field.  */
 229
 230   AARCH64_OPND_IDX,     /* AdvSIMD EXT index operand.  */
 231   AARCH64_OPND_MASK,    /* AdvSIMD EXT index operand.  */
 232   AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left.  */
 233   AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right.  */
 234   AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift.  */
 235   AARCH64_OPND_SIMD_IMM_SFT,    /* AdvSIMD modified immediate with shift.  */
 236   AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate.  */
 237   AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
 238                            (no encoding).  */
 239   AARCH64_OPND_IMM0,    /* Immediate for #0.  */
 240   AARCH64_OPND_FPIMM0,  /* Immediate for #0.0.  */
 241   AARCH64_OPND_FPIMM,   /* Floating-point Immediate.  */
 242   AARCH64_OPND_IMMR,    /* Immediate #<immr> in e.g. BFM.  */
 243   AARCH64_OPND_IMMS,    /* Immediate #<imms> in e.g. BFM.  */
 244   AARCH64_OPND_WIDTH,   /* Immediate #<width> in e.g. BFI.  */
 245   AARCH64_OPND_IMM,     /* Immediate.  */
 246   AARCH64_OPND_IMM_2,   /* Immediate.  */
 247   AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field.  */
 248   AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field.  */
 249   AARCH64_OPND_UIMM4,   /* Unsigned 4-bit immediate in the CRm field.  */
 250   AARCH64_OPND_UIMM4_ADDG,/* Unsigned 4-bit immediate in addg/subg.  */
 251   AARCH64_OPND_UIMM7,   /* Unsigned 7-bit immediate in the CRm:op2 fields.  */
 252   AARCH64_OPND_UIMM10,  /* Unsigned 10-bit immediate in addg/subg.  */
 253   AARCH64_OPND_BIT_NUM, /* Immediate.  */
 254   AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions.  */
 255   AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions.  */
 256   AARCH64_OPND_SIMM5,   /* 5-bit signed immediate in the imm5 field.  */
 257   AARCH64_OPND_NZCV,    /* Flag bit specifier giving an alternative value for
 258                            each condition flag.  */
 259
 260   AARCH64_OPND_LIMM,    /* Logical Immediate.  */
 261   AARCH64_OPND_AIMM,    /* Arithmetic immediate.  */
 262   AARCH64_OPND_HALF,    /* #<imm16>{, LSL #<shift>} operand in move wide.  */
 263   AARCH64_OPND_FBITS,   /* FP #<fbits> operand in e.g. SCVTF */
 264   AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias.  */
 265   AARCH64_OPND_IMM_ROT1,        /* Immediate rotate operand for FCMLA.  */
 266   AARCH64_OPND_IMM_ROT2,        /* Immediate rotate operand for indexed FCMLA.  */
 267   AARCH64_OPND_IMM_ROT3,        /* Immediate rotate operand for FCADD.  */
 268
 269   AARCH64_OPND_COND,    /* Standard condition as the last operand.  */
 270   AARCH64_OPND_COND1,   /* Same as the above, but excluding AL and NV.  */
 271
 272   AARCH64_OPND_ADDR_ADRP,       /* Memory address for ADRP */
 273   AARCH64_OPND_ADDR_PCREL14,    /* 14-bit PC-relative address for e.g. TBZ.  */
 274   AARCH64_OPND_ADDR_PCREL19,    /* 19-bit PC-relative address for e.g. LDR.  */
 275   AARCH64_OPND_ADDR_PCREL21,    /* 21-bit PC-relative address for e.g. ADR.  */
 276   AARCH64_OPND_ADDR_PCREL26,    /* 26-bit PC-relative address for e.g. BL.  */
 277
 278   AARCH64_OPND_ADDR_SIMPLE,     /* Address of ld/st exclusive.  */
 279   AARCH64_OPND_ADDR_REGOFF,     /* Address of register offset.  */
 280   AARCH64_OPND_ADDR_SIMM7,      /* Address of signed 7-bit immediate.  */
 281   AARCH64_OPND_ADDR_SIMM9,      /* Address of signed 9-bit immediate.  */
 282   AARCH64_OPND_ADDR_SIMM9_2,    /* Same as the above, but the immediate is
 283                                    negative or unaligned and there is
 284                                    no writeback allowed.  This operand code
 285                                    is only used to support the programmer-
 286                                    friendly feature of using LDR/STR as the
 287                                    the mnemonic name for LDUR/STUR instructions
 288                                    wherever there is no ambiguity.  */
 289   AARCH64_OPND_ADDR_SIMM10,     /* Address of signed 10-bit immediate.  */
 290   AARCH64_OPND_ADDR_SIMM11,     /* Address with a signed 11-bit (multiple of
 291                                    16) immediate.  */
 292   AARCH64_OPND_ADDR_UIMM12,     /* Address of unsigned 12-bit immediate.  */
 293   AARCH64_OPND_ADDR_SIMM13,     /* Address with a signed 13-bit (multiple of
 294                                    16) immediate.  */
 295   AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures.  */
 296   AARCH64_OPND_ADDR_OFFSET,     /* Address with an optional 9-bit immediate.  */
 297   AARCH64_OPND_SIMD_ADDR_POST,  /* Address of ld/st multiple post-indexed.  */
 298
 299   AARCH64_OPND_SYSREG,          /* System register operand.  */
 300   AARCH64_OPND_PSTATEFIELD,     /* PSTATE field name operand.  */
 301   AARCH64_OPND_SYSREG_AT,       /* System register <at_op> operand.  */
 302   AARCH64_OPND_SYSREG_DC,       /* System register <dc_op> operand.  */
 303   AARCH64_OPND_SYSREG_IC,       /* System register <ic_op> operand.  */
 304   AARCH64_OPND_SYSREG_TLBI,     /* System register <tlbi_op> operand.  */
 305   AARCH64_OPND_SYSREG_SR,       /* System register RCTX operand.  */
 306   AARCH64_OPND_BARRIER,         /* Barrier operand.  */
 307   AARCH64_OPND_BARRIER_ISB,     /* Barrier operand for ISB.  */
 308   AARCH64_OPND_PRFOP,           /* Prefetch operation.  */
 309   AARCH64_OPND_BARRIER_PSB,     /* Barrier operand for PSB.  */
 310   AARCH64_OPND_BTI_TARGET,      /* BTI {<target>}.  */
 311
 312   AARCH64_OPND_SVE_ADDR_RI_S4x16,   /* SVE [<Xn|SP>, #<simm4>*16].  */
 313   AARCH64_OPND_SVE_ADDR_RI_S4xVL,   /* SVE [<Xn|SP>, #<simm4>, MUL VL].  */
 314   AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL].  */
 315   AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL].  */
 316   AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL].  */
 317   AARCH64_OPND_SVE_ADDR_RI_S6xVL,   /* SVE [<Xn|SP>, #<simm6>, MUL VL].  */
 318   AARCH64_OPND_SVE_ADDR_RI_S9xVL,   /* SVE [<Xn|SP>, #<simm9>, MUL VL].  */
 319   AARCH64_OPND_SVE_ADDR_RI_U6,      /* SVE [<Xn|SP>, #<uimm6>].  */
 320   AARCH64_OPND_SVE_ADDR_RI_U6x2,    /* SVE [<Xn|SP>, #<uimm6>*2].  */
 321   AARCH64_OPND_SVE_ADDR_RI_U6x4,    /* SVE [<Xn|SP>, #<uimm6>*4].  */
 322   AARCH64_OPND_SVE_ADDR_RI_U6x8,    /* SVE [<Xn|SP>, #<uimm6>*8].  */
 323   AARCH64_OPND_SVE_ADDR_R,          /* SVE [<Xn|SP>].  */
 324   AARCH64_OPND_SVE_ADDR_RR,         /* SVE [<Xn|SP>, <Xm|XZR>].  */
 325   AARCH64_OPND_SVE_ADDR_RR_LSL1,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1].  */
 326   AARCH64_OPND_SVE_ADDR_RR_LSL2,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2].  */
 327   AARCH64_OPND_SVE_ADDR_RR_LSL3,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3].  */
 328   AARCH64_OPND_SVE_ADDR_RX,         /* SVE [<Xn|SP>, <Xm>].  */
 329   AARCH64_OPND_SVE_ADDR_RX_LSL1,    /* SVE [<Xn|SP>, <Xm>, LSL #1].  */
 330   AARCH64_OPND_SVE_ADDR_RX_LSL2,    /* SVE [<Xn|SP>, <Xm>, LSL #2].  */
 331   AARCH64_OPND_SVE_ADDR_RX_LSL3,    /* SVE [<Xn|SP>, <Xm>, LSL #3].  */
 332   AARCH64_OPND_SVE_ADDR_RZ,         /* SVE [<Xn|SP>, Zm.D].  */
 333   AARCH64_OPND_SVE_ADDR_RZ_LSL1,    /* SVE [<Xn|SP>, Zm.D, LSL #1].  */
 334   AARCH64_OPND_SVE_ADDR_RZ_LSL2,    /* SVE [<Xn|SP>, Zm.D, LSL #2].  */
 335   AARCH64_OPND_SVE_ADDR_RZ_LSL3,    /* SVE [<Xn|SP>, Zm.D, LSL #3].  */
 336   AARCH64_OPND_SVE_ADDR_RZ_XTW_14,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 337                                        Bit 14 controls S/U choice.  */
 338   AARCH64_OPND_SVE_ADDR_RZ_XTW_22,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 339                                        Bit 22 controls S/U choice.  */
 340   AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 341                                        Bit 14 controls S/U choice.  */
 342   AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 343                                        Bit 22 controls S/U choice.  */
 344   AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 345                                        Bit 14 controls S/U choice.  */
 346   AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 347                                        Bit 22 controls S/U choice.  */
 348   AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 349                                        Bit 14 controls S/U choice.  */
 350   AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 351                                        Bit 22 controls S/U choice.  */
 352   AARCH64_OPND_SVE_ADDR_ZI_U5,      /* SVE [Zn.<T>, #<uimm5>].  */
 353   AARCH64_OPND_SVE_ADDR_ZI_U5x2,    /* SVE [Zn.<T>, #<uimm5>*2].  */
 354   AARCH64_OPND_SVE_ADDR_ZI_U5x4,    /* SVE [Zn.<T>, #<uimm5>*4].  */
 355   AARCH64_OPND_SVE_ADDR_ZI_U5x8,    /* SVE [Zn.<T>, #<uimm5>*8].  */
 356   AARCH64_OPND_SVE_ADDR_ZZ_LSL,     /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>].  */
 357   AARCH64_OPND_SVE_ADDR_ZZ_SXTW,    /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>].  */
 358   AARCH64_OPND_SVE_ADDR_ZZ_UXTW,    /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>].  */
 359   AARCH64_OPND_SVE_AIMM,        /* SVE unsigned arithmetic immediate.  */
 360   AARCH64_OPND_SVE_ASIMM,       /* SVE signed arithmetic immediate.  */
 361   AARCH64_OPND_SVE_FPIMM8,      /* SVE 8-bit floating-point immediate.  */
 362   AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0.  */
 363   AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0.  */
 364   AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0.  */
 365   AARCH64_OPND_SVE_IMM_ROT1,    /* SVE 1-bit rotate operand (90 or 270).  */
 366   AARCH64_OPND_SVE_IMM_ROT2,    /* SVE 2-bit rotate operand (N*90).  */
 367   AARCH64_OPND_SVE_INV_LIMM,    /* SVE inverted logical immediate.  */
 368   AARCH64_OPND_SVE_LIMM,        /* SVE logical immediate.  */
 369   AARCH64_OPND_SVE_LIMM_MOV,    /* SVE logical immediate for MOV.  */
 370   AARCH64_OPND_SVE_PATTERN,     /* SVE vector pattern enumeration.  */
 371   AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor.  */
 372   AARCH64_OPND_SVE_PRFOP,       /* SVE prefetch operation.  */
 373   AARCH64_OPND_SVE_Pd,          /* SVE p0-p15 in Pd.  */
 374   AARCH64_OPND_SVE_Pg3,         /* SVE p0-p7 in Pg.  */
 375   AARCH64_OPND_SVE_Pg4_5,       /* SVE p0-p15 in Pg, bits [8,5].  */
 376   AARCH64_OPND_SVE_Pg4_10,      /* SVE p0-p15 in Pg, bits [13,10].  */
 377   AARCH64_OPND_SVE_Pg4_16,      /* SVE p0-p15 in Pg, bits [19,16].  */
 378   AARCH64_OPND_SVE_Pm,          /* SVE p0-p15 in Pm.  */
 379   AARCH64_OPND_SVE_Pn,          /* SVE p0-p15 in Pn.  */
 380   AARCH64_OPND_SVE_Pt,          /* SVE p0-p15 in Pt.  */
 381   AARCH64_OPND_SVE_Rm,          /* Integer Rm or ZR, alt. SVE position.  */
 382   AARCH64_OPND_SVE_Rn_SP,       /* Integer Rn or SP, alt. SVE position.  */
 383   AARCH64_OPND_SVE_SHLIMM_PRED,   /* SVE shift left amount (predicated).  */
 384   AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated).  */
 385   AARCH64_OPND_SVE_SHRIMM_PRED,   /* SVE shift right amount (predicated).  */
 386   AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated).  */
 387   AARCH64_OPND_SVE_SIMM5,       /* SVE signed 5-bit immediate.  */
 388   AARCH64_OPND_SVE_SIMM5B,      /* SVE secondary signed 5-bit immediate.  */
 389   AARCH64_OPND_SVE_SIMM6,       /* SVE signed 6-bit immediate.  */
 390   AARCH64_OPND_SVE_SIMM8,       /* SVE signed 8-bit immediate.  */
 391   AARCH64_OPND_SVE_UIMM3,       /* SVE unsigned 3-bit immediate.  */
 392   AARCH64_OPND_SVE_UIMM7,       /* SVE unsigned 7-bit immediate.  */
 393   AARCH64_OPND_SVE_UIMM8,       /* SVE unsigned 8-bit immediate.  */
 394   AARCH64_OPND_SVE_UIMM8_53,    /* SVE split unsigned 8-bit immediate.  */
 395   AARCH64_OPND_SVE_VZn,         /* Scalar SIMD&FP register in Zn field.  */
 396   AARCH64_OPND_SVE_Vd,          /* Scalar SIMD&FP register in Vd.  */
 397   AARCH64_OPND_SVE_Vm,          /* Scalar SIMD&FP register in Vm.  */
 398   AARCH64_OPND_SVE_Vn,          /* Scalar SIMD&FP register in Vn.  */
 399   AARCH64_OPND_SVE_Za_5,        /* SVE vector register in Za, bits [9,5].  */
 400   AARCH64_OPND_SVE_Za_16,       /* SVE vector register in Za, bits [20,16].  */
 401   AARCH64_OPND_SVE_Zd,          /* SVE vector register in Zd.  */
 402   AARCH64_OPND_SVE_Zm_5,        /* SVE vector register in Zm, bits [9,5].  */
 403   AARCH64_OPND_SVE_Zm_16,       /* SVE vector register in Zm, bits [20,16].  */
 404   AARCH64_OPND_SVE_Zm3_INDEX,   /* z0-z7[0-3] in Zm, bits [20,16].  */
 405   AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22.  */
 406   AARCH64_OPND_SVE_Zm4_INDEX,   /* z0-z15[0-1] in Zm, bits [20,16].  */
 407   AARCH64_OPND_SVE_Zn,          /* SVE vector register in Zn.  */
 408   AARCH64_OPND_SVE_Zn_INDEX,    /* Indexed SVE vector register, for DUP.  */
 409   AARCH64_OPND_SVE_ZnxN,        /* SVE vector register list in Zn.  */
 410   AARCH64_OPND_SVE_Zt,          /* SVE vector register in Zt.  */
 411   AARCH64_OPND_SVE_ZtxN,        /* SVE vector register list in Zt.  */
 412   AARCH64_OPND_SM3_IMM2,        /* SM3 encodes lane in bits [13, 14].  */
 413 };
 414
 415 /* Qualifier constrains an operand.  It either specifies a variant of an
 416    operand type or limits values available to an operand type.
 417
 418    N.B. Order is important; keep aarch64_opnd_qualifiers synced.  */
 419
 420 enum aarch64_opnd_qualifier
 421 {
 422   /* Indicating no further qualification on an operand.  */
 423   AARCH64_OPND_QLF_NIL,
 424
 425   /* Qualifying an operand which is a general purpose (integer) register;
 426      indicating the operand data size or a specific register.  */
 427   AARCH64_OPND_QLF_W,   /* Wn, WZR or WSP.  */
 428   AARCH64_OPND_QLF_X,   /* Xn, XZR or XSP.  */
 429   AARCH64_OPND_QLF_WSP, /* WSP.  */
 430   AARCH64_OPND_QLF_SP,  /* SP.  */
 431
 432   /* Qualifying an operand which is a floating-point register, a SIMD
 433      vector element or a SIMD vector element list; indicating operand data
 434      size or the size of each SIMD vector element in the case of a SIMD
 435      vector element list.
 436      These qualifiers are also used to qualify an address operand to
 437      indicate the size of data element a load/store instruction is
 438      accessing.
 439      They are also used for the immediate shift operand in e.g. SSHR.  Such
 440      a use is only for the ease of operand encoding/decoding and qualifier
 441      sequence matching; such a use should not be applied widely; use the value
 442      constraint qualifiers for immediate operands wherever possible.  */
 443   AARCH64_OPND_QLF_S_B,
 444   AARCH64_OPND_QLF_S_H,
 445   AARCH64_OPND_QLF_S_S,
 446   AARCH64_OPND_QLF_S_D,
 447   AARCH64_OPND_QLF_S_Q,
 448   /* This type qualifier has a special meaning in that it means that 4 x 1 byte
 449      are selected by the instruction.  Other than that it has no difference
 450      with AARCH64_OPND_QLF_S_B in encoding.  It is here purely for syntactical
 451      reasons and is an exception from normal AArch64 disassembly scheme.  */
 452   AARCH64_OPND_QLF_S_4B,
 453
 454   /* Qualifying an operand which is a SIMD vector register or a SIMD vector
 455      register list; indicating register shape.
 456      They are also used for the immediate shift operand in e.g. SSHR.  Such
 457      a use is only for the ease of operand encoding/decoding and qualifier
 458      sequence matching; such a use should not be applied widely; use the value
 459      constraint qualifiers for immediate operands wherever possible.  */
 460   AARCH64_OPND_QLF_V_4B,
 461   AARCH64_OPND_QLF_V_8B,
 462   AARCH64_OPND_QLF_V_16B,
 463   AARCH64_OPND_QLF_V_2H,
 464   AARCH64_OPND_QLF_V_4H,
 465   AARCH64_OPND_QLF_V_8H,
 466   AARCH64_OPND_QLF_V_2S,
 467   AARCH64_OPND_QLF_V_4S,
 468   AARCH64_OPND_QLF_V_1D,
 469   AARCH64_OPND_QLF_V_2D,
 470   AARCH64_OPND_QLF_V_1Q,
 471
 472   AARCH64_OPND_QLF_P_Z,
 473   AARCH64_OPND_QLF_P_M,
 474
 475   /* Used in scaled signed immediate that are scaled by a Tag granule
 476      like in stg, st2g, etc.   */
 477   AARCH64_OPND_QLF_imm_tag,
 478
 479   /* Constraint on value.  */
 480   AARCH64_OPND_QLF_CR,          /* CRn, CRm. */
 481   AARCH64_OPND_QLF_imm_0_7,
 482   AARCH64_OPND_QLF_imm_0_15,
 483   AARCH64_OPND_QLF_imm_0_31,
 484   AARCH64_OPND_QLF_imm_0_63,
 485   AARCH64_OPND_QLF_imm_1_32,
 486   AARCH64_OPND_QLF_imm_1_64,
 487
 488   /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
 489      or shift-ones.  */
 490   AARCH64_OPND_QLF_LSL,
 491   AARCH64_OPND_QLF_MSL,
 492
 493   /* Special qualifier helping retrieve qualifier information during the
 494      decoding time (currently not in use).  */
 495   AARCH64_OPND_QLF_RETRIEVE,
 496 };
 497 \f
 498 /* Instruction class.  */
 499
 500 enum aarch64_insn_class
 501 {
 502   addsub_carry,
 503   addsub_ext,
 504   addsub_imm,
 505   addsub_shift,
 506   asimdall,
 507   asimddiff,
 508   asimdelem,
 509   asimdext,
 510   asimdimm,
 511   asimdins,
 512   asimdmisc,
 513   asimdperm,
 514   asimdsame,
 515   asimdshf,
 516   asimdtbl,
 517   asisddiff,
 518   asisdelem,
 519   asisdlse,
 520   asisdlsep,
 521   asisdlso,
 522   asisdlsop,
 523   asisdmisc,
 524   asisdone,
 525   asisdpair,
 526   asisdsame,
 527   asisdshf,
 528   bitfield,
 529   branch_imm,
 530   branch_reg,
 531   compbranch,
 532   condbranch,
 533   condcmp_imm,
 534   condcmp_reg,
 535   condsel,
 536   cryptoaes,
 537   cryptosha2,
 538   cryptosha3,
 539   dp_1src,
 540   dp_2src,
 541   dp_3src,
 542   exception,
 543   extract,
 544   float2fix,
 545   float2int,
 546   floatccmp,
 547   floatcmp,
 548   floatdp1,
 549   floatdp2,
 550   floatdp3,
 551   floatimm,
 552   floatsel,
 553   ldst_immpost,
 554   ldst_immpre,
 555   ldst_imm9,    /* immpost or immpre */
 556   ldst_imm10,   /* LDRAA/LDRAB */
 557   ldst_pos,
 558   ldst_regoff,
 559   ldst_unpriv,
 560   ldst_unscaled,
 561   ldstexcl,
 562   ldstnapair_offs,
 563   ldstpair_off,
 564   ldstpair_indexed,
 565   loadlit,
 566   log_imm,
 567   log_shift,
 568   lse_atomic,
 569   movewide,
 570   pcreladdr,
 571   ic_system,
 572   sve_cpy,
 573   sve_index,
 574   sve_limm,
 575   sve_misc,
 576   sve_movprfx,
 577   sve_pred_zm,
 578   sve_shift_pred,
 579   sve_shift_unpred,
 580   sve_size_bhs,
 581   sve_size_bhsd,
 582   sve_size_hsd,
 583   sve_size_sd,
 584   testbranch,
 585   cryptosm3,
 586   cryptosm4,
 587   dotproduct,
 588 };
 589
 590 /* Opcode enumerators.  */
 591
 592 enum aarch64_op
 593 {
 594   OP_NIL,
 595   OP_STRB_POS,
 596   OP_LDRB_POS,
 597   OP_LDRSB_POS,
 598   OP_STRH_POS,
 599   OP_LDRH_POS,
 600   OP_LDRSH_POS,
 601   OP_STR_POS,
 602   OP_LDR_POS,
 603   OP_STRF_POS,
 604   OP_LDRF_POS,
 605   OP_LDRSW_POS,
 606   OP_PRFM_POS,
 607
 608   OP_STURB,
 609   OP_LDURB,
 610   OP_LDURSB,
 611   OP_STURH,
 612   OP_LDURH,
 613   OP_LDURSH,
 614   OP_STUR,
 615   OP_LDUR,
 616   OP_STURV,
 617   OP_LDURV,
 618   OP_LDURSW,
 619   OP_PRFUM,
 620
 621   OP_LDR_LIT,
 622   OP_LDRV_LIT,
 623   OP_LDRSW_LIT,
 624   OP_PRFM_LIT,
 625
 626   OP_ADD,
 627   OP_B,
 628   OP_BL,
 629
 630   OP_MOVN,
 631   OP_MOVZ,
 632   OP_MOVK,
 633
 634   OP_MOV_IMM_LOG,       /* MOV alias for moving bitmask immediate.  */
 635   OP_MOV_IMM_WIDE,      /* MOV alias for moving wide immediate.  */
 636   OP_MOV_IMM_WIDEN,     /* MOV alias for moving wide immediate (negated).  */
 637
 638   OP_MOV_V,             /* MOV alias for moving vector register.  */
 639
 640   OP_ASR_IMM,
 641   OP_LSR_IMM,
 642   OP_LSL_IMM,
 643
 644   OP_BIC,
 645
 646   OP_UBFX,
 647   OP_BFXIL,
 648   OP_SBFX,
 649   OP_SBFIZ,
 650   OP_BFI,
 651   OP_BFC,               /* ARMv8.2.  */
 652   OP_UBFIZ,
 653   OP_UXTB,
 654   OP_UXTH,
 655   OP_UXTW,
 656
 657   OP_CINC,
 658   OP_CINV,
 659   OP_CNEG,
 660   OP_CSET,
 661   OP_CSETM,
 662
 663   OP_FCVT,
 664   OP_FCVTN,
 665   OP_FCVTN2,
 666   OP_FCVTL,
 667   OP_FCVTL2,
 668   OP_FCVTXN_S,          /* Scalar version.  */
 669
 670   OP_ROR_IMM,
 671
 672   OP_SXTL,
 673   OP_SXTL2,
 674   OP_UXTL,
 675   OP_UXTL2,
 676
 677   OP_MOV_P_P,
 678   OP_MOV_Z_P_Z,
 679   OP_MOV_Z_V,
 680   OP_MOV_Z_Z,
 681   OP_MOV_Z_Zi,
 682   OP_MOVM_P_P_P,
 683   OP_MOVS_P_P,
 684   OP_MOVZS_P_P_P,
 685   OP_MOVZ_P_P_P,
 686   OP_NOTS_P_P_P_Z,
 687   OP_NOT_P_P_P_Z,
 688
 689   OP_FCMLA_ELEM,        /* ARMv8.3, indexed element version.  */
 690
 691   OP_TOTAL_NUM,         /* Pseudo.  */
 692 };
 693
 694 /* Error types.  */
 695 enum err_type
 696 {
 697   ERR_OK,
 698   ERR_UND,
 699   ERR_UNP,
 700   ERR_NYI,
 701   ERR_VFI,
 702   ERR_NR_ENTRIES
 703 };
 704
 705 /* Maximum number of operands an instruction can have.  */
 706 #define AARCH64_MAX_OPND_NUM 6
 707 /* Maximum number of qualifier sequences an instruction can have.  */
 708 #define AARCH64_MAX_QLF_SEQ_NUM 10
 709 /* Operand qualifier typedef; optimized for the size.  */
 710 typedef unsigned char aarch64_opnd_qualifier_t;
 711 /* Operand qualifier sequence typedef.  */
 712 typedef aarch64_opnd_qualifier_t        \
 713           aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
 714
 715 /* FIXME: improve the efficiency.  */
 716 static inline bfd_boolean
 717 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
 718 {
 719   int i;
 720   for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
 721     if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
 722       return FALSE;
 723   return TRUE;
 724 }
 725
 726 /*  Forward declare error reporting type.  */
 727 typedef struct aarch64_operand_error aarch64_operand_error;
 728 /* Forward declare instruction sequence type.  */
 729 typedef struct aarch64_instr_sequence aarch64_instr_sequence;
 730 /* Forward declare instruction definition.  */
 731 typedef struct aarch64_inst aarch64_inst;
 732
 733 /* This structure holds information for a particular opcode.  */
 734
 735 struct aarch64_opcode
 736 {
 737   /* The name of the mnemonic.  */
 738   const char *name;
 739
 740   /* The opcode itself.  Those bits which will be filled in with
 741      operands are zeroes.  */
 742   aarch64_insn opcode;
 743
 744   /* The opcode mask.  This is used by the disassembler.  This is a
 745      mask containing ones indicating those bits which must match the
 746      opcode field, and zeroes indicating those bits which need not
 747      match (and are presumably filled in by operands).  */
 748   aarch64_insn mask;
 749
 750   /* Instruction class.  */
 751   enum aarch64_insn_class iclass;
 752
 753   /* Enumerator identifier.  */
 754   enum aarch64_op op;
 755
 756   /* Which architecture variant provides this instruction.  */
 757   const aarch64_feature_set *avariant;
 758
 759   /* An array of operand codes.  Each code is an index into the
 760      operand table.  They appear in the order which the operands must
 761      appear in assembly code, and are terminated by a zero.  */
 762   enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
 763
 764   /* A list of operand qualifier code sequence.  Each operand qualifier
 765      code qualifies the corresponding operand code.  Each operand
 766      qualifier sequence specifies a valid opcode variant and related
 767      constraint on operands.  */
 768   aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
 769
 770   /* Flags providing information about this instruction */
 771   uint64_t flags;
 772
 773   /* Extra constraints on the instruction that the verifier checks.  */
 774   uint32_t constraints;
 775
 776   /* If nonzero, this operand and operand 0 are both registers and
 777      are required to have the same register number.  */
 778   unsigned char tied_operand;
 779
 780   /* If non-NULL, a function to verify that a given instruction is valid.  */
 781   enum err_type (* verifier) (const struct aarch64_inst *, const aarch64_insn,
 782                               bfd_vma, bfd_boolean, aarch64_operand_error *,
 783                               struct aarch64_instr_sequence *);
 784 };
 785
 786 typedef struct aarch64_opcode aarch64_opcode;
 787
 788 /* Table describing all the AArch64 opcodes.  */
 789 extern aarch64_opcode aarch64_opcode_table[];
 790
 791 /* Opcode flags.  */
 792 #define F_ALIAS (1 << 0)
 793 #define F_HAS_ALIAS (1 << 1)
 794 /* Disassembly preference priority 1-3 (the larger the higher).  If nothing
 795    is specified, it is the priority 0 by default, i.e. the lowest priority.  */
 796 #define F_P1 (1 << 2)
 797 #define F_P2 (2 << 2)
 798 #define F_P3 (3 << 2)
 799 /* Flag an instruction that is truly conditional executed, e.g. b.cond.  */
 800 #define F_COND (1 << 4)
 801 /* Instruction has the field of 'sf'.  */
 802 #define F_SF (1 << 5)
 803 /* Instruction has the field of 'size:Q'.  */
 804 #define F_SIZEQ (1 << 6)
 805 /* Floating-point instruction has the field of 'type'.  */
 806 #define F_FPTYPE (1 << 7)
 807 /* AdvSIMD scalar instruction has the field of 'size'.  */
 808 #define F_SSIZE (1 << 8)
 809 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q".  */
 810 #define F_T (1 << 9)
 811 /* Size of GPR operand in AdvSIMD instructions encoded in Q.  */
 812 #define F_GPRSIZE_IN_Q (1 << 10)
 813 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22.  */
 814 #define F_LDS_SIZE (1 << 11)
 815 /* Optional operand; assume maximum of 1 operand can be optional.  */
 816 #define F_OPD0_OPT (1 << 12)
 817 #define F_OPD1_OPT (2 << 12)
 818 #define F_OPD2_OPT (3 << 12)
 819 #define F_OPD3_OPT (4 << 12)
 820 #define F_OPD4_OPT (5 << 12)
 821 /* Default value for the optional operand when omitted from the assembly.  */
 822 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
 823 /* Instruction that is an alias of another instruction needs to be
 824    encoded/decoded by converting it to/from the real form, followed by
 825    the encoding/decoding according to the rules of the real opcode.
 826    This compares to the direct coding using the alias's information.
 827    N.B. this flag requires F_ALIAS to be used together.  */
 828 #define F_CONV (1 << 20)
 829 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
 830    friendly pseudo instruction available only in the assembly code (thus will
 831    not show up in the disassembly).  */
 832 #define F_PSEUDO (1 << 21)
 833 /* Instruction has miscellaneous encoding/decoding rules.  */
 834 #define F_MISC (1 << 22)
 835 /* Instruction has the field of 'N'; used in conjunction with F_SF.  */
 836 #define F_N (1 << 23)
 837 /* Opcode dependent field.  */
 838 #define F_OD(X) (((X) & 0x7) << 24)
 839 /* Instruction has the field of 'sz'.  */
 840 #define F_LSE_SZ (1 << 27)
 841 /* Require an exact qualifier match, even for NIL qualifiers.  */
 842 #define F_STRICT (1ULL << 28)
 843 /* This system instruction is used to read system registers.  */
 844 #define F_SYS_READ (1ULL << 29)
 845 /* This system instruction is used to write system registers.  */
 846 #define F_SYS_WRITE (1ULL << 30)
 847 /* This instruction has an extra constraint on it that imposes a requirement on
 848    subsequent instructions.  */
 849 #define F_SCAN (1ULL << 31)
 850 /* Next bit is 32.  */
 851
 852 /* Instruction constraints.  */
 853 /* This instruction has a predication constraint on the instruction at PC+4.  */
 854 #define C_SCAN_MOVPRFX (1U << 0)
 855 /* This instruction's operation width is determined by the operand with the
 856    largest element size.  */
 857 #define C_MAX_ELEM (1U << 1)
 858 /* Next bit is 2.  */
 859
 860 static inline bfd_boolean
 861 alias_opcode_p (const aarch64_opcode *opcode)
 862 {
 863   return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
 864 }
 865
 866 static inline bfd_boolean
 867 opcode_has_alias (const aarch64_opcode *opcode)
 868 {
 869   return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
 870 }
 871
 872 /* Priority for disassembling preference.  */
 873 static inline int
 874 opcode_priority (const aarch64_opcode *opcode)
 875 {
 876   return (opcode->flags >> 2) & 0x3;
 877 }
 878
 879 static inline bfd_boolean
 880 pseudo_opcode_p (const aarch64_opcode *opcode)
 881 {
 882   return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
 883 }
 884
 885 static inline bfd_boolean
 886 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
 887 {
 888   return (((opcode->flags >> 12) & 0x7) == idx + 1)
 889     ? TRUE : FALSE;
 890 }
 891
 892 static inline aarch64_insn
 893 get_optional_operand_default_value (const aarch64_opcode *opcode)
 894 {
 895   return (opcode->flags >> 15) & 0x1f;
 896 }
 897
 898 static inline unsigned int
 899 get_opcode_dependent_value (const aarch64_opcode *opcode)
 900 {
 901   return (opcode->flags >> 24) & 0x7;
 902 }
 903
 904 static inline bfd_boolean
 905 opcode_has_special_coder (const aarch64_opcode *opcode)
 906 {
 907   return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
 908           | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
 909     : FALSE;
 910 }
 911 \f
 912 struct aarch64_name_value_pair
 913 {
 914   const char *  name;
 915   aarch64_insn  value;
 916 };
 917
 918 extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
 919 extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
 920 extern const struct aarch64_name_value_pair aarch64_prfops [32];
 921 extern const struct aarch64_name_value_pair aarch64_hint_options [];
 922
 923 typedef struct
 924 {
 925   const char *  name;
 926   aarch64_insn  value;
 927   uint32_t      flags;
 928 } aarch64_sys_reg;
 929
 930 extern const aarch64_sys_reg aarch64_sys_regs [];
 931 extern const aarch64_sys_reg aarch64_pstatefields [];
 932 extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
 933 extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
 934                                                 const aarch64_sys_reg *);
 935 extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
 936                                                     const aarch64_sys_reg *);
 937
 938 typedef struct
 939 {
 940   const char *name;
 941   uint32_t value;
 942   uint32_t flags ;
 943 } aarch64_sys_ins_reg;
 944
 945 extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
 946 extern bfd_boolean
 947 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
 948                                  const aarch64_sys_ins_reg *);
 949
 950 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
 951 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
 952 extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
 953 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
 954 extern const aarch64_sys_ins_reg aarch64_sys_regs_sr [];
 955
 956 /* Shift/extending operator kinds.
 957    N.B. order is important; keep aarch64_operand_modifiers synced.  */
 958 enum aarch64_modifier_kind
 959 {
 960   AARCH64_MOD_NONE,
 961   AARCH64_MOD_MSL,
 962   AARCH64_MOD_ROR,
 963   AARCH64_MOD_ASR,
 964   AARCH64_MOD_LSR,
 965   AARCH64_MOD_LSL,
 966   AARCH64_MOD_UXTB,
 967   AARCH64_MOD_UXTH,
 968   AARCH64_MOD_UXTW,
 969   AARCH64_MOD_UXTX,
 970   AARCH64_MOD_SXTB,
 971   AARCH64_MOD_SXTH,
 972   AARCH64_MOD_SXTW,
 973   AARCH64_MOD_SXTX,
 974   AARCH64_MOD_MUL,
 975   AARCH64_MOD_MUL_VL,
 976 };
 977
 978 bfd_boolean
 979 aarch64_extend_operator_p (enum aarch64_modifier_kind);
 980
 981 enum aarch64_modifier_kind
 982 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
 983 /* Condition.  */
 984
 985 typedef struct
 986 {
 987   /* A list of names with the first one as the disassembly preference;
 988      terminated by NULL if fewer than 3.  */
 989   const char *names[4];
 990   aarch64_insn value;
 991 } aarch64_cond;
 992
 993 extern const aarch64_cond aarch64_conds[16];
 994
 995 const aarch64_cond* get_cond_from_value (aarch64_insn value);
 996 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
 997 \f
 998 /* Structure representing an operand.  */
 999
1000 struct aarch64_opnd_info
1001 {
1002   enum aarch64_opnd type;
1003   aarch64_opnd_qualifier_t qualifier;
1004   int idx;
1005
1006   union
1007     {
1008       struct
1009         {
1010           unsigned regno;
1011         } reg;
1012       struct
1013         {
1014           unsigned int regno;
1015           int64_t index;
1016         } reglane;
1017       /* e.g. LVn.  */
1018       struct
1019         {
1020           unsigned first_regno : 5;
1021           unsigned num_regs : 3;
1022           /* 1 if it is a list of reg element.  */
1023           unsigned has_index : 1;
1024           /* Lane index; valid only when has_index is 1.  */
1025           int64_t index;
1026         } reglist;
1027       /* e.g. immediate or pc relative address offset.  */
1028       struct
1029         {
1030           int64_t value;
1031           unsigned is_fp : 1;
1032         } imm;
1033       /* e.g. address in STR (register offset).  */
1034       struct
1035         {
1036           unsigned base_regno;
1037           struct
1038             {
1039               union
1040                 {
1041                   int imm;
1042                   unsigned regno;
1043                 };
1044               unsigned is_reg;
1045             } offset;
1046           unsigned pcrel : 1;           /* PC-relative.  */
1047           unsigned writeback : 1;
1048           unsigned preind : 1;          /* Pre-indexed.  */
1049           unsigned postind : 1;         /* Post-indexed.  */
1050         } addr;
1051
1052       struct
1053         {
1054           /* The encoding of the system register.  */
1055           aarch64_insn value;
1056
1057           /* The system register flags.  */
1058           uint32_t flags;
1059         } sysreg;
1060
1061       const aarch64_cond *cond;
1062       /* The encoding of the PSTATE field.  */
1063       aarch64_insn pstatefield;
1064       const aarch64_sys_ins_reg *sysins_op;
1065       const struct aarch64_name_value_pair *barrier;
1066       const struct aarch64_name_value_pair *hint_option;
1067       const struct aarch64_name_value_pair *prfop;
1068     };
1069
1070   /* Operand shifter; in use when the operand is a register offset address,
1071      add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}.  */
1072   struct
1073     {
1074       enum aarch64_modifier_kind kind;
1075       unsigned operator_present: 1;     /* Only valid during encoding.  */
1076       /* Value of the 'S' field in ld/st reg offset; used only in decoding.  */
1077       unsigned amount_present: 1;
1078       int64_t amount;
1079     } shifter;
1080
1081   unsigned skip:1;      /* Operand is not completed if there is a fixup needed
1082                            to be done on it.  In some (but not all) of these
1083                            cases, we need to tell libopcodes to skip the
1084                            constraint checking and the encoding for this
1085                            operand, so that the libopcodes can pick up the
1086                            right opcode before the operand is fixed-up.  This
1087                            flag should only be used during the
1088                            assembling/encoding.  */
1089   unsigned present:1;   /* Whether this operand is present in the assembly
1090                            line; not used during the disassembly.  */
1091 };
1092
1093 typedef struct aarch64_opnd_info aarch64_opnd_info;
1094
1095 /* Structure representing an instruction.
1096
1097    It is used during both the assembling and disassembling.  The assembler
1098    fills an aarch64_inst after a successful parsing and then passes it to the
1099    encoding routine to do the encoding.  During the disassembling, the
1100    disassembler calls the decoding routine to decode a binary instruction; on a
1101    successful return, such a structure will be filled with information of the
1102    instruction; then the disassembler uses the information to print out the
1103    instruction.  */
1104
1105 struct aarch64_inst
1106 {
1107   /* The value of the binary instruction.  */
1108   aarch64_insn value;
1109
1110   /* Corresponding opcode entry.  */
1111   const aarch64_opcode *opcode;
1112
1113   /* Condition for a truly conditional-executed instrutions, e.g. b.cond.  */
1114   const aarch64_cond *cond;
1115
1116   /* Operands information.  */
1117   aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
1118 };
1119
1120 /* Defining the HINT #imm values for the aarch64_hint_options.  */
1121 #define HINT_OPD_CSYNC  0x11
1122 #define HINT_OPD_C      0x22
1123 #define HINT_OPD_J      0x24
1124 #define HINT_OPD_JC     0x26
1125 #define HINT_OPD_NULL   0x00
1126
1127 \f
1128 /* Diagnosis related declaration and interface.  */
1129
1130 /* Operand error kind enumerators.
1131
1132    AARCH64_OPDE_RECOVERABLE
1133      Less severe error found during the parsing, very possibly because that
1134      GAS has picked up a wrong instruction template for the parsing.
1135
1136    AARCH64_OPDE_SYNTAX_ERROR
1137      General syntax error; it can be either a user error, or simply because
1138      that GAS is trying a wrong instruction template.
1139
1140    AARCH64_OPDE_FATAL_SYNTAX_ERROR
1141      Definitely a user syntax error.
1142
1143    AARCH64_OPDE_INVALID_VARIANT
1144      No syntax error, but the operands are not a valid combination, e.g.
1145      FMOV D0,S0
1146
1147    AARCH64_OPDE_UNTIED_OPERAND
1148      The asm failed to use the same register for a destination operand
1149      and a tied source operand.
1150
1151    AARCH64_OPDE_OUT_OF_RANGE
1152      Error about some immediate value out of a valid range.
1153
1154    AARCH64_OPDE_UNALIGNED
1155      Error about some immediate value not properly aligned (i.e. not being a
1156      multiple times of a certain value).
1157
1158    AARCH64_OPDE_REG_LIST
1159      Error about the register list operand having unexpected number of
1160      registers.
1161
1162    AARCH64_OPDE_OTHER_ERROR
1163      Error of the highest severity and used for any severe issue that does not
1164      fall into any of the above categories.
1165
1166    The enumerators are only interesting to GAS.  They are declared here (in
1167    libopcodes) because that some errors are detected (and then notified to GAS)
1168    by libopcodes (rather than by GAS solely).
1169
1170    The first three errors are only deteced by GAS while the
1171    AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1172    only libopcodes has the information about the valid variants of each
1173    instruction.
1174
1175    The enumerators have an increasing severity.  This is helpful when there are
1176    multiple instruction templates available for a given mnemonic name (e.g.
1177    FMOV); this mechanism will help choose the most suitable template from which
1178    the generated diagnostics can most closely describe the issues, if any.  */
1179
1180 enum aarch64_operand_error_kind
1181 {
1182   AARCH64_OPDE_NIL,
1183   AARCH64_OPDE_RECOVERABLE,
1184   AARCH64_OPDE_SYNTAX_ERROR,
1185   AARCH64_OPDE_FATAL_SYNTAX_ERROR,
1186   AARCH64_OPDE_INVALID_VARIANT,
1187   AARCH64_OPDE_UNTIED_OPERAND,
1188   AARCH64_OPDE_OUT_OF_RANGE,
1189   AARCH64_OPDE_UNALIGNED,
1190   AARCH64_OPDE_REG_LIST,
1191   AARCH64_OPDE_OTHER_ERROR
1192 };
1193
1194 /* N.B. GAS assumes that this structure work well with shallow copy.  */
1195 struct aarch64_operand_error
1196 {
1197   enum aarch64_operand_error_kind kind;
1198   int index;
1199   const char *error;
1200   int data[3];  /* Some data for extra information.  */
1201   bfd_boolean non_fatal;
1202 };
1203
1204 /* AArch64 sequence structure used to track instructions with F_SCAN
1205    dependencies for both assembler and disassembler.  */
1206 struct aarch64_instr_sequence
1207 {
1208   /* The instruction that caused this sequence to be opened.  */
1209   aarch64_inst *instr;
1210   /* The number of instructions the above instruction allows to be kept in the
1211      sequence before an automatic close is done.  */
1212   int num_insns;
1213   /* The instructions currently added to the sequence.  */
1214   aarch64_inst **current_insns;
1215   /* The number of instructions already in the sequence.  */
1216   int next_insn;
1217 };
1218
1219 /* Encoding entrypoint.  */
1220
1221 extern int
1222 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1223                        aarch64_insn *, aarch64_opnd_qualifier_t *,
1224                        aarch64_operand_error *, aarch64_instr_sequence *);
1225
1226 extern const aarch64_opcode *
1227 aarch64_replace_opcode (struct aarch64_inst *,
1228                         const aarch64_opcode *);
1229
1230 /* Given the opcode enumerator OP, return the pointer to the corresponding
1231    opcode entry.  */
1232
1233 extern const aarch64_opcode *
1234 aarch64_get_opcode (enum aarch64_op);
1235
1236 /* Generate the string representation of an operand.  */
1237 extern void
1238 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
1239                        const aarch64_opnd_info *, int, int *, bfd_vma *,
1240                        char **);
1241
1242 /* Miscellaneous interface.  */
1243
1244 extern int
1245 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1246
1247 extern aarch64_opnd_qualifier_t
1248 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1249                                 const aarch64_opnd_qualifier_t, int);
1250
1251 extern bfd_boolean
1252 aarch64_is_destructive_by_operands (const aarch64_opcode *);
1253
1254 extern int
1255 aarch64_num_of_operands (const aarch64_opcode *);
1256
1257 extern int
1258 aarch64_stack_pointer_p (const aarch64_opnd_info *);
1259
1260 extern int
1261 aarch64_zero_register_p (const aarch64_opnd_info *);
1262
1263 extern enum err_type
1264 aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean,
1265                      aarch64_operand_error *);
1266
1267 extern void
1268 init_insn_sequence (const struct aarch64_inst *, aarch64_instr_sequence *);
1269
1270 /* Given an operand qualifier, return the expected data element size
1271    of a qualified operand.  */
1272 extern unsigned char
1273 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1274
1275 extern enum aarch64_operand_class
1276 aarch64_get_operand_class (enum aarch64_opnd);
1277
1278 extern const char *
1279 aarch64_get_operand_name (enum aarch64_opnd);
1280
1281 extern const char *
1282 aarch64_get_operand_desc (enum aarch64_opnd);
1283
1284 extern bfd_boolean
1285 aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1286
1287 #ifdef DEBUG_AARCH64
1288 extern int debug_dump;
1289
1290 extern void
1291 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1292
1293 #define DEBUG_TRACE(M, ...)                                     \
1294   {                                                             \
1295     if (debug_dump)                                             \
1296       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1297   }
1298
1299 #define DEBUG_TRACE_IF(C, M, ...)                               \
1300   {                                                             \
1301     if (debug_dump && (C))                                      \
1302       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1303   }
1304 #else  /* !DEBUG_AARCH64 */
1305 #define DEBUG_TRACE(M, ...) ;
1306 #define DEBUG_TRACE_IF(C, M, ...) ;
1307 #endif /* DEBUG_AARCH64 */
1308
1309 extern const char *const aarch64_sve_pattern_array[32];
1310 extern const char *const aarch64_sve_prfop_array[16];
1311
1312 #ifdef __cplusplus
1313 }
1314 #endif
1315
1316 #endif /* OPCODE_AARCH64_H */