1 /* mips.h. Mips opcode list for GDB, the GNU debugger.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2008, 2009, 2010, 2013
4 Free Software Foundation, Inc.
5 Contributed by Ralph Campbell and OSF
6 Commented and modified by Ian Lance Taylor, Cygnus Support
8 This file is part of GDB, GAS, and the GNU binutils.
10 GDB, GAS, and the GNU binutils are free software; you can redistribute
11 them and/or modify them under the terms of the GNU General Public
12 License as published by the Free Software Foundation; either version 3,
13 or (at your option) any later version.
15 GDB, GAS, and the GNU binutils are distributed in the hope that they
16 will be useful, but WITHOUT ANY WARRANTY; without even the implied
17 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
18 the GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this file; see the file COPYING3. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
23 MA 02110-1301, USA. */
30 /* These are bit masks and shift counts to use to access the various
31 fields of an instruction. To retrieve the X field of an
32 instruction, use the expression
33 (i >> OP_SH_X) & OP_MASK_X
34 To set the same field (to j), use
35 i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
37 Make sure you use fields that are appropriate for the instruction,
40 The 'i' format uses OP, RS, RT and IMMEDIATE.
42 The 'j' format uses OP and TARGET.
44 The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
46 The 'b' format uses OP, RS, RT and DELTA.
48 The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
50 The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
52 A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
53 breakpoint instruction are not defined; Kane says the breakpoint
54 code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
55 only use ten bits). An optional two-operand form of break/sdbbp
56 allows the lower ten bits to be set too, and MIPS32 and later
57 architectures allow 20 bits to be set with a signal operand
60 The syscall instruction uses CODE20.
62 The general coprocessor instructions use COPZ. */
64 #define OP_MASK_OP 0x3f
66 #define OP_MASK_RS 0x1f
68 #define OP_MASK_FR 0x1f
70 #define OP_MASK_FMT 0x1f
72 #define OP_MASK_BCC 0x7
74 #define OP_MASK_CODE 0x3ff
76 #define OP_MASK_CODE2 0x3ff
78 #define OP_MASK_RT 0x1f
80 #define OP_MASK_FT 0x1f
82 #define OP_MASK_CACHE 0x1f
83 #define OP_SH_CACHE 16
84 #define OP_MASK_RD 0x1f
86 #define OP_MASK_FS 0x1f
88 #define OP_MASK_PREFX 0x1f
89 #define OP_SH_PREFX 11
90 #define OP_MASK_CCC 0x7
92 #define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */
93 #define OP_SH_CODE20 6
94 #define OP_MASK_SHAMT 0x1f
96 #define OP_MASK_EXTLSB OP_MASK_SHAMT
97 #define OP_SH_EXTLSB OP_SH_SHAMT
98 #define OP_MASK_STYPE OP_MASK_SHAMT
99 #define OP_SH_STYPE OP_SH_SHAMT
100 #define OP_MASK_FD 0x1f
102 #define OP_MASK_TARGET 0x3ffffff
103 #define OP_SH_TARGET 0
104 #define OP_MASK_COPZ 0x1ffffff
106 #define OP_MASK_IMMEDIATE 0xffff
107 #define OP_SH_IMMEDIATE 0
108 #define OP_MASK_DELTA 0xffff
109 #define OP_SH_DELTA 0
110 #define OP_MASK_FUNCT 0x3f
111 #define OP_SH_FUNCT 0
112 #define OP_MASK_SPEC 0x3f
114 #define OP_SH_LOCC 8 /* FP condition code. */
115 #define OP_SH_HICC 18 /* FP condition code. */
116 #define OP_MASK_CC 0x7
117 #define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */
118 #define OP_MASK_COP1NORM 0x1 /* a single bit. */
119 #define OP_SH_COP1SPEC 21 /* COP1 encodings. */
120 #define OP_MASK_COP1SPEC 0xf
121 #define OP_MASK_COP1SCLR 0x4
122 #define OP_MASK_COP1CMP 0x3
123 #define OP_SH_COP1CMP 4
124 #define OP_SH_FORMAT 21 /* FP short format field. */
125 #define OP_MASK_FORMAT 0x7
126 #define OP_SH_TRUE 16
127 #define OP_MASK_TRUE 0x1
129 #define OP_MASK_GE 0x01
130 #define OP_SH_UNSIGNED 16
131 #define OP_MASK_UNSIGNED 0x1
132 #define OP_SH_HINT 16
133 #define OP_MASK_HINT 0x1f
134 #define OP_SH_MMI 0 /* Multimedia (parallel) op. */
135 #define OP_MASK_MMI 0x3f
136 #define OP_SH_MMISUB 6
137 #define OP_MASK_MMISUB 0x1f
138 #define OP_MASK_PERFREG 0x1f /* Performance monitoring. */
139 #define OP_SH_PERFREG 1
140 #define OP_SH_SEL 0 /* Coprocessor select field. */
141 #define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */
142 #define OP_SH_CODE19 6 /* 19 bit wait code. */
143 #define OP_MASK_CODE19 0x7ffff
145 #define OP_MASK_ALN 0x7
146 #define OP_SH_VSEL 21
147 #define OP_MASK_VSEL 0x1f
148 #define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits,
149 but 0x8-0xf don't select bytes. */
150 #define OP_SH_VECBYTE 22
151 #define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */
152 #define OP_SH_VECALIGN 21
153 #define OP_MASK_INSMSB 0x1f /* "ins" MSB. */
154 #define OP_SH_INSMSB 11
155 #define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */
156 #define OP_SH_EXTMSBD 11
159 #define OP_SH_DSPACC 11
160 #define OP_MASK_DSPACC 0x3
161 #define OP_SH_DSPACC_S 21
162 #define OP_MASK_DSPACC_S 0x3
163 #define OP_SH_DSPSFT 20
164 #define OP_MASK_DSPSFT 0x3f
165 #define OP_SH_DSPSFT_7 19
166 #define OP_MASK_DSPSFT_7 0x7f
168 #define OP_MASK_SA3 0x7
170 #define OP_MASK_SA4 0xf
171 #define OP_SH_IMM8 16
172 #define OP_MASK_IMM8 0xff
173 #define OP_SH_IMM10 16
174 #define OP_MASK_IMM10 0x3ff
175 #define OP_SH_WRDSP 11
176 #define OP_MASK_WRDSP 0x3f
177 #define OP_SH_RDDSP 16
178 #define OP_MASK_RDDSP 0x3f
180 #define OP_MASK_BP 0x3
184 #define OP_MASK_MT_U 0x1
186 #define OP_MASK_MT_H 0x1
187 #define OP_SH_MTACC_T 18
188 #define OP_MASK_MTACC_T 0x3
189 #define OP_SH_MTACC_D 13
190 #define OP_MASK_MTACC_D 0x3
193 #define OP_MASK_3BITPOS 0x7
194 #define OP_SH_3BITPOS 12
195 #define OP_MASK_OFFSET12 0xfff
196 #define OP_SH_OFFSET12 0
198 #define OP_OP_COP0 0x10
199 #define OP_OP_COP1 0x11
200 #define OP_OP_COP2 0x12
201 #define OP_OP_COP3 0x13
202 #define OP_OP_LWC1 0x31
203 #define OP_OP_LWC2 0x32
204 #define OP_OP_LWC3 0x33 /* a.k.a. pref */
205 #define OP_OP_LDC1 0x35
206 #define OP_OP_LDC2 0x36
207 #define OP_OP_LDC3 0x37 /* a.k.a. ld */
208 #define OP_OP_SWC1 0x39
209 #define OP_OP_SWC2 0x3a
210 #define OP_OP_SWC3 0x3b
211 #define OP_OP_SDC1 0x3d
212 #define OP_OP_SDC2 0x3e
213 #define OP_OP_SDC3 0x3f /* a.k.a. sd */
216 #define OP_MASK_CODE10 0x3ff
217 #define OP_SH_CODE10 11
219 /* Values in the 'VSEL' field. */
220 #define MDMX_FMTSEL_IMM_QH 0x1d
221 #define MDMX_FMTSEL_IMM_OB 0x1e
222 #define MDMX_FMTSEL_VEC_QH 0x15
223 #define MDMX_FMTSEL_VEC_OB 0x16
227 #define OP_MASK_UDI1 0x1f
229 #define OP_MASK_UDI2 0x3ff
231 #define OP_MASK_UDI3 0x7fff
233 #define OP_MASK_UDI4 0xfffff
236 #define OP_SH_BBITIND 16
237 #define OP_MASK_BBITIND 0x1f
238 #define OP_SH_CINSPOS 6
239 #define OP_MASK_CINSPOS 0x1f
240 #define OP_SH_CINSLM1 11
241 #define OP_MASK_CINSLM1 0x1f
243 #define OP_MASK_SEQI 0x3ff
246 #define OP_SH_OFFSET_A 6
247 #define OP_MASK_OFFSET_A 0xff
248 #define OP_SH_OFFSET_B 3
249 #define OP_MASK_OFFSET_B 0xff
250 #define OP_SH_OFFSET_C 6
251 #define OP_MASK_OFFSET_C 0x1ff
253 #define OP_MASK_RZ 0x1f
255 #define OP_MASK_FZ 0x1f
257 /* Every MICROMIPSOP_X definition requires a corresponding OP_X
258 definition, and vice versa. This simplifies various parts
259 of the operand handling in GAS. The fields below only exist
260 in the microMIPS encoding, so define each one to have an empty
262 #define OP_MASK_TRAP 0
264 #define OP_MASK_OFFSET10 0
265 #define OP_SH_OFFSET10 0
266 #define OP_MASK_RS3 0
294 #define OP_MASK_IMMA 0
296 #define OP_MASK_IMMB 0
298 #define OP_MASK_IMMC 0
300 #define OP_MASK_IMMF 0
302 #define OP_MASK_IMMG 0
304 #define OP_MASK_IMMH 0
306 #define OP_MASK_IMMI 0
308 #define OP_MASK_IMMJ 0
310 #define OP_MASK_IMML 0
312 #define OP_MASK_IMMM 0
314 #define OP_MASK_IMMN 0
316 #define OP_MASK_IMMO 0
318 #define OP_MASK_IMMP 0
320 #define OP_MASK_IMMQ 0
322 #define OP_MASK_IMMU 0
324 #define OP_MASK_IMMW 0
326 #define OP_MASK_IMMX 0
328 #define OP_MASK_IMMY 0
331 /* Enhanced VA Scheme */
332 #define OP_SH_EVAOFFSET 7
333 #define OP_MASK_EVAOFFSET 0x1ff
335 /* Enumerates the various types of MIPS operand. */
336 enum mips_operand_type
{
337 /* Described by mips_int_operand. */
340 /* Described by mips_mapped_int_operand. */
343 /* Described by mips_msb_operand. */
346 /* Described by mips_reg_operand. */
349 /* Described by mips_reg_pair_operand. */
352 /* Described by mips_pcrel_operand. */
355 /* A performance register. The field is 5 bits in size, but the supported
356 values are much more restricted. */
359 /* The final operand in a microMIPS ADDIUSP instruction. It mostly acts
360 as a normal 9-bit signed offset that is multiplied by four, but there
361 are four special cases:
369 /* The target of a (D)CLO or (D)CLZ instruction. The operand spans two
370 5-bit register fields, both of which must be set to the destination
374 /* A register list for a microMIPS LWM or SWM instruction. The operand
375 size determines whether the 16-bit or 32-bit encoding is required. */
378 /* The register list for an emulated MIPS16 ENTRY or EXIT instruction. */
381 /* The register list and frame size for a MIPS16 SAVE or RESTORE
383 OP_SAVE_RESTORE_LIST
,
385 /* A 10-bit field VVVVVNNNNN used for octobyte and quadhalf instructions:
389 0EEE0 8 copies of $vN[E], OB format
390 0EE01 4 copies of $vN[E], QH format
391 10110 all 8 elements of $vN, OB format
392 10101 all 4 elements of $vN, QH format
393 11110 8 copies of immediate N, OB format
394 11101 4 copies of immediate N, QH format. */
397 /* A register operand that must match the destination register. */
400 /* A register operand that must match the previous register. */
403 /* $pc, which has no encoding in the architectural instruction. */
406 /* A 4-bit XYZW channel mask or 2-bit XYZW index; the size determines
410 /* Like OP_VU0_SUFFIX, but used when the operand's value has already
411 been set. Any suffix used here must match the previous value. */
415 /* Enumerates the types of MIPS register. */
416 enum mips_reg_operand_type
{
417 /* General registers $0-$31. Software names like $at can also be used. */
420 /* Floating-point registers $f0-$f31. */
423 /* Coprocessor condition code registers $cc0-$cc7. FPU condition codes
424 can also be written $fcc0-$fcc7. */
427 /* FPRs used in a vector capacity. They can be written $f0-$f31
428 or $v0-$v31, although the latter form is not used for the VR5400
429 vector instructions. */
432 /* DSP accumulator registers $ac0-$ac3. */
435 /* Coprocessor registers $0-$31. Mnemonic names like c0_cause can
436 also be used in some contexts. */
439 /* Hardware registers $0-$31. Mnemonic names like hwr_cpunum can
440 also be used in some contexts. */
443 /* Floating-point registers $vf0-$vf31. */
446 /* Integer registers $vi0-$vi31. */
449 /* R5900 VU0 registers $I, $Q, $R and $ACC. */
456 /* Base class for all operands. */
459 /* The type of the operand. */
460 enum mips_operand_type type
;
462 /* The operand occupies SIZE bits of the instruction, starting at LSB. */
467 /* Describes an integer operand with a regular encoding pattern. */
468 struct mips_int_operand
470 struct mips_operand root
;
472 /* The low ROOT.SIZE bits of MAX_VAL encodes (MAX_VAL + BIAS) << SHIFT.
473 The cyclically previous field value encodes 1 << SHIFT less than that,
476 - for { { T, 4, L }, 14, 0, 0 }, field values 0...14 encode themselves,
479 - { { T, 8, L }, 127, 0, 2 } is a normal signed 8-bit operand that is
480 shifted left two places.
482 - { { T, 3, L }, 8, 0, 0 } is a normal unsigned 3-bit operand except
485 - { { ... }, 0, 1, 3 } means that N encodes (N + 1) << 3. */
486 unsigned int max_val
;
490 /* True if the operand should be printed as hex rather than decimal. */
491 bfd_boolean print_hex
;
494 /* Uses a lookup table to describe a small integer operand. */
495 struct mips_mapped_int_operand
497 struct mips_operand root
;
499 /* Maps each encoding value to the integer that it represents. */
502 /* True if the operand should be printed as hex rather than decimal. */
503 bfd_boolean print_hex
;
506 /* An operand that encodes the most significant bit position of a bitfield.
507 Given a bitfield that spans bits [MSB, LSB], some operands of this type
508 encode MSB directly while others encode MSB - LSB. Each operand of this
509 type is preceded by an integer operand that specifies LSB.
511 The assembly form varies between instructions. For some instructions,
512 such as EXT, the operand is written as the bitfield size. For others,
513 such as EXTS, it is written in raw MSB - LSB form. */
514 struct mips_msb_operand
516 struct mips_operand root
;
518 /* The assembly-level operand encoded by a field value of 0. */
521 /* True if the operand encodes MSB directly, false if it encodes
525 /* The maximum value of MSB + 1. */
529 /* Describes a single register operand. */
530 struct mips_reg_operand
532 struct mips_operand root
;
534 /* The type of register. */
535 enum mips_reg_operand_type reg_type
;
537 /* If nonnull, REG_MAP[N] gives the register associated with encoding N,
538 otherwise the encoding is the same as the register number. */
539 const unsigned char *reg_map
;
542 /* Describes an operand that encodes a pair of registers. */
543 struct mips_reg_pair_operand
545 struct mips_operand root
;
547 /* The type of register. */
548 enum mips_reg_operand_type reg_type
;
550 /* Encoding N represents REG1_MAP[N], REG2_MAP[N]. */
551 unsigned char *reg1_map
;
552 unsigned char *reg2_map
;
555 /* Describes an operand that is calculated relative to a base PC.
556 The base PC is usually the address of the following instruction,
557 but the rules for MIPS16 instructions like ADDIUPC are more complicated. */
558 struct mips_pcrel_operand
560 /* Encodes the offset. */
561 struct mips_int_operand root
;
563 /* The low ALIGN_LOG2 bits of the base PC are cleared to give PC',
564 which is then added to the offset encoded by ROOT. */
565 unsigned int align_log2
: 8;
567 /* If INCLUDE_ISA_BIT, the ISA bit of the original base PC is then
568 reinstated. This is true for jumps and branches and false for
569 PC-relative data instructions. */
570 unsigned int include_isa_bit
: 1;
572 /* If FLIP_ISA_BIT, the ISA bit of the result is inverted.
573 This is true for JALX and false otherwise. */
574 unsigned int flip_isa_bit
: 1;
577 /* Return a version of INSN in which the field specified by OPERAND
580 static inline unsigned int
581 mips_insert_operand (const struct mips_operand
*operand
, unsigned int insn
,
586 mask
= (1 << operand
->size
) - 1;
587 insn
&= ~(mask
<< operand
->lsb
);
588 insn
|= (uval
& mask
) << operand
->lsb
;
592 /* Extract OPERAND from instruction INSN. */
594 static inline unsigned int
595 mips_extract_operand (const struct mips_operand
*operand
, unsigned int insn
)
597 return (insn
>> operand
->lsb
) & ((1 << operand
->size
) - 1);
600 /* UVAL is the value encoded by OPERAND. Return it in signed form. */
603 mips_signed_operand (const struct mips_operand
*operand
, unsigned int uval
)
605 unsigned int sign_bit
, mask
;
607 mask
= (1 << operand
->size
) - 1;
608 sign_bit
= 1 << (operand
->size
- 1);
609 return ((uval
+ sign_bit
) & mask
) - sign_bit
;
612 /* Return the integer that OPERAND encodes as UVAL. */
615 mips_decode_int_operand (const struct mips_int_operand
*operand
,
618 uval
|= (operand
->max_val
- uval
) & -(1 << operand
->root
.size
);
619 uval
+= operand
->bias
;
620 uval
<<= operand
->shift
;
624 /* Return the maximum value that can be encoded by OPERAND. */
627 mips_int_operand_max (const struct mips_int_operand
*operand
)
629 return (operand
->max_val
+ operand
->bias
) << operand
->shift
;
632 /* Return the minimum value that can be encoded by OPERAND. */
635 mips_int_operand_min (const struct mips_int_operand
*operand
)
639 mask
= (1 << operand
->root
.size
) - 1;
640 return mips_int_operand_max (operand
) - (mask
<< operand
->shift
);
643 /* Return the register that OPERAND encodes as UVAL. */
646 mips_decode_reg_operand (const struct mips_reg_operand
*operand
,
649 if (operand
->reg_map
)
650 uval
= operand
->reg_map
[uval
];
654 /* PC-relative operand OPERAND has value UVAL and is relative to BASE_PC.
655 Return the address that it encodes. */
657 static inline bfd_vma
658 mips_decode_pcrel_operand (const struct mips_pcrel_operand
*operand
,
659 bfd_vma base_pc
, unsigned int uval
)
663 addr
= base_pc
& -(1 << operand
->align_log2
);
664 addr
+= mips_decode_int_operand (&operand
->root
, uval
);
665 if (operand
->include_isa_bit
)
667 if (operand
->flip_isa_bit
)
672 /* This structure holds information for a particular instruction. */
676 /* The name of the instruction. */
678 /* A string describing the arguments for this instruction. */
680 /* The basic opcode for the instruction. When assembling, this
681 opcode is modified by the arguments to produce the actual opcode
682 that is used. If pinfo is INSN_MACRO, then this is 0. */
684 /* If pinfo is not INSN_MACRO, then this is a bit mask for the
685 relevant portions of the opcode when disassembling. If the
686 actual opcode anded with the match field equals the opcode field,
687 then we have found the correct instruction. If pinfo is
688 INSN_MACRO, then this field is the macro identifier. */
690 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection
691 of bits describing the instruction, notably any relevant hazard
694 /* A collection of additional bits describing the instruction. */
695 unsigned long pinfo2
;
696 /* A collection of bits describing the instruction sets of which this
697 instruction or macro is a member. */
698 unsigned long membership
;
699 /* A collection of bits describing the ASE of which this instruction
700 or macro is a member. */
702 /* A collection of bits describing the instruction sets of which this
703 instruction or macro is not a member. */
704 unsigned long exclusions
;
707 /* These are the characters which may appear in the args field of an
708 instruction. They appear in the order in which the fields appear
709 when the instruction is used. Commas and parentheses in the args
710 string are ignored when assembling, and written into the output
713 Each of these characters corresponds to a mask field defined above.
715 "1" 5 bit sync type (OP_*_STYPE)
716 "<" 5 bit shift amount (OP_*_SHAMT)
717 ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
718 "a" 26 bit target address (OP_*_TARGET)
719 "+i" likewise, but flips bit 0
720 "b" 5 bit base register (OP_*_RS)
721 "c" 10 bit breakpoint code (OP_*_CODE)
722 "d" 5 bit destination register specifier (OP_*_RD)
723 "h" 5 bit prefx hint (OP_*_PREFX)
724 "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
725 "j" 16 bit signed immediate (OP_*_DELTA)
726 "k" 5 bit cache opcode in target register position (OP_*_CACHE)
727 "o" 16 bit signed offset (OP_*_DELTA)
728 "p" 16 bit PC relative branch target address (OP_*_DELTA)
729 "q" 10 bit extra breakpoint code (OP_*_CODE2)
730 "r" 5 bit same register used as both source and target (OP_*_RS)
731 "s" 5 bit source register specifier (OP_*_RS)
732 "t" 5 bit target register (OP_*_RT)
733 "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
734 "v" 5 bit same register used as both source and destination (OP_*_RS)
735 "w" 5 bit same register used as both target and destination (OP_*_RT)
736 "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
737 (used by clo and clz)
738 "C" 25 bit coprocessor function code (OP_*_COPZ)
739 "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
740 "J" 19 bit wait function code (OP_*_CODE19)
741 "x" accept and ignore register name
742 "z" must be zero register
743 "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
744 "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes
745 LSB (OP_*_SHAMT; OP_*_EXTLSB or OP_*_STYPE may be used for
746 microMIPS compatibility).
747 Enforces: 0 <= pos < 32.
748 "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB).
749 Requires that "+A" or "+E" occur first to set position.
750 Enforces: 0 < (pos+size) <= 32.
751 "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD).
752 Requires that "+A" or "+E" occur first to set position.
753 Enforces: 0 < (pos+size) <= 32.
754 (Also used by "dext" w/ different limits, but limits for
755 that are checked by the M_DEXT macro.)
756 "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT).
757 Enforces: 32 <= pos < 64.
758 "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB).
759 Requires that "+A" or "+E" occur first to set position.
760 Enforces: 32 < (pos+size) <= 64.
761 "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
762 Requires that "+A" or "+E" occur first to set position.
763 Enforces: 32 < (pos+size) <= 64.
764 "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD).
765 Requires that "+A" or "+E" occur first to set position.
766 Enforces: 32 < (pos+size) <= 64.
768 Floating point instructions:
769 "D" 5 bit destination register (OP_*_FD)
770 "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
771 "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
772 "S" 5 bit fs source 1 register (OP_*_FS)
773 "T" 5 bit ft source 2 register (OP_*_FT)
774 "R" 5 bit fr source 3 register (OP_*_FR)
775 "V" 5 bit same register used as floating source and destination (OP_*_FS)
776 "W" 5 bit same register used as floating target and destination (OP_*_FT)
778 Coprocessor instructions:
779 "E" 5 bit target register (OP_*_RT)
780 "G" 5 bit destination register (OP_*_RD)
781 "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
782 "P" 5 bit performance-monitor register (OP_*_PERFREG)
783 "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
784 "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
787 "A" General 32 bit expression
788 "I" 32 bit immediate (value placed in imm_expr).
789 "+I" 32 bit immediate (value placed in imm2_expr).
790 "F" 64 bit floating point constant in .rdata
791 "L" 64 bit floating point constant in .lit8
792 "f" 32 bit floating point constant
793 "l" 32 bit floating point constant in .lit4
795 MDMX and VR5400 instruction operands (note that while these use the
796 FP register fields, the MDMX instructions accept both $fN and $vN names
798 "O" alignment offset (OP_*_ALN)
799 "Q" vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
800 "X" destination register (OP_*_FD)
801 "Y" source register (OP_*_FS)
802 "Z" source register (OP_*_FT)
804 R5900 VU0 Macromode instructions:
805 "+5" 5 bit floating point register (FD)
806 "+6" 5 bit floating point register (FS)
807 "+7" 5 bit floating point register (FT)
808 "+8" 5 bit integer register (FD)
809 "+9" 5 bit integer register (FS)
810 "+0" 5 bit integer register (FT)
811 "+K" match an existing 4-bit channel mask starting at bit 21
812 "+L" 2-bit channel index starting at bit 21
813 "+M" 2-bit channel index starting at bit 23
814 "+N" match an existing 2-bit channel index starting at bit 0
815 "+f" 15 bit immediate for VCALLMS
816 "+g" 5 bit signed immediate for VIADDI
817 "+m" $ACC register (syntax only)
818 "+q" $Q register (syntax only)
819 "+r" $R register (syntax only)
820 "+y" $I register (syntax only)
821 "#+" "++" decorator in ($reg++) sequence
822 "#-" "--" decorator in (--$reg) sequence
825 "2" 2 bit unsigned immediate for byte align (OP_*_BP)
826 "3" 3 bit unsigned immediate (OP_*_SA3)
827 "4" 4 bit unsigned immediate (OP_*_SA4)
828 "5" 8 bit unsigned immediate (OP_*_IMM8)
829 "6" 5 bit unsigned immediate (OP_*_RS)
830 "7" 2 bit dsp accumulator register (OP_*_DSPACC)
831 "8" 6 bit unsigned immediate (OP_*_WRDSP)
832 "9" 2 bit dsp accumulator register (OP_*_DSPACC_S)
833 "0" 6 bit signed immediate (OP_*_DSPSFT)
834 ":" 7 bit signed immediate (OP_*_DSPSFT_7)
835 "'" 6 bit unsigned immediate (OP_*_RDDSP)
836 "@" 10 bit signed immediate (OP_*_IMM10)
839 "!" 1 bit usermode flag (OP_*_MT_U)
840 "$" 1 bit load high flag (OP_*_MT_H)
841 "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
842 "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
843 "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
844 "+t" 5 bit coprocessor 0 destination register (OP_*_RT)
847 "~" 12 bit offset (OP_*_OFFSET12)
848 "\" 3 bit position for aset and aclr (OP_*_3BITPOS)
851 "+J" 10-bit hypcall code (OP_*CODE10)
854 "+1" UDI immediate bits 6-10
855 "+2" UDI immediate bits 6-15
856 "+3" UDI immediate bits 6-20
857 "+4" UDI immediate bits 6-25
860 "+x" Bit index field of bbit. Enforces: 0 <= index < 32.
861 "+X" Bit index field of bbit aliasing bbit32. Matches if 32 <= index < 64,
862 otherwise skips to next candidate.
863 "+p" Position field of cins/cins32/exts/exts32. Enforces 0 <= pos < 32.
864 "+P" Position field of cins/exts aliasing cins32/exts32. Matches if
865 32 <= pos < 64, otherwise skips to next candidate.
866 "+Q" Immediate field of seqi/snei. Enforces -512 <= imm < 512.
867 "+s" Length-minus-one field of cins32/exts32. Requires msb position
868 of the field to be <= 31.
869 "+S" Length-minus-one field of cins/exts. Requires msb position
870 of the field to be <= 63.
873 "+a" 8-bit signed offset in bit 6 (OP_*_OFFSET_A)
874 "+b" 8-bit signed offset in bit 3 (OP_*_OFFSET_B)
875 "+c" 9-bit signed offset in bit 6 (OP_*_OFFSET_C)
876 "+z" 5-bit rz register (OP_*_RZ)
877 "+Z" 5-bit fz register (OP_*_FZ)
880 "+j" 9-bit signed offset in bit 7 (OP_*_EVAOFFSET)
883 "()" parens surrounding optional value
884 "," separates operands
885 "+" Start of extension sequence.
887 Characters used so far, for quick reference when adding more:
889 "%[]<>(),+:'@!#$*&\~"
890 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
891 "abcdefghijklopqrstuvwxz"
893 Extension character sequences used so far ("+" followed by the
894 following), for quick reference when adding more:
900 /* These are the bits which may be set in the pinfo field of an
901 instructions, if it is not equal to INSN_MACRO. */
903 /* Writes to operand number N. */
904 #define INSN_WRITE_SHIFT 0
905 #define INSN_WRITE_1 0x00000001
906 #define INSN_WRITE_2 0x00000002
907 #define INSN_WRITE_ALL 0x00000003
908 /* Reads from operand number N. */
909 #define INSN_READ_SHIFT 2
910 #define INSN_READ_1 0x00000004
911 #define INSN_READ_2 0x00000008
912 #define INSN_READ_3 0x00000010
913 #define INSN_READ_4 0x00000020
914 #define INSN_READ_ALL 0x0000003c
915 /* Modifies general purpose register 31. */
916 #define INSN_WRITE_GPR_31 0x00000040
917 /* Modifies coprocessor condition code. */
918 #define INSN_WRITE_COND_CODE 0x00000080
919 /* Reads coprocessor condition code. */
920 #define INSN_READ_COND_CODE 0x00000100
922 #define INSN_TLB 0x00000200
923 /* Reads coprocessor register other than floating point register. */
924 #define INSN_COP 0x00000400
925 /* Instruction loads value from memory, requiring delay. */
926 #define INSN_LOAD_MEMORY_DELAY 0x00000800
927 /* Instruction loads value from coprocessor, requiring delay. */
928 #define INSN_LOAD_COPROC_DELAY 0x00001000
929 /* Instruction has unconditional branch delay slot. */
930 #define INSN_UNCOND_BRANCH_DELAY 0x00002000
931 /* Instruction has conditional branch delay slot. */
932 #define INSN_COND_BRANCH_DELAY 0x00004000
933 /* Conditional branch likely: if branch not taken, insn nullified. */
934 #define INSN_COND_BRANCH_LIKELY 0x00008000
935 /* Moves to coprocessor register, requiring delay. */
936 #define INSN_COPROC_MOVE_DELAY 0x00010000
937 /* Loads coprocessor register from memory, requiring delay. */
938 #define INSN_COPROC_MEMORY_DELAY 0x00020000
939 /* Reads the HI register. */
940 #define INSN_READ_HI 0x00040000
941 /* Reads the LO register. */
942 #define INSN_READ_LO 0x00080000
943 /* Modifies the HI register. */
944 #define INSN_WRITE_HI 0x00100000
945 /* Modifies the LO register. */
946 #define INSN_WRITE_LO 0x00200000
947 /* Not to be placed in a branch delay slot, either architecturally
948 or for ease of handling (such as with instructions that take a trap). */
949 #define INSN_NO_DELAY_SLOT 0x00400000
950 /* Instruction stores value into memory. */
951 #define INSN_STORE_MEMORY 0x00800000
952 /* Instruction uses single precision floating point. */
953 #define FP_S 0x01000000
954 /* Instruction uses double precision floating point. */
955 #define FP_D 0x02000000
956 /* Instruction is part of the tx39's integer multiply family. */
957 #define INSN_MULT 0x04000000
958 /* Reads general purpose register 24. */
959 #define INSN_READ_GPR_24 0x08000000
960 /* Writes to general purpose register 24. */
961 #define INSN_WRITE_GPR_24 0x10000000
962 /* A user-defined instruction. */
963 #define INSN_UDI 0x20000000
964 /* Instruction is actually a macro. It should be ignored by the
965 disassembler, and requires special treatment by the assembler. */
966 #define INSN_MACRO 0xffffffff
968 /* These are the bits which may be set in the pinfo2 field of an
971 /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
972 #define INSN2_ALIAS 0x00000001
973 /* Instruction reads MDMX accumulator. */
974 #define INSN2_READ_MDMX_ACC 0x00000002
975 /* Instruction writes MDMX accumulator. */
976 #define INSN2_WRITE_MDMX_ACC 0x00000004
977 /* Macro uses single-precision floating-point instructions. This should
978 only be set for macros. For instructions, FP_S in pinfo carries the
980 #define INSN2_M_FP_S 0x00000008
981 /* Macro uses double-precision floating-point instructions. This should
982 only be set for macros. For instructions, FP_D in pinfo carries the
984 #define INSN2_M_FP_D 0x00000010
985 /* Instruction has a branch delay slot that requires a 16-bit instruction. */
986 #define INSN2_BRANCH_DELAY_16BIT 0x00000020
987 /* Instruction has a branch delay slot that requires a 32-bit instruction. */
988 #define INSN2_BRANCH_DELAY_32BIT 0x00000040
989 /* Writes to the stack pointer ($29). */
990 #define INSN2_WRITE_SP 0x00000080
991 /* Reads from the stack pointer ($29). */
992 #define INSN2_READ_SP 0x00000100
993 /* Reads the RA ($31) register. */
994 #define INSN2_READ_GPR_31 0x00000200
995 /* Reads the program counter ($pc). */
996 #define INSN2_READ_PC 0x00000400
997 /* Is an unconditional branch insn. */
998 #define INSN2_UNCOND_BRANCH 0x00000800
999 /* Is a conditional branch insn. */
1000 #define INSN2_COND_BRANCH 0x00001000
1001 /* Reads from $16. This is true of the MIPS16 0x6500 nop. */
1002 #define INSN2_READ_GPR_16 0x00002000
1003 /* Has an "\.x?y?z?w?" suffix based on mips_vu0_channel_mask. */
1004 #define INSN2_VU0_CHANNEL_SUFFIX 0x00004000
1006 /* Masks used to mark instructions to indicate which MIPS ISA level
1007 they were introduced in. INSN_ISA_MASK masks an enumeration that
1008 specifies the base ISA level(s). The remainder of a 32-bit
1009 word constructed using these macros is a bitmask of the remaining
1010 INSN_* values below. */
1012 #define INSN_ISA_MASK 0x0000000ful
1014 /* We cannot start at zero due to ISA_UNKNOWN below. */
1020 #define INSN_ISA32 6
1021 #define INSN_ISA32R2 7
1022 #define INSN_ISA64 8
1023 #define INSN_ISA64R2 9
1024 /* Below this point the INSN_* values correspond to combinations of ISAs.
1025 They are only for use in the opcodes table to indicate membership of
1026 a combination of ISAs that cannot be expressed using the usual inclusion
1027 ordering on the above INSN_* values. */
1028 #define INSN_ISA3_32 10
1029 #define INSN_ISA3_32R2 11
1030 #define INSN_ISA4_32 12
1031 #define INSN_ISA4_32R2 13
1032 #define INSN_ISA5_32R2 14
1034 /* Given INSN_ISA* values X and Y, where X ranges over INSN_ISA1 through
1035 INSN_ISA5_32R2 and Y ranges over INSN_ISA1 through INSN_ISA64R2,
1036 this table describes whether at least one of the ISAs described by X
1037 is/are implemented by ISA Y. (Think of Y as the ISA level supported by
1038 a particular core and X as the ISA level(s) at which a certain instruction
1039 is defined.) The ISA(s) described by X is/are implemented by Y iff
1040 (mips_isa_table[(Y & INSN_ISA_MASK) - 1] >> ((X & INSN_ISA_MASK) - 1)) & 1
1042 static const unsigned int mips_isa_table
[] =
1043 { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
1045 /* Masks used for Chip specific instructions. */
1046 #define INSN_CHIP_MASK 0xc3ff0f20
1048 /* Cavium Networks Octeon instructions. */
1049 #define INSN_OCTEON 0x00000800
1050 #define INSN_OCTEONP 0x00000200
1051 #define INSN_OCTEON2 0x00000100
1053 /* MIPS R5900 instruction */
1054 #define INSN_5900 0x00004000
1056 /* MIPS R4650 instruction. */
1057 #define INSN_4650 0x00010000
1058 /* LSI R4010 instruction. */
1059 #define INSN_4010 0x00020000
1060 /* NEC VR4100 instruction. */
1061 #define INSN_4100 0x00040000
1062 /* Toshiba R3900 instruction. */
1063 #define INSN_3900 0x00080000
1064 /* MIPS R10000 instruction. */
1065 #define INSN_10000 0x00100000
1066 /* Broadcom SB-1 instruction. */
1067 #define INSN_SB1 0x00200000
1068 /* NEC VR4111/VR4181 instruction. */
1069 #define INSN_4111 0x00400000
1070 /* NEC VR4120 instruction. */
1071 #define INSN_4120 0x00800000
1072 /* NEC VR5400 instruction. */
1073 #define INSN_5400 0x01000000
1074 /* NEC VR5500 instruction. */
1075 #define INSN_5500 0x02000000
1077 /* ST Microelectronics Loongson 2E. */
1078 #define INSN_LOONGSON_2E 0x40000000
1079 /* ST Microelectronics Loongson 2F. */
1080 #define INSN_LOONGSON_2F 0x80000000
1082 #define INSN_LOONGSON_3A 0x00000400
1083 /* RMI Xlr instruction */
1084 #define INSN_XLR 0x00000020
1087 #define ASE_DSP 0x00000001
1088 #define ASE_DSP64 0x00000002
1090 #define ASE_DSPR2 0x00000004
1091 /* Enhanced VA Scheme */
1092 #define ASE_EVA 0x00000008
1093 /* MCU (MicroController) ASE */
1094 #define ASE_MCU 0x00000010
1096 #define ASE_MDMX 0x00000020
1098 #define ASE_MIPS3D 0x00000040
1100 #define ASE_MT 0x00000080
1102 #define ASE_SMARTMIPS 0x00000100
1103 /* Virtualization ASE */
1104 #define ASE_VIRT 0x00000200
1105 #define ASE_VIRT64 0x00000400
1107 /* MIPS ISA defines, use instead of hardcoding ISA level. */
1109 #define ISA_UNKNOWN 0 /* Gas internal use. */
1110 #define ISA_MIPS1 INSN_ISA1
1111 #define ISA_MIPS2 INSN_ISA2
1112 #define ISA_MIPS3 INSN_ISA3
1113 #define ISA_MIPS4 INSN_ISA4
1114 #define ISA_MIPS5 INSN_ISA5
1116 #define ISA_MIPS32 INSN_ISA32
1117 #define ISA_MIPS64 INSN_ISA64
1119 #define ISA_MIPS32R2 INSN_ISA32R2
1120 #define ISA_MIPS64R2 INSN_ISA64R2
1123 /* CPU defines, use instead of hardcoding processor number. Keep this
1124 in sync with bfd/archures.c in order for machine selection to work. */
1125 #define CPU_UNKNOWN 0 /* Gas internal use. */
1126 #define CPU_R3000 3000
1127 #define CPU_R3900 3900
1128 #define CPU_R4000 4000
1129 #define CPU_R4010 4010
1130 #define CPU_VR4100 4100
1131 #define CPU_R4111 4111
1132 #define CPU_VR4120 4120
1133 #define CPU_R4300 4300
1134 #define CPU_R4400 4400
1135 #define CPU_R4600 4600
1136 #define CPU_R4650 4650
1137 #define CPU_R5000 5000
1138 #define CPU_VR5400 5400
1139 #define CPU_VR5500 5500
1140 #define CPU_R5900 5900
1141 #define CPU_R6000 6000
1142 #define CPU_RM7000 7000
1143 #define CPU_R8000 8000
1144 #define CPU_RM9000 9000
1145 #define CPU_R10000 10000
1146 #define CPU_R12000 12000
1147 #define CPU_R14000 14000
1148 #define CPU_R16000 16000
1149 #define CPU_MIPS16 16
1150 #define CPU_MIPS32 32
1151 #define CPU_MIPS32R2 33
1153 #define CPU_MIPS64 64
1154 #define CPU_MIPS64R2 65
1155 #define CPU_SB1 12310201 /* octal 'SB', 01. */
1156 #define CPU_LOONGSON_2E 3001
1157 #define CPU_LOONGSON_2F 3002
1158 #define CPU_LOONGSON_3A 3003
1159 #define CPU_OCTEON 6501
1160 #define CPU_OCTEONP 6601
1161 #define CPU_OCTEON2 6502
1162 #define CPU_XLR 887682 /* decimal 'XLR' */
1164 /* Return true if the given CPU is included in INSN_* mask MASK. */
1166 static inline bfd_boolean
1167 cpu_is_member (int cpu
, unsigned int mask
)
1174 return (mask
& INSN_4650
) != 0;
1177 return (mask
& INSN_4010
) != 0;
1180 return (mask
& INSN_4100
) != 0;
1183 return (mask
& INSN_3900
) != 0;
1189 return (mask
& INSN_10000
) != 0;
1192 return (mask
& INSN_SB1
) != 0;
1195 return (mask
& INSN_4111
) != 0;
1198 return (mask
& INSN_4120
) != 0;
1201 return (mask
& INSN_5400
) != 0;
1204 return (mask
& INSN_5500
) != 0;
1207 return (mask
& INSN_5900
) != 0;
1209 case CPU_LOONGSON_2E
:
1210 return (mask
& INSN_LOONGSON_2E
) != 0;
1212 case CPU_LOONGSON_2F
:
1213 return (mask
& INSN_LOONGSON_2F
) != 0;
1215 case CPU_LOONGSON_3A
:
1216 return (mask
& INSN_LOONGSON_3A
) != 0;
1219 return (mask
& INSN_OCTEON
) != 0;
1222 return (mask
& INSN_OCTEONP
) != 0;
1225 return (mask
& INSN_OCTEON2
) != 0;
1228 return (mask
& INSN_XLR
) != 0;
1235 /* Test for membership in an ISA including chip specific ISAs. INSN
1236 is pointer to an element of the opcode table; ISA is the specified
1237 ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
1238 test, or zero if no CPU specific ISA test is desired. Return true
1239 if instruction INSN is available to the given ISA and CPU. */
1241 static inline bfd_boolean
1242 opcode_is_member (const struct mips_opcode
*insn
, int isa
, int ase
, int cpu
)
1244 if (!cpu_is_member (cpu
, insn
->exclusions
))
1246 /* Test for ISA level compatibility. */
1247 if ((isa
& INSN_ISA_MASK
) != 0
1248 && (insn
->membership
& INSN_ISA_MASK
) != 0
1249 && ((mips_isa_table
[(isa
& INSN_ISA_MASK
) - 1]
1250 >> ((insn
->membership
& INSN_ISA_MASK
) - 1)) & 1) != 0)
1253 /* Test for ASE compatibility. */
1254 if ((ase
& insn
->ase
) != 0)
1257 /* Test for processor-specific extensions. */
1258 if (cpu_is_member (cpu
, insn
->membership
))
1264 /* This is a list of macro expanded instructions.
1266 _I appended means immediate
1267 _A appended means target address of a jump
1268 _AB appended means address with (possibly zero) base register
1269 _D appended means 64 bit floating point constant
1270 _S appended means 32 bit floating point constant. */
1525 /* The order of overloaded instructions matters. Label arguments and
1526 register arguments look the same. Instructions that can have either
1527 for arguments must apear in the correct order in this table for the
1528 assembler to pick the right one. In other words, entries with
1529 immediate operands must apear after the same instruction with
1532 Many instructions are short hand for other instructions (i.e., The
1533 jal <register> instruction is short for jalr <register>). */
1535 extern const struct mips_operand mips_vu0_channel_mask
;
1536 extern const struct mips_operand
*decode_mips_operand (const char *);
1537 extern const struct mips_opcode mips_builtin_opcodes
[];
1538 extern const int bfd_mips_num_builtin_opcodes
;
1539 extern struct mips_opcode
*mips_opcodes
;
1540 extern int bfd_mips_num_opcodes
;
1541 #define NUMOPCODES bfd_mips_num_opcodes
1544 /* The rest of this file adds definitions for the mips16 TinyRISC
1547 /* These are the bitmasks and shift counts used for the different
1548 fields in the instruction formats. Other than OP, no masks are
1549 provided for the fixed portions of an instruction, since they are
1552 The I format uses IMM11.
1554 The RI format uses RX and IMM8.
1556 The RR format uses RX, and RY.
1558 The RRI format uses RX, RY, and IMM5.
1560 The RRR format uses RX, RY, and RZ.
1562 The RRI_A format uses RX, RY, and IMM4.
1564 The SHIFT format uses RX, RY, and SHAMT.
1566 The I8 format uses IMM8.
1568 The I8_MOVR32 format uses RY and REGR32.
1570 The IR_MOV32R format uses REG32R and MOV32Z.
1572 The I64 format uses IMM8.
1574 The RI64 format uses RY and IMM5.
1577 #define MIPS16OP_MASK_OP 0x1f
1578 #define MIPS16OP_SH_OP 11
1579 #define MIPS16OP_MASK_IMM11 0x7ff
1580 #define MIPS16OP_SH_IMM11 0
1581 #define MIPS16OP_MASK_RX 0x7
1582 #define MIPS16OP_SH_RX 8
1583 #define MIPS16OP_MASK_IMM8 0xff
1584 #define MIPS16OP_SH_IMM8 0
1585 #define MIPS16OP_MASK_RY 0x7
1586 #define MIPS16OP_SH_RY 5
1587 #define MIPS16OP_MASK_IMM5 0x1f
1588 #define MIPS16OP_SH_IMM5 0
1589 #define MIPS16OP_MASK_RZ 0x7
1590 #define MIPS16OP_SH_RZ 2
1591 #define MIPS16OP_MASK_IMM4 0xf
1592 #define MIPS16OP_SH_IMM4 0
1593 #define MIPS16OP_MASK_REGR32 0x1f
1594 #define MIPS16OP_SH_REGR32 0
1595 #define MIPS16OP_MASK_REG32R 0x1f
1596 #define MIPS16OP_SH_REG32R 3
1597 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
1598 #define MIPS16OP_MASK_MOVE32Z 0x7
1599 #define MIPS16OP_SH_MOVE32Z 0
1600 #define MIPS16OP_MASK_IMM6 0x3f
1601 #define MIPS16OP_SH_IMM6 5
1603 /* These are the characters which may appears in the args field of a MIPS16
1604 instruction. They appear in the order in which the fields appear when the
1605 instruction is used. Commas and parentheses in the args string are ignored
1606 when assembling, and written into the output when disassembling.
1608 "y" 3 bit register (MIPS16OP_*_RY)
1609 "x" 3 bit register (MIPS16OP_*_RX)
1610 "z" 3 bit register (MIPS16OP_*_RZ)
1611 "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
1612 "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
1613 "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
1614 "0" zero register ($0)
1615 "S" stack pointer ($sp or $29)
1617 "R" return address register ($ra or $31)
1618 "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
1619 "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
1620 "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
1621 "a" 26 bit jump address
1622 "i" likewise, but flips bit 0
1623 "e" 11 bit extension value
1624 "l" register list for entry instruction
1625 "L" register list for exit instruction
1627 "I" an immediate value used for macros
1629 The remaining codes may be extended. Except as otherwise noted,
1630 the full extended operand is a 16 bit signed value.
1631 "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
1632 ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
1633 "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
1634 "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
1635 "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
1636 "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
1637 "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
1638 "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
1639 "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
1640 "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
1641 "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
1642 "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
1643 "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
1644 "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
1645 "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
1646 "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
1647 "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
1648 "q" 11 bit branch address (MIPS16OP_*_IMM11)
1649 "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
1650 "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
1651 "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
1652 "m" 7 bit register list for save instruction (18 bit extended)
1653 "M" 7 bit register list for restore instruction (18 bit extended)
1656 /* Save/restore encoding for the args field when all 4 registers are
1657 either saved as arguments or saved/restored as statics. */
1658 #define MIPS16_ALL_ARGS 0xe
1659 #define MIPS16_ALL_STATICS 0xb
1661 /* The following flags have the same value for the mips16 opcode
1666 INSN_UNCOND_BRANCH_DELAY
1667 INSN_COND_BRANCH_DELAY
1668 INSN_COND_BRANCH_LIKELY (never used)
1677 extern const struct mips_operand
*decode_mips16_operand (char, bfd_boolean
);
1678 extern const struct mips_opcode mips16_opcodes
[];
1679 extern const int bfd_mips16_num_opcodes
;
1681 /* These are the bit masks and shift counts used for the different fields
1682 in the microMIPS instruction formats. No masks are provided for the
1683 fixed portions of an instruction, since they are not needed. */
1685 #define MICROMIPSOP_MASK_IMMEDIATE 0xffff
1686 #define MICROMIPSOP_SH_IMMEDIATE 0
1687 #define MICROMIPSOP_MASK_DELTA 0xffff
1688 #define MICROMIPSOP_SH_DELTA 0
1689 #define MICROMIPSOP_MASK_CODE10 0x3ff
1690 #define MICROMIPSOP_SH_CODE10 16 /* 10-bit wait code. */
1691 #define MICROMIPSOP_MASK_TRAP 0xf
1692 #define MICROMIPSOP_SH_TRAP 12 /* 4-bit trap code. */
1693 #define MICROMIPSOP_MASK_SHAMT 0x1f
1694 #define MICROMIPSOP_SH_SHAMT 11
1695 #define MICROMIPSOP_MASK_TARGET 0x3ffffff
1696 #define MICROMIPSOP_SH_TARGET 0
1697 #define MICROMIPSOP_MASK_EXTLSB 0x1f /* "ext" LSB. */
1698 #define MICROMIPSOP_SH_EXTLSB 6
1699 #define MICROMIPSOP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */
1700 #define MICROMIPSOP_SH_EXTMSBD 11
1701 #define MICROMIPSOP_MASK_INSMSB 0x1f /* "ins" MSB. */
1702 #define MICROMIPSOP_SH_INSMSB 11
1703 #define MICROMIPSOP_MASK_CODE 0x3ff
1704 #define MICROMIPSOP_SH_CODE 16 /* 10-bit higher break code. */
1705 #define MICROMIPSOP_MASK_CODE2 0x3ff
1706 #define MICROMIPSOP_SH_CODE2 6 /* 10-bit lower break code. */
1707 #define MICROMIPSOP_MASK_CACHE 0x1f
1708 #define MICROMIPSOP_SH_CACHE 21 /* 5-bit cache op. */
1709 #define MICROMIPSOP_MASK_SEL 0x7
1710 #define MICROMIPSOP_SH_SEL 11
1711 #define MICROMIPSOP_MASK_OFFSET12 0xfff
1712 #define MICROMIPSOP_SH_OFFSET12 0
1713 #define MICROMIPSOP_MASK_3BITPOS 0x7
1714 #define MICROMIPSOP_SH_3BITPOS 21
1715 #define MICROMIPSOP_MASK_STYPE 0x1f
1716 #define MICROMIPSOP_SH_STYPE 16
1717 #define MICROMIPSOP_MASK_OFFSET10 0x3ff
1718 #define MICROMIPSOP_SH_OFFSET10 6
1719 #define MICROMIPSOP_MASK_RS 0x1f
1720 #define MICROMIPSOP_SH_RS 16
1721 #define MICROMIPSOP_MASK_RT 0x1f
1722 #define MICROMIPSOP_SH_RT 21
1723 #define MICROMIPSOP_MASK_RD 0x1f
1724 #define MICROMIPSOP_SH_RD 11
1725 #define MICROMIPSOP_MASK_FS 0x1f
1726 #define MICROMIPSOP_SH_FS 16
1727 #define MICROMIPSOP_MASK_FT 0x1f
1728 #define MICROMIPSOP_SH_FT 21
1729 #define MICROMIPSOP_MASK_FD 0x1f
1730 #define MICROMIPSOP_SH_FD 11
1731 #define MICROMIPSOP_MASK_FR 0x1f
1732 #define MICROMIPSOP_SH_FR 6
1733 #define MICROMIPSOP_MASK_RS3 0x1f
1734 #define MICROMIPSOP_SH_RS3 6
1735 #define MICROMIPSOP_MASK_PREFX 0x1f
1736 #define MICROMIPSOP_SH_PREFX 11
1737 #define MICROMIPSOP_MASK_BCC 0x7
1738 #define MICROMIPSOP_SH_BCC 18
1739 #define MICROMIPSOP_MASK_CCC 0x7
1740 #define MICROMIPSOP_SH_CCC 13
1741 #define MICROMIPSOP_MASK_COPZ 0x7fffff
1742 #define MICROMIPSOP_SH_COPZ 3
1744 #define MICROMIPSOP_MASK_MB 0x7
1745 #define MICROMIPSOP_SH_MB 23
1746 #define MICROMIPSOP_MASK_MC 0x7
1747 #define MICROMIPSOP_SH_MC 4
1748 #define MICROMIPSOP_MASK_MD 0x7
1749 #define MICROMIPSOP_SH_MD 7
1750 #define MICROMIPSOP_MASK_ME 0x7
1751 #define MICROMIPSOP_SH_ME 1
1752 #define MICROMIPSOP_MASK_MF 0x7
1753 #define MICROMIPSOP_SH_MF 3
1754 #define MICROMIPSOP_MASK_MG 0x7
1755 #define MICROMIPSOP_SH_MG 0
1756 #define MICROMIPSOP_MASK_MH 0x7
1757 #define MICROMIPSOP_SH_MH 7
1758 #define MICROMIPSOP_MASK_MJ 0x1f
1759 #define MICROMIPSOP_SH_MJ 0
1760 #define MICROMIPSOP_MASK_ML 0x7
1761 #define MICROMIPSOP_SH_ML 4
1762 #define MICROMIPSOP_MASK_MM 0x7
1763 #define MICROMIPSOP_SH_MM 1
1764 #define MICROMIPSOP_MASK_MN 0x7
1765 #define MICROMIPSOP_SH_MN 4
1766 #define MICROMIPSOP_MASK_MP 0x1f
1767 #define MICROMIPSOP_SH_MP 5
1768 #define MICROMIPSOP_MASK_MQ 0x7
1769 #define MICROMIPSOP_SH_MQ 7
1771 #define MICROMIPSOP_MASK_IMMA 0x7f
1772 #define MICROMIPSOP_SH_IMMA 0
1773 #define MICROMIPSOP_MASK_IMMB 0x7
1774 #define MICROMIPSOP_SH_IMMB 1
1775 #define MICROMIPSOP_MASK_IMMC 0xf
1776 #define MICROMIPSOP_SH_IMMC 0
1777 #define MICROMIPSOP_MASK_IMMD 0x3ff
1778 #define MICROMIPSOP_SH_IMMD 0
1779 #define MICROMIPSOP_MASK_IMME 0x7f
1780 #define MICROMIPSOP_SH_IMME 0
1781 #define MICROMIPSOP_MASK_IMMF 0xf
1782 #define MICROMIPSOP_SH_IMMF 0
1783 #define MICROMIPSOP_MASK_IMMG 0xf
1784 #define MICROMIPSOP_SH_IMMG 0
1785 #define MICROMIPSOP_MASK_IMMH 0xf
1786 #define MICROMIPSOP_SH_IMMH 0
1787 #define MICROMIPSOP_MASK_IMMI 0x7f
1788 #define MICROMIPSOP_SH_IMMI 0
1789 #define MICROMIPSOP_MASK_IMMJ 0xf
1790 #define MICROMIPSOP_SH_IMMJ 0
1791 #define MICROMIPSOP_MASK_IMML 0xf
1792 #define MICROMIPSOP_SH_IMML 0
1793 #define MICROMIPSOP_MASK_IMMM 0x7
1794 #define MICROMIPSOP_SH_IMMM 1
1795 #define MICROMIPSOP_MASK_IMMN 0x3
1796 #define MICROMIPSOP_SH_IMMN 4
1797 #define MICROMIPSOP_MASK_IMMO 0xf
1798 #define MICROMIPSOP_SH_IMMO 0
1799 #define MICROMIPSOP_MASK_IMMP 0x1f
1800 #define MICROMIPSOP_SH_IMMP 0
1801 #define MICROMIPSOP_MASK_IMMQ 0x7fffff
1802 #define MICROMIPSOP_SH_IMMQ 0
1803 #define MICROMIPSOP_MASK_IMMU 0x1f
1804 #define MICROMIPSOP_SH_IMMU 0
1805 #define MICROMIPSOP_MASK_IMMW 0x3f
1806 #define MICROMIPSOP_SH_IMMW 1
1807 #define MICROMIPSOP_MASK_IMMX 0xf
1808 #define MICROMIPSOP_SH_IMMX 1
1809 #define MICROMIPSOP_MASK_IMMY 0x1ff
1810 #define MICROMIPSOP_SH_IMMY 1
1813 #define MICROMIPSOP_MASK_DSPACC 0x3
1814 #define MICROMIPSOP_SH_DSPACC 14
1815 #define MICROMIPSOP_MASK_DSPSFT 0x3f
1816 #define MICROMIPSOP_SH_DSPSFT 16
1817 #define MICROMIPSOP_MASK_SA3 0x7
1818 #define MICROMIPSOP_SH_SA3 13
1819 #define MICROMIPSOP_MASK_SA4 0xf
1820 #define MICROMIPSOP_SH_SA4 12
1821 #define MICROMIPSOP_MASK_IMM8 0xff
1822 #define MICROMIPSOP_SH_IMM8 13
1823 #define MICROMIPSOP_MASK_IMM10 0x3ff
1824 #define MICROMIPSOP_SH_IMM10 16
1825 #define MICROMIPSOP_MASK_WRDSP 0x3f
1826 #define MICROMIPSOP_SH_WRDSP 14
1827 #define MICROMIPSOP_MASK_BP 0x3
1828 #define MICROMIPSOP_SH_BP 14
1830 /* Placeholders for fields that only exist in the traditional 32-bit
1831 instruction encoding; see the comment above for details. */
1832 #define MICROMIPSOP_MASK_CODE20 0
1833 #define MICROMIPSOP_SH_CODE20 0
1834 #define MICROMIPSOP_MASK_PERFREG 0
1835 #define MICROMIPSOP_SH_PERFREG 0
1836 #define MICROMIPSOP_MASK_CODE19 0
1837 #define MICROMIPSOP_SH_CODE19 0
1838 #define MICROMIPSOP_MASK_ALN 0
1839 #define MICROMIPSOP_SH_ALN 0
1840 #define MICROMIPSOP_MASK_VECBYTE 0
1841 #define MICROMIPSOP_SH_VECBYTE 0
1842 #define MICROMIPSOP_MASK_VECALIGN 0
1843 #define MICROMIPSOP_SH_VECALIGN 0
1844 #define MICROMIPSOP_MASK_DSPACC_S 0
1845 #define MICROMIPSOP_SH_DSPACC_S 0
1846 #define MICROMIPSOP_MASK_DSPSFT_7 0
1847 #define MICROMIPSOP_SH_DSPSFT_7 0
1848 #define MICROMIPSOP_MASK_RDDSP 0
1849 #define MICROMIPSOP_SH_RDDSP 0
1850 #define MICROMIPSOP_MASK_MT_U 0
1851 #define MICROMIPSOP_SH_MT_U 0
1852 #define MICROMIPSOP_MASK_MT_H 0
1853 #define MICROMIPSOP_SH_MT_H 0
1854 #define MICROMIPSOP_MASK_MTACC_T 0
1855 #define MICROMIPSOP_SH_MTACC_T 0
1856 #define MICROMIPSOP_MASK_MTACC_D 0
1857 #define MICROMIPSOP_SH_MTACC_D 0
1858 #define MICROMIPSOP_MASK_BBITIND 0
1859 #define MICROMIPSOP_SH_BBITIND 0
1860 #define MICROMIPSOP_MASK_CINSPOS 0
1861 #define MICROMIPSOP_SH_CINSPOS 0
1862 #define MICROMIPSOP_MASK_CINSLM1 0
1863 #define MICROMIPSOP_SH_CINSLM1 0
1864 #define MICROMIPSOP_MASK_SEQI 0
1865 #define MICROMIPSOP_SH_SEQI 0
1866 #define MICROMIPSOP_SH_OFFSET_A 0
1867 #define MICROMIPSOP_MASK_OFFSET_A 0
1868 #define MICROMIPSOP_SH_OFFSET_B 0
1869 #define MICROMIPSOP_MASK_OFFSET_B 0
1870 #define MICROMIPSOP_SH_OFFSET_C 0
1871 #define MICROMIPSOP_MASK_OFFSET_C 0
1872 #define MICROMIPSOP_SH_RZ 0
1873 #define MICROMIPSOP_MASK_RZ 0
1874 #define MICROMIPSOP_SH_FZ 0
1875 #define MICROMIPSOP_MASK_FZ 0
1877 /* microMIPS Enhanced VA Scheme */
1878 #define MICROMIPSOP_SH_EVAOFFSET 0
1879 #define MICROMIPSOP_MASK_EVAOFFSET 0x1ff
1881 /* These are the characters which may appears in the args field of a microMIPS
1882 instruction. They appear in the order in which the fields appear
1883 when the instruction is used. Commas and parentheses in the args
1884 string are ignored when assembling, and written into the output
1887 The followings are for 16-bit microMIPS instructions.
1890 "mc" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MC) at bit 4
1891 The same register used as both source and target.
1892 "md" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MD) at bit 7
1893 "me" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ME) at bit 1
1894 The same register used as both source and target.
1895 "mf" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MF) at bit 3
1896 "mg" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MG) at bit 0
1897 "mh" 3-bit MIPS register pair (MICROMIPSOP_*_MH) at bit 7
1898 "mj" 5-bit MIPS registers (MICROMIPSOP_*_MJ) at bit 0
1899 "ml" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ML) at bit 4
1900 "mm" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MM) at bit 1
1901 "mn" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MN) at bit 4
1902 "mp" 5-bit MIPS registers (MICROMIPSOP_*_MP) at bit 5
1903 "mq" 3-bit MIPS registers 0, 2-7, 17 (MICROMIPSOP_*_MQ) at bit 7
1904 "mr" must be program counter
1906 "mt" must be the same as the previous register
1907 "mx" must be the same as the destination register
1911 "mA" 7-bit immediate (-64 .. 63) << 2 (MICROMIPSOP_*_IMMA)
1912 "mB" 3-bit immediate (-1, 1, 4, 8, 12, 16, 20, 24) (MICROMIPSOP_*_IMMB)
1913 "mC" 4-bit immediate (1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 128, 255,
1914 32768, 65535) (MICROMIPSOP_*_IMMC)
1915 "mD" 10-bit branch address (-512 .. 511) << 1 (MICROMIPSOP_*_IMMD)
1916 "mE" 7-bit branch address (-64 .. 63) << 1 (MICROMIPSOP_*_IMME)
1917 "mF" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMMF)
1918 "mG" 4-bit immediate (-1 .. 14) (MICROMIPSOP_*_IMMG)
1919 "mH" 4-bit immediate (0 .. 15) << 1 (MICROMIPSOP_*_IMMH)
1920 "mI" 7-bit immediate (-1 .. 126) (MICROMIPSOP_*_IMMI)
1921 "mJ" 4-bit immediate (0 .. 15) << 2 (MICROMIPSOP_*_IMMJ)
1922 "mL" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML)
1923 "mM" 3-bit immediate (1 .. 8) (MICROMIPSOP_*_IMMM)
1924 "mN" 2-bit immediate (0 .. 3) for register list (MICROMIPSOP_*_IMMN)
1925 "mO" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML)
1926 "mP" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMP)
1927 "mU" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMU)
1928 "mW" 6-bit immediate (0 .. 63) << 2 (MICROMIPSOP_*_IMMW)
1929 "mX" 4-bit immediate (-8 .. 7) (MICROMIPSOP_*_IMMX)
1930 "mY" 9-bit immediate (-258 .. -3, 2 .. 257) << 2 (MICROMIPSOP_*_IMMY)
1933 In most cases 32-bit microMIPS instructions use the same characters
1934 as MIPS (with ADDIUPC being a notable exception, but there are some
1937 "." 10-bit signed offset/number (MICROMIPSOP_*_OFFSET10)
1938 "1" 5-bit sync type (MICROMIPSOP_*_STYPE)
1939 "<" 5-bit shift amount (MICROMIPSOP_*_SHAMT)
1940 ">" shift amount between 32 and 63, stored after subtracting 32
1941 (MICROMIPSOP_*_SHAMT)
1942 "\" 3-bit position for ASET and ACLR (MICROMIPSOP_*_3BITPOS)
1943 "|" 4-bit trap code (MICROMIPSOP_*_TRAP)
1944 "~" 12-bit signed offset (MICROMIPSOP_*_OFFSET12)
1945 "a" 26-bit target address (MICROMIPSOP_*_TARGET)
1946 "+i" likewise, but flips bit 0
1947 "b" 5-bit base register (MICROMIPSOP_*_RS)
1948 "c" 10-bit higher breakpoint code (MICROMIPSOP_*_CODE)
1949 "d" 5-bit destination register specifier (MICROMIPSOP_*_RD)
1950 "h" 5-bit PREFX hint (MICROMIPSOP_*_PREFX)
1951 "i" 16-bit unsigned immediate (MICROMIPSOP_*_IMMEDIATE)
1952 "j" 16-bit signed immediate (MICROMIPSOP_*_DELTA)
1953 "k" 5-bit cache opcode in target register position (MICROMIPSOP_*_CACHE)
1954 "n" register list for 32-bit LWM/SWM instruction (MICROMIPSOP_*_RT)
1955 "o" 16-bit signed offset (MICROMIPSOP_*_DELTA)
1956 "p" 16-bit PC-relative branch target address (MICROMIPSOP_*_DELTA)
1957 "q" 10-bit lower breakpoint code (MICROMIPSOP_*_CODE2)
1958 "r" 5-bit same register used as both source and target (MICROMIPSOP_*_RS)
1959 "s" 5-bit source register specifier (MICROMIPSOP_*_RS)
1960 "t" 5-bit target register (MICROMIPSOP_*_RT)
1961 "u" 16-bit upper 16 bits of address (MICROMIPSOP_*_IMMEDIATE)
1962 "v" 5-bit same register used as both source and destination
1964 "w" 5-bit same register used as both target and destination
1966 "y" 5-bit source 3 register for ALNV.PS (MICROMIPSOP_*_RS3)
1967 "z" must be zero register
1968 "C" 23-bit coprocessor function code (MICROMIPSOP_*_COPZ)
1969 "B" 10-bit syscall/wait function code (MICROMIPSOP_*_CODE10)
1970 "K" 5-bit Hardware Register (RDHWR instruction) (MICROMIPSOP_*_RS)
1972 "+A" 5-bit INS/EXT/DINS/DEXT/DINSM/DEXTM position, which becomes
1973 LSB (MICROMIPSOP_*_EXTLSB).
1974 Enforces: 0 <= pos < 32.
1975 "+B" 5-bit INS/DINS size, which becomes MSB (MICROMIPSOP_*_INSMSB).
1976 Requires that "+A" or "+E" occur first to set position.
1977 Enforces: 0 < (pos+size) <= 32.
1978 "+C" 5-bit EXT/DEXT size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD).
1979 Requires that "+A" or "+E" occur first to set position.
1980 Enforces: 0 < (pos+size) <= 32.
1981 (Also used by DEXT w/ different limits, but limits for
1982 that are checked by the M_DEXT macro.)
1983 "+E" 5-bit DINSU/DEXTU position, which becomes LSB-32 (MICROMIPSOP_*_EXTLSB).
1984 Enforces: 32 <= pos < 64.
1985 "+F" 5-bit DINSM/DINSU size, which becomes MSB-32 (MICROMIPSOP_*_INSMSB).
1986 Requires that "+A" or "+E" occur first to set position.
1987 Enforces: 32 < (pos+size) <= 64.
1988 "+G" 5-bit DEXTM size, which becomes MSBD-32 (MICROMIPSOP_*_EXTMSBD).
1989 Requires that "+A" or "+E" occur first to set position.
1990 Enforces: 32 < (pos+size) <= 64.
1991 "+H" 5-bit DEXTU size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD).
1992 Requires that "+A" or "+E" occur first to set position.
1993 Enforces: 32 < (pos+size) <= 64.
1995 PC-relative addition (ADDIUPC) instruction:
1996 "mQ" 23-bit offset (-4194304 .. 4194303) << 2 (MICROMIPSOP_*_IMMQ)
1997 "mb" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MB) at bit 23
1999 Floating point instructions:
2000 "D" 5-bit destination register (MICROMIPSOP_*_FD)
2001 "M" 3-bit compare condition code (MICROMIPSOP_*_CCC)
2002 "N" 3-bit branch condition code (MICROMIPSOP_*_BCC)
2003 "R" 5-bit fr source 3 register (MICROMIPSOP_*_FR)
2004 "S" 5-bit fs source 1 register (MICROMIPSOP_*_FS)
2005 "T" 5-bit ft source 2 register (MICROMIPSOP_*_FT)
2006 "V" 5-bit same register used as floating source and destination or target
2009 Coprocessor instructions:
2010 "E" 5-bit target register (MICROMIPSOP_*_RT)
2011 "G" 5-bit source register (MICROMIPSOP_*_RS)
2012 "H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL)
2015 "A" general 32 bit expression
2016 "I" 32-bit immediate (value placed in imm_expr).
2017 "+I" 32-bit immediate (value placed in imm2_expr).
2018 "F" 64-bit floating point constant in .rdata
2019 "L" 64-bit floating point constant in .lit8
2020 "f" 32-bit floating point constant
2021 "l" 32-bit floating point constant in .lit4
2024 "2" 2-bit unsigned immediate for byte align (MICROMIPSOP_*_BP)
2025 "3" 3-bit unsigned immediate (MICROMIPSOP_*_SA3)
2026 "4" 4-bit unsigned immediate (MICROMIPSOP_*_SA4)
2027 "5" 8-bit unsigned immediate (MICROMIPSOP_*_IMM8)
2028 "6" 5-bit unsigned immediate (MICROMIPSOP_*_RS)
2029 "7" 2-bit DSP accumulator register (MICROMIPSOP_*_DSPACC)
2030 "8" 6-bit unsigned immediate (MICROMIPSOP_*_WRDSP)
2031 "0" 6-bit signed immediate (MICROMIPSOP_*_DSPSFT)
2032 "@" 10-bit signed immediate (MICROMIPSOP_*_IMM10)
2033 "^" 5-bit unsigned immediate (MICROMIPSOP_*_RD)
2035 microMIPS Enhanced VA Scheme:
2036 "+j" 9-bit signed offset in bit 0 (OP_*_EVAOFFSET)
2039 "()" parens surrounding optional value
2040 "," separates operands
2041 "+" start of extension sequence
2042 "m" start of microMIPS extension sequence
2044 Characters used so far, for quick reference when adding more:
2047 "ABCDEFGHI KLMN RST V "
2048 "abcd f hijklmnopqrstuvw yz"
2050 Extension character sequences used so far ("+" followed by the
2051 following), for quick reference when adding more:
2057 Extension character sequences used so far ("m" followed by the
2058 following), for quick reference when adding more:
2061 " BCDEFGHIJ LMNOPQ U WXYZ"
2062 " bcdefghij lmn pq st xyz"
2065 extern const struct mips_operand
*decode_micromips_operand (const char *);
2066 extern const struct mips_opcode micromips_opcodes
[];
2067 extern const int bfd_micromips_num_opcodes
;
2069 /* A NOP insn impemented as "or at,at,zero".
2070 Used to implement -mfix-loongson2f. */
2071 #define LOONGSON2F_NOP_INSN 0x00200825
2073 #endif /* _MIPS_H_ */