include/opcode/mips.h

   1 /* mips.h.  Mips opcode list for GDB, the GNU debugger.
   2    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
   3    2003, 2004, 2005, 2008, 2009, 2010, 2013
   4    Free Software Foundation, Inc.
   5    Contributed by Ralph Campbell and OSF
   6    Commented and modified by Ian Lance Taylor, Cygnus Support
   7
   8    This file is part of GDB, GAS, and the GNU binutils.
   9
  10    GDB, GAS, and the GNU binutils are free software; you can redistribute
  11    them and/or modify them under the terms of the GNU General Public
  12    License as published by the Free Software Foundation; either version 3,
  13    or (at your option) any later version.
  14
  15    GDB, GAS, and the GNU binutils are distributed in the hope that they
  16    will be useful, but WITHOUT ANY WARRANTY; without even the implied
  17    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  18    the GNU General Public License for more details.
  19
  20    You should have received a copy of the GNU General Public License
  21    along with this file; see the file COPYING3.  If not, write to the Free
  22    Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  23    MA 02110-1301, USA.  */
  24
  25 #ifndef _MIPS_H_
  26 #define _MIPS_H_
  27
  28 #include "bfd.h"
  29
  30 /* These are bit masks and shift counts to use to access the various
  31    fields of an instruction.  To retrieve the X field of an
  32    instruction, use the expression
  33         (i >> OP_SH_X) & OP_MASK_X
  34    To set the same field (to j), use
  35         i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
  36
  37    Make sure you use fields that are appropriate for the instruction,
  38    of course.
  39
  40    The 'i' format uses OP, RS, RT and IMMEDIATE.
  41
  42    The 'j' format uses OP and TARGET.
  43
  44    The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
  45
  46    The 'b' format uses OP, RS, RT and DELTA.
  47
  48    The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
  49
  50    The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
  51
  52    A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
  53    breakpoint instruction are not defined; Kane says the breakpoint
  54    code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
  55    only use ten bits).  An optional two-operand form of break/sdbbp
  56    allows the lower ten bits to be set too, and MIPS32 and later
  57    architectures allow 20 bits to be set with a signal operand
  58    (using CODE20).
  59
  60    The syscall instruction uses CODE20.
  61
  62    The general coprocessor instructions use COPZ.  */
  63
  64 #define OP_MASK_OP              0x3f
  65 #define OP_SH_OP                26
  66 #define OP_MASK_RS              0x1f
  67 #define OP_SH_RS                21
  68 #define OP_MASK_FR              0x1f
  69 #define OP_SH_FR                21
  70 #define OP_MASK_FMT             0x1f
  71 #define OP_SH_FMT               21
  72 #define OP_MASK_BCC             0x7
  73 #define OP_SH_BCC               18
  74 #define OP_MASK_CODE            0x3ff
  75 #define OP_SH_CODE              16
  76 #define OP_MASK_CODE2           0x3ff
  77 #define OP_SH_CODE2             6
  78 #define OP_MASK_RT              0x1f
  79 #define OP_SH_RT                16
  80 #define OP_MASK_FT              0x1f
  81 #define OP_SH_FT                16
  82 #define OP_MASK_CACHE           0x1f
  83 #define OP_SH_CACHE             16
  84 #define OP_MASK_RD              0x1f
  85 #define OP_SH_RD                11
  86 #define OP_MASK_FS              0x1f
  87 #define OP_SH_FS                11
  88 #define OP_MASK_PREFX           0x1f
  89 #define OP_SH_PREFX             11
  90 #define OP_MASK_CCC             0x7
  91 #define OP_SH_CCC               8
  92 #define OP_MASK_CODE20          0xfffff /* 20 bit syscall/breakpoint code.  */
  93 #define OP_SH_CODE20            6
  94 #define OP_MASK_SHAMT           0x1f
  95 #define OP_SH_SHAMT             6
  96 #define OP_MASK_EXTLSB          OP_MASK_SHAMT
  97 #define OP_SH_EXTLSB            OP_SH_SHAMT
  98 #define OP_MASK_STYPE           OP_MASK_SHAMT
  99 #define OP_SH_STYPE             OP_SH_SHAMT
 100 #define OP_MASK_FD              0x1f
 101 #define OP_SH_FD                6
 102 #define OP_MASK_TARGET          0x3ffffff
 103 #define OP_SH_TARGET            0
 104 #define OP_MASK_COPZ            0x1ffffff
 105 #define OP_SH_COPZ              0
 106 #define OP_MASK_IMMEDIATE       0xffff
 107 #define OP_SH_IMMEDIATE         0
 108 #define OP_MASK_DELTA           0xffff
 109 #define OP_SH_DELTA             0
 110 #define OP_MASK_FUNCT           0x3f
 111 #define OP_SH_FUNCT             0
 112 #define OP_MASK_SPEC            0x3f
 113 #define OP_SH_SPEC              0
 114 #define OP_SH_LOCC              8       /* FP condition code.  */
 115 #define OP_SH_HICC              18      /* FP condition code.  */
 116 #define OP_MASK_CC              0x7
 117 #define OP_SH_COP1NORM          25      /* Normal COP1 encoding.  */
 118 #define OP_MASK_COP1NORM        0x1     /* a single bit.  */
 119 #define OP_SH_COP1SPEC          21      /* COP1 encodings.  */
 120 #define OP_MASK_COP1SPEC        0xf
 121 #define OP_MASK_COP1SCLR        0x4
 122 #define OP_MASK_COP1CMP         0x3
 123 #define OP_SH_COP1CMP           4
 124 #define OP_SH_FORMAT            21      /* FP short format field.  */
 125 #define OP_MASK_FORMAT          0x7
 126 #define OP_SH_TRUE              16
 127 #define OP_MASK_TRUE            0x1
 128 #define OP_SH_GE                17
 129 #define OP_MASK_GE              0x01
 130 #define OP_SH_UNSIGNED          16
 131 #define OP_MASK_UNSIGNED        0x1
 132 #define OP_SH_HINT              16
 133 #define OP_MASK_HINT            0x1f
 134 #define OP_SH_MMI               0       /* Multimedia (parallel) op.  */
 135 #define OP_MASK_MMI             0x3f
 136 #define OP_SH_MMISUB            6
 137 #define OP_MASK_MMISUB          0x1f
 138 #define OP_MASK_PERFREG         0x1f    /* Performance monitoring.  */
 139 #define OP_SH_PERFREG           1
 140 #define OP_SH_SEL               0       /* Coprocessor select field.  */
 141 #define OP_MASK_SEL             0x7     /* The sel field of mfcZ and mtcZ.  */
 142 #define OP_SH_CODE19            6       /* 19 bit wait code.  */
 143 #define OP_MASK_CODE19          0x7ffff
 144 #define OP_SH_ALN               21
 145 #define OP_MASK_ALN             0x7
 146 #define OP_SH_VSEL              21
 147 #define OP_MASK_VSEL            0x1f
 148 #define OP_MASK_VECBYTE         0x7     /* Selector field is really 4 bits,
 149                                            but 0x8-0xf don't select bytes.  */
 150 #define OP_SH_VECBYTE           22
 151 #define OP_MASK_VECALIGN        0x7     /* Vector byte-align (alni.ob) op.  */
 152 #define OP_SH_VECALIGN          21
 153 #define OP_MASK_INSMSB          0x1f    /* "ins" MSB.  */
 154 #define OP_SH_INSMSB            11
 155 #define OP_MASK_EXTMSBD         0x1f    /* "ext" MSBD.  */
 156 #define OP_SH_EXTMSBD           11
 157
 158 /* MIPS DSP ASE */
 159 #define OP_SH_DSPACC            11
 160 #define OP_MASK_DSPACC          0x3
 161 #define OP_SH_DSPACC_S          21
 162 #define OP_MASK_DSPACC_S        0x3
 163 #define OP_SH_DSPSFT            20
 164 #define OP_MASK_DSPSFT          0x3f
 165 #define OP_SH_DSPSFT_7          19
 166 #define OP_MASK_DSPSFT_7        0x7f
 167 #define OP_SH_SA3               21
 168 #define OP_MASK_SA3             0x7
 169 #define OP_SH_SA4               21
 170 #define OP_MASK_SA4             0xf
 171 #define OP_SH_IMM8              16
 172 #define OP_MASK_IMM8            0xff
 173 #define OP_SH_IMM10             16
 174 #define OP_MASK_IMM10           0x3ff
 175 #define OP_SH_WRDSP             11
 176 #define OP_MASK_WRDSP           0x3f
 177 #define OP_SH_RDDSP             16
 178 #define OP_MASK_RDDSP           0x3f
 179 #define OP_SH_BP                11
 180 #define OP_MASK_BP              0x3
 181
 182 /* MIPS MT ASE */
 183 #define OP_SH_MT_U              5
 184 #define OP_MASK_MT_U            0x1
 185 #define OP_SH_MT_H              4
 186 #define OP_MASK_MT_H            0x1
 187 #define OP_SH_MTACC_T           18
 188 #define OP_MASK_MTACC_T         0x3
 189 #define OP_SH_MTACC_D           13
 190 #define OP_MASK_MTACC_D         0x3
 191
 192 /* MIPS MCU ASE */
 193 #define OP_MASK_3BITPOS         0x7
 194 #define OP_SH_3BITPOS           12
 195 #define OP_MASK_OFFSET12        0xfff
 196 #define OP_SH_OFFSET12          0
 197
 198 #define OP_OP_COP0              0x10
 199 #define OP_OP_COP1              0x11
 200 #define OP_OP_COP2              0x12
 201 #define OP_OP_COP3              0x13
 202 #define OP_OP_LWC1              0x31
 203 #define OP_OP_LWC2              0x32
 204 #define OP_OP_LWC3              0x33    /* a.k.a. pref */
 205 #define OP_OP_LDC1              0x35
 206 #define OP_OP_LDC2              0x36
 207 #define OP_OP_LDC3              0x37    /* a.k.a. ld */
 208 #define OP_OP_SWC1              0x39
 209 #define OP_OP_SWC2              0x3a
 210 #define OP_OP_SWC3              0x3b
 211 #define OP_OP_SDC1              0x3d
 212 #define OP_OP_SDC2              0x3e
 213 #define OP_OP_SDC3              0x3f    /* a.k.a. sd */
 214
 215 /* MIPS VIRT ASE */
 216 #define OP_MASK_CODE10          0x3ff
 217 #define OP_SH_CODE10            11
 218
 219 /* Values in the 'VSEL' field.  */
 220 #define MDMX_FMTSEL_IMM_QH      0x1d
 221 #define MDMX_FMTSEL_IMM_OB      0x1e
 222 #define MDMX_FMTSEL_VEC_QH      0x15
 223 #define MDMX_FMTSEL_VEC_OB      0x16
 224
 225 /* UDI */
 226 #define OP_SH_UDI1              6
 227 #define OP_MASK_UDI1            0x1f
 228 #define OP_SH_UDI2              6
 229 #define OP_MASK_UDI2            0x3ff
 230 #define OP_SH_UDI3              6
 231 #define OP_MASK_UDI3            0x7fff
 232 #define OP_SH_UDI4              6
 233 #define OP_MASK_UDI4            0xfffff
 234
 235 /* Octeon */
 236 #define OP_SH_BBITIND           16
 237 #define OP_MASK_BBITIND         0x1f
 238 #define OP_SH_CINSPOS           6
 239 #define OP_MASK_CINSPOS         0x1f
 240 #define OP_SH_CINSLM1           11
 241 #define OP_MASK_CINSLM1         0x1f
 242 #define OP_SH_SEQI              6
 243 #define OP_MASK_SEQI            0x3ff
 244
 245 /* Loongson */
 246 #define OP_SH_OFFSET_A          6
 247 #define OP_MASK_OFFSET_A        0xff
 248 #define OP_SH_OFFSET_B          3
 249 #define OP_MASK_OFFSET_B        0xff
 250 #define OP_SH_OFFSET_C          6
 251 #define OP_MASK_OFFSET_C        0x1ff
 252 #define OP_SH_RZ                0
 253 #define OP_MASK_RZ              0x1f
 254 #define OP_SH_FZ                0
 255 #define OP_MASK_FZ              0x1f
 256
 257 /* Every MICROMIPSOP_X definition requires a corresponding OP_X
 258    definition, and vice versa.  This simplifies various parts
 259    of the operand handling in GAS.  The fields below only exist
 260    in the microMIPS encoding, so define each one to have an empty
 261    range.  */
 262 #define OP_MASK_TRAP            0
 263 #define OP_SH_TRAP              0
 264 #define OP_MASK_OFFSET10        0
 265 #define OP_SH_OFFSET10          0
 266 #define OP_MASK_RS3             0
 267 #define OP_SH_RS3               0
 268 #define OP_MASK_MB              0
 269 #define OP_SH_MB                0
 270 #define OP_MASK_MC              0
 271 #define OP_SH_MC                0
 272 #define OP_MASK_MD              0
 273 #define OP_SH_MD                0
 274 #define OP_MASK_ME              0
 275 #define OP_SH_ME                0
 276 #define OP_MASK_MF              0
 277 #define OP_SH_MF                0
 278 #define OP_MASK_MG              0
 279 #define OP_SH_MG                0
 280 #define OP_MASK_MH              0
 281 #define OP_SH_MH                0
 282 #define OP_MASK_MI              0
 283 #define OP_SH_MI                0
 284 #define OP_MASK_MJ              0
 285 #define OP_SH_MJ                0
 286 #define OP_MASK_ML              0
 287 #define OP_SH_ML                0
 288 #define OP_MASK_MM              0
 289 #define OP_SH_MM                0
 290 #define OP_MASK_MN              0
 291 #define OP_SH_MN                0
 292 #define OP_MASK_MP              0
 293 #define OP_SH_MP                0
 294 #define OP_MASK_MQ              0
 295 #define OP_SH_MQ                0
 296 #define OP_MASK_IMMA            0
 297 #define OP_SH_IMMA              0
 298 #define OP_MASK_IMMB            0
 299 #define OP_SH_IMMB              0
 300 #define OP_MASK_IMMC            0
 301 #define OP_SH_IMMC              0
 302 #define OP_MASK_IMMF            0
 303 #define OP_SH_IMMF              0
 304 #define OP_MASK_IMMG            0
 305 #define OP_SH_IMMG              0
 306 #define OP_MASK_IMMH            0
 307 #define OP_SH_IMMH              0
 308 #define OP_MASK_IMMI            0
 309 #define OP_SH_IMMI              0
 310 #define OP_MASK_IMMJ            0
 311 #define OP_SH_IMMJ              0
 312 #define OP_MASK_IMML            0
 313 #define OP_SH_IMML              0
 314 #define OP_MASK_IMMM            0
 315 #define OP_SH_IMMM              0
 316 #define OP_MASK_IMMN            0
 317 #define OP_SH_IMMN              0
 318 #define OP_MASK_IMMO            0
 319 #define OP_SH_IMMO              0
 320 #define OP_MASK_IMMP            0
 321 #define OP_SH_IMMP              0
 322 #define OP_MASK_IMMQ            0
 323 #define OP_SH_IMMQ              0
 324 #define OP_MASK_IMMU            0
 325 #define OP_SH_IMMU              0
 326 #define OP_MASK_IMMW            0
 327 #define OP_SH_IMMW              0
 328 #define OP_MASK_IMMX            0
 329 #define OP_SH_IMMX              0
 330 #define OP_MASK_IMMY            0
 331 #define OP_SH_IMMY              0
 332
 333 /* This structure holds information for a particular instruction.  */
 334
 335 struct mips_opcode
 336 {
 337   /* The name of the instruction.  */
 338   const char *name;
 339   /* A string describing the arguments for this instruction.  */
 340   const char *args;
 341   /* The basic opcode for the instruction.  When assembling, this
 342      opcode is modified by the arguments to produce the actual opcode
 343      that is used.  If pinfo is INSN_MACRO, then this is 0.  */
 344   unsigned long match;
 345   /* If pinfo is not INSN_MACRO, then this is a bit mask for the
 346      relevant portions of the opcode when disassembling.  If the
 347      actual opcode anded with the match field equals the opcode field,
 348      then we have found the correct instruction.  If pinfo is
 349      INSN_MACRO, then this field is the macro identifier.  */
 350   unsigned long mask;
 351   /* For a macro, this is INSN_MACRO.  Otherwise, it is a collection
 352      of bits describing the instruction, notably any relevant hazard
 353      information.  */
 354   unsigned long pinfo;
 355   /* A collection of additional bits describing the instruction. */
 356   unsigned long pinfo2;
 357   /* A collection of bits describing the instruction sets of which this
 358      instruction or macro is a member. */
 359   unsigned long membership;
 360   /* A collection of bits describing the ASE of which this instruction
 361      or macro is a member.  */
 362   unsigned long ase;
 363   /* A collection of bits describing the instruction sets of which this
 364      instruction or macro is not a member.  */
 365   unsigned long exclusions;
 366 };
 367
 368 /* These are the characters which may appear in the args field of an
 369    instruction.  They appear in the order in which the fields appear
 370    when the instruction is used.  Commas and parentheses in the args
 371    string are ignored when assembling, and written into the output
 372    when disassembling.
 373
 374    Each of these characters corresponds to a mask field defined above.
 375
 376    "1" 5 bit sync type (OP_*_SHAMT)
 377    "<" 5 bit shift amount (OP_*_SHAMT)
 378    ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
 379    "a" 26 bit target address (OP_*_TARGET)
 380    "b" 5 bit base register (OP_*_RS)
 381    "c" 10 bit breakpoint code (OP_*_CODE)
 382    "d" 5 bit destination register specifier (OP_*_RD)
 383    "h" 5 bit prefx hint (OP_*_PREFX)
 384    "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
 385    "j" 16 bit signed immediate (OP_*_DELTA)
 386    "k" 5 bit cache opcode in target register position (OP_*_CACHE)
 387        Also used for immediate operands in vr5400 vector insns.
 388    "o" 16 bit signed offset (OP_*_DELTA)
 389    "p" 16 bit PC relative branch target address (OP_*_DELTA)
 390    "q" 10 bit extra breakpoint code (OP_*_CODE2)
 391    "r" 5 bit same register used as both source and target (OP_*_RS)
 392    "s" 5 bit source register specifier (OP_*_RS)
 393    "t" 5 bit target register (OP_*_RT)
 394    "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
 395    "v" 5 bit same register used as both source and destination (OP_*_RS)
 396    "w" 5 bit same register used as both target and destination (OP_*_RT)
 397    "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
 398        (used by clo and clz)
 399    "C" 25 bit coprocessor function code (OP_*_COPZ)
 400    "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
 401    "J" 19 bit wait function code (OP_*_CODE19)
 402    "x" accept and ignore register name
 403    "z" must be zero register
 404    "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
 405    "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes
 406         LSB (OP_*_SHAMT; OP_*_EXTLSB or OP_*_STYPE may be used for
 407         microMIPS compatibility).
 408         Enforces: 0 <= pos < 32.
 409    "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB).
 410         Requires that "+A" or "+E" occur first to set position.
 411         Enforces: 0 < (pos+size) <= 32.
 412    "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD).
 413         Requires that "+A" or "+E" occur first to set position.
 414         Enforces: 0 < (pos+size) <= 32.
 415         (Also used by "dext" w/ different limits, but limits for
 416         that are checked by the M_DEXT macro.)
 417    "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT).
 418         Enforces: 32 <= pos < 64.
 419    "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB).
 420         Requires that "+A" or "+E" occur first to set position.
 421         Enforces: 32 < (pos+size) <= 64.
 422    "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
 423         Requires that "+A" or "+E" occur first to set position.
 424         Enforces: 32 < (pos+size) <= 64.
 425    "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD).
 426         Requires that "+A" or "+E" occur first to set position.
 427         Enforces: 32 < (pos+size) <= 64.
 428
 429    Floating point instructions:
 430    "D" 5 bit destination register (OP_*_FD)
 431    "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
 432    "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
 433    "S" 5 bit fs source 1 register (OP_*_FS)
 434    "T" 5 bit ft source 2 register (OP_*_FT)
 435    "R" 5 bit fr source 3 register (OP_*_FR)
 436    "V" 5 bit same register used as floating source and destination (OP_*_FS)
 437    "W" 5 bit same register used as floating target and destination (OP_*_FT)
 438
 439    Coprocessor instructions:
 440    "E" 5 bit target register (OP_*_RT)
 441    "G" 5 bit destination register (OP_*_RD)
 442    "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
 443    "P" 5 bit performance-monitor register (OP_*_PERFREG)
 444    "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
 445    "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
 446    see also "k" above
 447    "+D" Combined destination register ("G") and sel ("H") for CP0 ops,
 448         for pretty-printing in disassembly only.
 449
 450    Macro instructions:
 451    "A" General 32 bit expression
 452    "I" 32 bit immediate (value placed in imm_expr).
 453    "+I" 32 bit immediate (value placed in imm2_expr).
 454    "F" 64 bit floating point constant in .rdata
 455    "L" 64 bit floating point constant in .lit8
 456    "f" 32 bit floating point constant
 457    "l" 32 bit floating point constant in .lit4
 458
 459    MDMX instruction operands (note that while these use the FP register
 460    fields, they accept both $fN and $vN names for the registers):
 461    "O"  MDMX alignment offset (OP_*_ALN)
 462    "Q"  MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
 463    "X"  MDMX destination register (OP_*_FD)
 464    "Y"  MDMX source register (OP_*_FS)
 465    "Z"  MDMX source register (OP_*_FT)
 466
 467    DSP ASE usage:
 468    "2" 2 bit unsigned immediate for byte align (OP_*_BP)
 469    "3" 3 bit unsigned immediate (OP_*_SA3)
 470    "4" 4 bit unsigned immediate (OP_*_SA4)
 471    "5" 8 bit unsigned immediate (OP_*_IMM8)
 472    "6" 5 bit unsigned immediate (OP_*_RS)
 473    "7" 2 bit dsp accumulator register (OP_*_DSPACC)
 474    "8" 6 bit unsigned immediate (OP_*_WRDSP)
 475    "9" 2 bit dsp accumulator register (OP_*_DSPACC_S)
 476    "0" 6 bit signed immediate (OP_*_DSPSFT)
 477    ":" 7 bit signed immediate (OP_*_DSPSFT_7)
 478    "'" 6 bit unsigned immediate (OP_*_RDDSP)
 479    "@" 10 bit signed immediate (OP_*_IMM10)
 480
 481    MT ASE usage:
 482    "!" 1 bit usermode flag (OP_*_MT_U)
 483    "$" 1 bit load high flag (OP_*_MT_H)
 484    "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
 485    "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
 486    "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
 487    "+t" 5 bit coprocessor 0 destination register (OP_*_RT)
 488    "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only
 489
 490    MCU ASE usage:
 491    "~" 12 bit offset (OP_*_OFFSET12)
 492    "\" 3 bit position for aset and aclr (OP_*_3BITPOS)
 493
 494    VIRT ASE usage:
 495    "+J" 10-bit hypcall code (OP_*CODE10)
 496
 497    UDI immediates:
 498    "+1" UDI immediate bits 6-10
 499    "+2" UDI immediate bits 6-15
 500    "+3" UDI immediate bits 6-20
 501    "+4" UDI immediate bits 6-25
 502
 503    Octeon:
 504    "+x" Bit index field of bbit.  Enforces: 0 <= index < 32.
 505    "+X" Bit index field of bbit aliasing bbit32.  Matches if 32 <= index < 64,
 506         otherwise skips to next candidate.
 507    "+p" Position field of cins/cins32/exts/exts32. Enforces 0 <= pos < 32.
 508    "+P" Position field of cins/exts aliasing cins32/exts32.  Matches if
 509         32 <= pos < 64, otherwise skips to next candidate.
 510    "+Q" Immediate field of seqi/snei.  Enforces -512 <= imm < 512.
 511    "+s" Length-minus-one field of cins/exts.  Enforces: 0 <= lenm1 < 32.
 512    "+S" Length-minus-one field of cins32/exts32 or cins/exts aliasing
 513         cint32/exts32.  Enforces non-negative value and that
 514         pos + lenm1 < 32 or pos + lenm1 < 64 depending whether previous
 515         position field is "+p" or "+P".
 516
 517    Loongson-3A:
 518    "+a" 8-bit signed offset in bit 6 (OP_*_OFFSET_A)
 519    "+b" 8-bit signed offset in bit 3 (OP_*_OFFSET_B)
 520    "+c" 9-bit signed offset in bit 6 (OP_*_OFFSET_C)
 521    "+z" 5-bit rz register (OP_*_RZ)
 522    "+Z" 5-bit fz register (OP_*_FZ)
 523
 524    Other:
 525    "()" parens surrounding optional value
 526    ","  separates operands
 527    "[]" brackets around index for vector-op scalar operand specifier (vr5400)
 528    "+"  Start of extension sequence.
 529
 530    Characters used so far, for quick reference when adding more:
 531    "1234567890"
 532    "%[]<>(),+:'@!$*&\~"
 533    "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
 534    "abcdefghijklopqrstuvwxz"
 535
 536    Extension character sequences used so far ("+" followed by the
 537    following), for quick reference when adding more:
 538    "1234"
 539    "ABCDEFGHIJPQSTXZ"
 540    "abcpstxz"
 541 */
 542
 543 /* These are the bits which may be set in the pinfo field of an
 544    instructions, if it is not equal to INSN_MACRO.  */
 545
 546 /* Modifies the general purpose register in OP_*_RD.  */
 547 #define INSN_WRITE_GPR_D            0x00000001
 548 /* Modifies the general purpose register in OP_*_RT.  */
 549 #define INSN_WRITE_GPR_T            0x00000002
 550 /* Modifies general purpose register 31.  */
 551 #define INSN_WRITE_GPR_31           0x00000004
 552 /* Modifies the floating point register in OP_*_FD.  */
 553 #define INSN_WRITE_FPR_D            0x00000008
 554 /* Modifies the floating point register in OP_*_FS.  */
 555 #define INSN_WRITE_FPR_S            0x00000010
 556 /* Modifies the floating point register in OP_*_FT.  */
 557 #define INSN_WRITE_FPR_T            0x00000020
 558 /* Reads the general purpose register in OP_*_RS.  */
 559 #define INSN_READ_GPR_S             0x00000040
 560 /* Reads the general purpose register in OP_*_RT.  */
 561 #define INSN_READ_GPR_T             0x00000080
 562 /* Reads the floating point register in OP_*_FS.  */
 563 #define INSN_READ_FPR_S             0x00000100
 564 /* Reads the floating point register in OP_*_FT.  */
 565 #define INSN_READ_FPR_T             0x00000200
 566 /* Reads the floating point register in OP_*_FR.  */
 567 #define INSN_READ_FPR_R             0x00000400
 568 /* Modifies coprocessor condition code.  */
 569 #define INSN_WRITE_COND_CODE        0x00000800
 570 /* Reads coprocessor condition code.  */
 571 #define INSN_READ_COND_CODE         0x00001000
 572 /* TLB operation.  */
 573 #define INSN_TLB                    0x00002000
 574 /* Reads coprocessor register other than floating point register.  */
 575 #define INSN_COP                    0x00004000
 576 /* Instruction loads value from memory, requiring delay.  */
 577 #define INSN_LOAD_MEMORY_DELAY      0x00008000
 578 /* Instruction loads value from coprocessor, requiring delay.  */
 579 #define INSN_LOAD_COPROC_DELAY      0x00010000
 580 /* Instruction has unconditional branch delay slot.  */
 581 #define INSN_UNCOND_BRANCH_DELAY    0x00020000
 582 /* Instruction has conditional branch delay slot.  */
 583 #define INSN_COND_BRANCH_DELAY      0x00040000
 584 /* Conditional branch likely: if branch not taken, insn nullified.  */
 585 #define INSN_COND_BRANCH_LIKELY     0x00080000
 586 /* Moves to coprocessor register, requiring delay.  */
 587 #define INSN_COPROC_MOVE_DELAY      0x00100000
 588 /* Loads coprocessor register from memory, requiring delay.  */
 589 #define INSN_COPROC_MEMORY_DELAY    0x00200000
 590 /* Reads the HI register.  */
 591 #define INSN_READ_HI                0x00400000
 592 /* Reads the LO register.  */
 593 #define INSN_READ_LO                0x00800000
 594 /* Modifies the HI register.  */
 595 #define INSN_WRITE_HI               0x01000000
 596 /* Modifies the LO register.  */
 597 #define INSN_WRITE_LO               0x02000000
 598 /* Not to be placed in a branch delay slot, either architecturally
 599    or for ease of handling (such as with instructions that take a trap).  */
 600 #define INSN_NO_DELAY_SLOT          0x04000000
 601 /* Instruction stores value into memory.  */
 602 #define INSN_STORE_MEMORY           0x08000000
 603 /* Instruction uses single precision floating point.  */
 604 #define FP_S                        0x10000000
 605 /* Instruction uses double precision floating point.  */
 606 #define FP_D                        0x20000000
 607 /* Instruction is part of the tx39's integer multiply family.    */
 608 #define INSN_MULT                   0x40000000
 609 /* Modifies the general purpose register in MICROMIPSOP_*_RS.  */
 610 #define INSN_WRITE_GPR_S            0x80000000
 611 /* Instruction is actually a macro.  It should be ignored by the
 612    disassembler, and requires special treatment by the assembler.  */
 613 #define INSN_MACRO                  0xffffffff
 614
 615 /* These are the bits which may be set in the pinfo2 field of an
 616    instruction. */
 617
 618 /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
 619 #define INSN2_ALIAS                 0x00000001
 620 /* Instruction reads MDMX accumulator. */
 621 #define INSN2_READ_MDMX_ACC         0x00000002
 622 /* Instruction writes MDMX accumulator. */
 623 #define INSN2_WRITE_MDMX_ACC        0x00000004
 624 /* Macro uses single-precision floating-point instructions.  This should
 625    only be set for macros.  For instructions, FP_S in pinfo carries the
 626    same information.  */
 627 #define INSN2_M_FP_S                0x00000008
 628 /* Macro uses double-precision floating-point instructions.  This should
 629    only be set for macros.  For instructions, FP_D in pinfo carries the
 630    same information.  */
 631 #define INSN2_M_FP_D                0x00000010
 632 /* Modifies the general purpose register in OP_*_RZ.  */
 633 #define INSN2_WRITE_GPR_Z           0x00000020
 634 /* Modifies the floating point register in OP_*_FZ.  */
 635 #define INSN2_WRITE_FPR_Z           0x00000040
 636 /* Reads the general purpose register in OP_*_RZ.  */
 637 #define INSN2_READ_GPR_Z            0x00000080
 638 /* Reads the floating point register in OP_*_FZ.  */
 639 #define INSN2_READ_FPR_Z            0x00000100
 640 /* Reads the general purpose register in OP_*_RD.  */
 641 #define INSN2_READ_GPR_D            0x00000200
 642
 643
 644 /* Instruction has a branch delay slot that requires a 16-bit instruction.  */
 645 #define INSN2_BRANCH_DELAY_16BIT    0x00000400
 646 /* Instruction has a branch delay slot that requires a 32-bit instruction.  */
 647 #define INSN2_BRANCH_DELAY_32BIT    0x00000800
 648 /* Reads the floating point register in MICROMIPSOP_*_FD.  */
 649 #define INSN2_READ_FPR_D            0x00001000
 650 /* Modifies the general purpose register in MICROMIPSOP_*_MB.  */
 651 #define INSN2_WRITE_GPR_MB          0x00002000
 652 /* Reads the general purpose register in MICROMIPSOP_*_MC.  */
 653 #define INSN2_READ_GPR_MC           0x00004000
 654 /* Reads/writes the general purpose register in MICROMIPSOP_*_MD.  */
 655 #define INSN2_MOD_GPR_MD            0x00008000
 656 /* Reads the general purpose register in MICROMIPSOP_*_ME.  */
 657 #define INSN2_READ_GPR_ME           0x00010000
 658 /* Reads/writes the general purpose register in MICROMIPSOP_*_MF.  */
 659 #define INSN2_MOD_GPR_MF            0x00020000
 660 /* Reads the general purpose register in MICROMIPSOP_*_MG.  */
 661 #define INSN2_READ_GPR_MG           0x00040000
 662 /* Reads the general purpose register in MICROMIPSOP_*_MJ.  */
 663 #define INSN2_READ_GPR_MJ           0x00080000
 664 /* Modifies the general purpose register in MICROMIPSOP_*_MJ.  */
 665 #define INSN2_WRITE_GPR_MJ          0x00100000
 666 /* Reads the general purpose register in MICROMIPSOP_*_MP.  */
 667 #define INSN2_READ_GPR_MP           0x00200000
 668 /* Modifies the general purpose register in MICROMIPSOP_*_MP.  */
 669 #define INSN2_WRITE_GPR_MP          0x00400000
 670 /* Reads the general purpose register in MICROMIPSOP_*_MQ.  */
 671 #define INSN2_READ_GPR_MQ           0x00800000
 672 /* Reads/Writes the stack pointer ($29).  */
 673 #define INSN2_MOD_SP                0x01000000
 674 /* Reads the RA ($31) register.  */
 675 #define INSN2_READ_GPR_31           0x02000000
 676 /* Reads the global pointer ($28).  */
 677 #define INSN2_READ_GP               0x04000000
 678 /* Reads the program counter ($pc).  */
 679 #define INSN2_READ_PC               0x08000000
 680 /* Is an unconditional branch insn. */
 681 #define INSN2_UNCOND_BRANCH         0x10000000
 682 /* Is a conditional branch insn. */
 683 #define INSN2_COND_BRANCH           0x20000000
 684 /* Modifies the general purpose registers in MICROMIPSOP_*_MH/I.  */
 685 #define INSN2_WRITE_GPR_MHI         0x40000000
 686 /* Reads the general purpose registers in MICROMIPSOP_*_MM/N.  */
 687 #define INSN2_READ_GPR_MMN          0x80000000
 688
 689 /* Masks used to mark instructions to indicate which MIPS ISA level
 690    they were introduced in.  INSN_ISA_MASK masks an enumeration that
 691    specifies the base ISA level(s).  The remainder of a 32-bit
 692    word constructed using these macros is a bitmask of the remaining
 693    INSN_* values below.  */
 694
 695 #define INSN_ISA_MASK             0x0000000ful
 696
 697 /* We cannot start at zero due to ISA_UNKNOWN below.  */
 698 #define INSN_ISA1                 1
 699 #define INSN_ISA2                 2
 700 #define INSN_ISA3                 3
 701 #define INSN_ISA4                 4
 702 #define INSN_ISA5                 5
 703 #define INSN_ISA32                6
 704 #define INSN_ISA32R2              7
 705 #define INSN_ISA64                8
 706 #define INSN_ISA64R2              9
 707 /* Below this point the INSN_* values correspond to combinations of ISAs.
 708    They are only for use in the opcodes table to indicate membership of
 709    a combination of ISAs that cannot be expressed using the usual inclusion
 710    ordering on the above INSN_* values.  */
 711 #define INSN_ISA3_32              10
 712 #define INSN_ISA3_32R2            11
 713 #define INSN_ISA4_32              12
 714 #define INSN_ISA4_32R2            13
 715 #define INSN_ISA5_32R2            14
 716
 717 /* Given INSN_ISA* values X and Y, where X ranges over INSN_ISA1 through
 718    INSN_ISA5_32R2 and Y ranges over INSN_ISA1 through INSN_ISA64R2,
 719    this table describes whether at least one of the ISAs described by X
 720    is/are implemented by ISA Y.  (Think of Y as the ISA level supported by
 721    a particular core and X as the ISA level(s) at which a certain instruction
 722    is defined.)  The ISA(s) described by X is/are implemented by Y iff
 723    (mips_isa_table[(Y & INSN_ISA_MASK) - 1] >> ((X & INSN_ISA_MASK) - 1)) & 1
 724    is non-zero.  */
 725 static const unsigned int mips_isa_table[] =
 726   { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
 727
 728 /* Masks used for Chip specific instructions.  */
 729 #define INSN_CHIP_MASK            0xc3ff0f20
 730
 731 /* Cavium Networks Octeon instructions.  */
 732 #define INSN_OCTEON               0x00000800
 733 #define INSN_OCTEONP              0x00000200
 734 #define INSN_OCTEON2              0x00000100
 735
 736 /* Masks used for MIPS-defined ASEs.  */
 737 #define INSN_ASE_MASK             0x3c00f0d0
 738
 739 /* MIPS R5900 instruction */
 740 #define INSN_5900                 0x00004000
 741
 742 /* MIPS R4650 instruction.  */
 743 #define INSN_4650                 0x00010000
 744 /* LSI R4010 instruction.  */
 745 #define INSN_4010                 0x00020000
 746 /* NEC VR4100 instruction.  */
 747 #define INSN_4100                 0x00040000
 748 /* Toshiba R3900 instruction.  */
 749 #define INSN_3900                 0x00080000
 750 /* MIPS R10000 instruction.  */
 751 #define INSN_10000                0x00100000
 752 /* Broadcom SB-1 instruction.  */
 753 #define INSN_SB1                  0x00200000
 754 /* NEC VR4111/VR4181 instruction.  */
 755 #define INSN_4111                 0x00400000
 756 /* NEC VR4120 instruction.  */
 757 #define INSN_4120                 0x00800000
 758 /* NEC VR5400 instruction.  */
 759 #define INSN_5400                 0x01000000
 760 /* NEC VR5500 instruction.  */
 761 #define INSN_5500                 0x02000000
 762
 763 /* ST Microelectronics Loongson 2E.  */
 764 #define INSN_LOONGSON_2E          0x40000000
 765 /* ST Microelectronics Loongson 2F.  */
 766 #define INSN_LOONGSON_2F          0x80000000
 767 /* Loongson 3A.  */
 768 #define INSN_LOONGSON_3A          0x00000400
 769 /* RMI Xlr instruction */
 770 #define INSN_XLR                 0x00000020
 771
 772 /* DSP ASE */
 773 #define ASE_DSP                 0x00000001
 774 #define ASE_DSP64               0x00000002
 775 /* DSP R2 ASE  */
 776 #define ASE_DSPR2               0x00000004
 777 /* MCU (MicroController) ASE */
 778 #define ASE_MCU                 0x00000010
 779 /* MDMX ASE */
 780 #define ASE_MDMX                0x00000020
 781 /* MIPS-3D ASE */
 782 #define ASE_MIPS3D              0x00000040
 783 /* MT ASE */
 784 #define ASE_MT                  0x00000080
 785 /* SmartMIPS ASE  */
 786 #define ASE_SMARTMIPS           0x00000100
 787 /* Virtualization ASE */
 788 #define ASE_VIRT                0x00000200
 789 #define ASE_VIRT64              0x00000400
 790
 791 /* MIPS ISA defines, use instead of hardcoding ISA level.  */
 792
 793 #define       ISA_UNKNOWN     0               /* Gas internal use.  */
 794 #define       ISA_MIPS1       INSN_ISA1
 795 #define       ISA_MIPS2       INSN_ISA2
 796 #define       ISA_MIPS3       INSN_ISA3
 797 #define       ISA_MIPS4       INSN_ISA4
 798 #define       ISA_MIPS5       INSN_ISA5
 799
 800 #define       ISA_MIPS32      INSN_ISA32
 801 #define       ISA_MIPS64      INSN_ISA64
 802
 803 #define       ISA_MIPS32R2    INSN_ISA32R2
 804 #define       ISA_MIPS64R2    INSN_ISA64R2
 805
 806
 807 /* CPU defines, use instead of hardcoding processor number. Keep this
 808    in sync with bfd/archures.c in order for machine selection to work.  */
 809 #define CPU_UNKNOWN     0               /* Gas internal use.  */
 810 #define CPU_R3000       3000
 811 #define CPU_R3900       3900
 812 #define CPU_R4000       4000
 813 #define CPU_R4010       4010
 814 #define CPU_VR4100      4100
 815 #define CPU_R4111       4111
 816 #define CPU_VR4120      4120
 817 #define CPU_R4300       4300
 818 #define CPU_R4400       4400
 819 #define CPU_R4600       4600
 820 #define CPU_R4650       4650
 821 #define CPU_R5000       5000
 822 #define CPU_VR5400      5400
 823 #define CPU_VR5500      5500
 824 #define CPU_R5900       5900
 825 #define CPU_R6000       6000
 826 #define CPU_RM7000      7000
 827 #define CPU_R8000       8000
 828 #define CPU_RM9000      9000
 829 #define CPU_R10000      10000
 830 #define CPU_R12000      12000
 831 #define CPU_R14000      14000
 832 #define CPU_R16000      16000
 833 #define CPU_MIPS16      16
 834 #define CPU_MIPS32      32
 835 #define CPU_MIPS32R2    33
 836 #define CPU_MIPS5       5
 837 #define CPU_MIPS64      64
 838 #define CPU_MIPS64R2    65
 839 #define CPU_SB1         12310201        /* octal 'SB', 01.  */
 840 #define CPU_LOONGSON_2E 3001
 841 #define CPU_LOONGSON_2F 3002
 842 #define CPU_LOONGSON_3A 3003
 843 #define CPU_OCTEON      6501
 844 #define CPU_OCTEONP     6601
 845 #define CPU_OCTEON2     6502
 846 #define CPU_XLR         887682          /* decimal 'XLR'   */
 847
 848 /* Return true if the given CPU is included in INSN_* mask MASK.  */
 849
 850 static inline bfd_boolean
 851 cpu_is_member (int cpu, unsigned int mask)
 852 {
 853   switch (cpu)
 854     {
 855     case CPU_R4650:
 856     case CPU_RM7000:
 857     case CPU_RM9000:
 858       return (mask & INSN_4650) != 0;
 859
 860     case CPU_R4010:
 861       return (mask & INSN_4010) != 0;
 862
 863     case CPU_VR4100:
 864       return (mask & INSN_4100) != 0;
 865
 866     case CPU_R3900:
 867       return (mask & INSN_3900) != 0;
 868
 869     case CPU_R10000:
 870     case CPU_R12000:
 871     case CPU_R14000:
 872     case CPU_R16000:
 873       return (mask & INSN_10000) != 0;
 874
 875     case CPU_SB1:
 876       return (mask & INSN_SB1) != 0;
 877
 878     case CPU_R4111:
 879       return (mask & INSN_4111) != 0;
 880
 881     case CPU_VR4120:
 882       return (mask & INSN_4120) != 0;
 883
 884     case CPU_VR5400:
 885       return (mask & INSN_5400) != 0;
 886
 887     case CPU_VR5500:
 888       return (mask & INSN_5500) != 0;
 889
 890     case CPU_R5900:
 891       return (mask & INSN_5900) != 0;
 892
 893     case CPU_LOONGSON_2E:
 894       return (mask & INSN_LOONGSON_2E) != 0;
 895
 896     case CPU_LOONGSON_2F:
 897       return (mask & INSN_LOONGSON_2F) != 0;
 898
 899     case CPU_LOONGSON_3A:
 900       return (mask & INSN_LOONGSON_3A) != 0;
 901
 902     case CPU_OCTEON:
 903       return (mask & INSN_OCTEON) != 0;
 904
 905     case CPU_OCTEONP:
 906       return (mask & INSN_OCTEONP) != 0;
 907
 908     case CPU_OCTEON2:
 909       return (mask & INSN_OCTEON2) != 0;
 910
 911     case CPU_XLR:
 912       return (mask & INSN_XLR) != 0;
 913
 914     default:
 915       return FALSE;
 916     }
 917 }
 918
 919 /* Test for membership in an ISA including chip specific ISAs.  INSN
 920    is pointer to an element of the opcode table; ISA is the specified
 921    ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
 922    test, or zero if no CPU specific ISA test is desired.  Return true
 923    if instruction INSN is available to the given ISA and CPU. */
 924
 925 static inline bfd_boolean
 926 opcode_is_member (const struct mips_opcode *insn, int isa, int ase, int cpu)
 927 {
 928   if (!cpu_is_member (cpu, insn->exclusions))
 929     {
 930       /* Test for ISA level compatibility.  */
 931       if ((isa & INSN_ISA_MASK) != 0
 932           && (insn->membership & INSN_ISA_MASK) != 0
 933           && ((mips_isa_table[(isa & INSN_ISA_MASK) - 1]
 934                >> ((insn->membership & INSN_ISA_MASK) - 1)) & 1) != 0)
 935         return TRUE;
 936
 937       /* Test for ASE compatibility.  */
 938       if ((ase & insn->ase) != 0)
 939         return TRUE;
 940
 941       /* Test for processor-specific extensions.  */
 942       if (cpu_is_member (cpu, insn->membership))
 943         return TRUE;
 944     }
 945   return FALSE;
 946 }
 947
 948 /* This is a list of macro expanded instructions.
 949
 950    _I appended means immediate
 951    _A appended means address
 952    _AB appended means address with base register
 953    _D appended means 64 bit floating point constant
 954    _S appended means 32 bit floating point constant.  */
 955
 956 enum
 957 {
 958   M_ABS,
 959   M_ACLR_AB,
 960   M_ACLR_OB,
 961   M_ADD_I,
 962   M_ADDU_I,
 963   M_AND_I,
 964   M_ASET_AB,
 965   M_ASET_OB,
 966   M_BALIGN,
 967   M_BC1FL,
 968   M_BC1TL,
 969   M_BC2FL,
 970   M_BC2TL,
 971   M_BEQ,
 972   M_BEQ_I,
 973   M_BEQL,
 974   M_BEQL_I,
 975   M_BGE,
 976   M_BGEL,
 977   M_BGE_I,
 978   M_BGEL_I,
 979   M_BGEU,
 980   M_BGEUL,
 981   M_BGEU_I,
 982   M_BGEUL_I,
 983   M_BGEZ,
 984   M_BGEZL,
 985   M_BGEZALL,
 986   M_BGT,
 987   M_BGTL,
 988   M_BGT_I,
 989   M_BGTL_I,
 990   M_BGTU,
 991   M_BGTUL,
 992   M_BGTU_I,
 993   M_BGTUL_I,
 994   M_BGTZ,
 995   M_BGTZL,
 996   M_BLE,
 997   M_BLEL,
 998   M_BLE_I,
 999   M_BLEL_I,
1000   M_BLEU,
1001   M_BLEUL,
1002   M_BLEU_I,
1003   M_BLEUL_I,
1004   M_BLEZ,
1005   M_BLEZL,
1006   M_BLT,
1007   M_BLTL,
1008   M_BLT_I,
1009   M_BLTL_I,
1010   M_BLTU,
1011   M_BLTUL,
1012   M_BLTU_I,
1013   M_BLTUL_I,
1014   M_BLTZ,
1015   M_BLTZL,
1016   M_BLTZALL,
1017   M_BNE,
1018   M_BNEL,
1019   M_BNE_I,
1020   M_BNEL_I,
1021   M_CACHE_AB,
1022   M_CACHE_OB,
1023   M_DABS,
1024   M_DADD_I,
1025   M_DADDU_I,
1026   M_DDIV_3,
1027   M_DDIV_3I,
1028   M_DDIVU_3,
1029   M_DDIVU_3I,
1030   M_DEXT,
1031   M_DINS,
1032   M_DIV_3,
1033   M_DIV_3I,
1034   M_DIVU_3,
1035   M_DIVU_3I,
1036   M_DLA_AB,
1037   M_DLCA_AB,
1038   M_DLI,
1039   M_DMUL,
1040   M_DMUL_I,
1041   M_DMULO,
1042   M_DMULO_I,
1043   M_DMULOU,
1044   M_DMULOU_I,
1045   M_DREM_3,
1046   M_DREM_3I,
1047   M_DREMU_3,
1048   M_DREMU_3I,
1049   M_DSUB_I,
1050   M_DSUBU_I,
1051   M_DSUBU_I_2,
1052   M_J_A,
1053   M_JAL_1,
1054   M_JAL_2,
1055   M_JAL_A,
1056   M_JALS_1,
1057   M_JALS_2,
1058   M_JALS_A,
1059   M_L_DOB,
1060   M_L_DAB,
1061   M_LA_AB,
1062   M_LB_A,
1063   M_LB_AB,
1064   M_LBU_A,
1065   M_LBU_AB,
1066   M_LCA_AB,
1067   M_LD_A,
1068   M_LD_OB,
1069   M_LD_AB,
1070   M_LDC1_AB,
1071   M_LDC2_AB,
1072   M_LDC2_OB,
1073   M_LQC2_AB,
1074   M_LDC3_AB,
1075   M_LDL_AB,
1076   M_LDL_OB,
1077   M_LDM_AB,
1078   M_LDM_OB,
1079   M_LDP_AB,
1080   M_LDP_OB,
1081   M_LDR_AB,
1082   M_LDR_OB,
1083   M_LH_A,
1084   M_LH_AB,
1085   M_LHU_A,
1086   M_LHU_AB,
1087   M_LI,
1088   M_LI_D,
1089   M_LI_DD,
1090   M_LI_S,
1091   M_LI_SS,
1092   M_LL_AB,
1093   M_LL_OB,
1094   M_LLD_AB,
1095   M_LLD_OB,
1096   M_LQ_AB,
1097   M_LS_A,
1098   M_LW_A,
1099   M_LW_AB,
1100   M_LWC0_A,
1101   M_LWC0_AB,
1102   M_LWC1_A,
1103   M_LWC1_AB,
1104   M_LWC2_A,
1105   M_LWC2_AB,
1106   M_LWC2_OB,
1107   M_LWC3_A,
1108   M_LWC3_AB,
1109   M_LWL_A,
1110   M_LWL_AB,
1111   M_LWL_OB,
1112   M_LWM_AB,
1113   M_LWM_OB,
1114   M_LWP_AB,
1115   M_LWP_OB,
1116   M_LWR_A,
1117   M_LWR_AB,
1118   M_LWR_OB,
1119   M_LWU_AB,
1120   M_LWU_OB,
1121   M_MSGSND,
1122   M_MSGLD,
1123   M_MSGLD_T,
1124   M_MSGWAIT,
1125   M_MSGWAIT_T,
1126   M_MOVE,
1127   M_MUL,
1128   M_MUL_I,
1129   M_MULO,
1130   M_MULO_I,
1131   M_MULOU,
1132   M_MULOU_I,
1133   M_NOR_I,
1134   M_OR_I,
1135   M_PREF_AB,
1136   M_PREF_OB,
1137   M_REM_3,
1138   M_REM_3I,
1139   M_REMU_3,
1140   M_REMU_3I,
1141   M_DROL,
1142   M_ROL,
1143   M_DROL_I,
1144   M_ROL_I,
1145   M_DROR,
1146   M_ROR,
1147   M_DROR_I,
1148   M_ROR_I,
1149   M_S_DA,
1150   M_S_DOB,
1151   M_S_DAB,
1152   M_S_S,
1153   M_SAA_AB,
1154   M_SAA_OB,
1155   M_SAAD_AB,
1156   M_SAAD_OB,
1157   M_SC_AB,
1158   M_SC_OB,
1159   M_SCD_AB,
1160   M_SCD_OB,
1161   M_SD_A,
1162   M_SD_OB,
1163   M_SD_AB,
1164   M_SDC1_AB,
1165   M_SDC2_AB,
1166   M_SDC2_OB,
1167   M_SQC2_AB,
1168   M_SDC3_AB,
1169   M_SDL_AB,
1170   M_SDL_OB,
1171   M_SDM_AB,
1172   M_SDM_OB,
1173   M_SDP_AB,
1174   M_SDP_OB,
1175   M_SDR_AB,
1176   M_SDR_OB,
1177   M_SEQ,
1178   M_SEQ_I,
1179   M_SGE,
1180   M_SGE_I,
1181   M_SGEU,
1182   M_SGEU_I,
1183   M_SGT,
1184   M_SGT_I,
1185   M_SGTU,
1186   M_SGTU_I,
1187   M_SLE,
1188   M_SLE_I,
1189   M_SLEU,
1190   M_SLEU_I,
1191   M_SLT_I,
1192   M_SLTU_I,
1193   M_SNE,
1194   M_SNE_I,
1195   M_SB_A,
1196   M_SB_AB,
1197   M_SH_A,
1198   M_SH_AB,
1199   M_SQ_AB,
1200   M_SW_A,
1201   M_SW_AB,
1202   M_SWC0_A,
1203   M_SWC0_AB,
1204   M_SWC1_A,
1205   M_SWC1_AB,
1206   M_SWC2_A,
1207   M_SWC2_AB,
1208   M_SWC2_OB,
1209   M_SWC3_A,
1210   M_SWC3_AB,
1211   M_SWL_A,
1212   M_SWL_AB,
1213   M_SWL_OB,
1214   M_SWM_AB,
1215   M_SWM_OB,
1216   M_SWP_AB,
1217   M_SWP_OB,
1218   M_SWR_A,
1219   M_SWR_AB,
1220   M_SWR_OB,
1221   M_SUB_I,
1222   M_SUBU_I,
1223   M_SUBU_I_2,
1224   M_TEQ_I,
1225   M_TGE_I,
1226   M_TGEU_I,
1227   M_TLT_I,
1228   M_TLTU_I,
1229   M_TNE_I,
1230   M_TRUNCWD,
1231   M_TRUNCWS,
1232   M_ULD,
1233   M_ULD_A,
1234   M_ULH,
1235   M_ULH_A,
1236   M_ULHU,
1237   M_ULHU_A,
1238   M_ULW,
1239   M_ULW_A,
1240   M_USH,
1241   M_USH_A,
1242   M_USW,
1243   M_USW_A,
1244   M_USD,
1245   M_USD_A,
1246   M_XOR_I,
1247   M_COP0,
1248   M_COP1,
1249   M_COP2,
1250   M_COP3,
1251   M_NUM_MACROS
1252 };
1253
1254
1255 /* The order of overloaded instructions matters.  Label arguments and
1256    register arguments look the same. Instructions that can have either
1257    for arguments must apear in the correct order in this table for the
1258    assembler to pick the right one. In other words, entries with
1259    immediate operands must apear after the same instruction with
1260    registers.
1261
1262    Many instructions are short hand for other instructions (i.e., The
1263    jal <register> instruction is short for jalr <register>).  */
1264
1265 extern const struct mips_opcode mips_builtin_opcodes[];
1266 extern const int bfd_mips_num_builtin_opcodes;
1267 extern struct mips_opcode *mips_opcodes;
1268 extern int bfd_mips_num_opcodes;
1269 #define NUMOPCODES bfd_mips_num_opcodes
1270
1271 \f
1272 /* The rest of this file adds definitions for the mips16 TinyRISC
1273    processor.  */
1274
1275 /* These are the bitmasks and shift counts used for the different
1276    fields in the instruction formats.  Other than OP, no masks are
1277    provided for the fixed portions of an instruction, since they are
1278    not needed.
1279
1280    The I format uses IMM11.
1281
1282    The RI format uses RX and IMM8.
1283
1284    The RR format uses RX, and RY.
1285
1286    The RRI format uses RX, RY, and IMM5.
1287
1288    The RRR format uses RX, RY, and RZ.
1289
1290    The RRI_A format uses RX, RY, and IMM4.
1291
1292    The SHIFT format uses RX, RY, and SHAMT.
1293
1294    The I8 format uses IMM8.
1295
1296    The I8_MOVR32 format uses RY and REGR32.
1297
1298    The IR_MOV32R format uses REG32R and MOV32Z.
1299
1300    The I64 format uses IMM8.
1301
1302    The RI64 format uses RY and IMM5.
1303    */
1304
1305 #define MIPS16OP_MASK_OP        0x1f
1306 #define MIPS16OP_SH_OP          11
1307 #define MIPS16OP_MASK_IMM11     0x7ff
1308 #define MIPS16OP_SH_IMM11       0
1309 #define MIPS16OP_MASK_RX        0x7
1310 #define MIPS16OP_SH_RX          8
1311 #define MIPS16OP_MASK_IMM8      0xff
1312 #define MIPS16OP_SH_IMM8        0
1313 #define MIPS16OP_MASK_RY        0x7
1314 #define MIPS16OP_SH_RY          5
1315 #define MIPS16OP_MASK_IMM5      0x1f
1316 #define MIPS16OP_SH_IMM5        0
1317 #define MIPS16OP_MASK_RZ        0x7
1318 #define MIPS16OP_SH_RZ          2
1319 #define MIPS16OP_MASK_IMM4      0xf
1320 #define MIPS16OP_SH_IMM4        0
1321 #define MIPS16OP_MASK_REGR32    0x1f
1322 #define MIPS16OP_SH_REGR32      0
1323 #define MIPS16OP_MASK_REG32R    0x1f
1324 #define MIPS16OP_SH_REG32R      3
1325 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
1326 #define MIPS16OP_MASK_MOVE32Z   0x7
1327 #define MIPS16OP_SH_MOVE32Z     0
1328 #define MIPS16OP_MASK_IMM6      0x3f
1329 #define MIPS16OP_SH_IMM6        5
1330
1331 /* These are the characters which may appears in the args field of a MIPS16
1332    instruction.  They appear in the order in which the fields appear when the
1333    instruction is used.  Commas and parentheses in the args string are ignored
1334    when assembling, and written into the output when disassembling.
1335
1336    "y" 3 bit register (MIPS16OP_*_RY)
1337    "x" 3 bit register (MIPS16OP_*_RX)
1338    "z" 3 bit register (MIPS16OP_*_RZ)
1339    "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
1340    "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
1341    "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
1342    "0" zero register ($0)
1343    "S" stack pointer ($sp or $29)
1344    "P" program counter
1345    "R" return address register ($ra or $31)
1346    "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
1347    "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
1348    "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
1349    "a" 26 bit jump address
1350    "e" 11 bit extension value
1351    "l" register list for entry instruction
1352    "L" register list for exit instruction
1353
1354    The remaining codes may be extended.  Except as otherwise noted,
1355    the full extended operand is a 16 bit signed value.
1356    "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
1357    ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
1358    "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
1359    "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
1360    "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
1361    "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
1362    "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
1363    "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
1364    "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
1365    "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
1366    "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
1367    "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
1368    "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
1369    "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
1370    "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
1371    "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
1372    "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
1373    "q" 11 bit branch address (MIPS16OP_*_IMM11)
1374    "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
1375    "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
1376    "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
1377    "m" 7 bit register list for save instruction (18 bit extended)
1378    "M" 7 bit register list for restore instruction (18 bit extended)
1379   */
1380
1381 /* Save/restore encoding for the args field when all 4 registers are
1382    either saved as arguments or saved/restored as statics.  */
1383 #define MIPS16_ALL_ARGS    0xe
1384 #define MIPS16_ALL_STATICS 0xb
1385
1386 /* For the mips16, we use the same opcode table format and a few of
1387    the same flags.  However, most of the flags are different.  */
1388
1389 /* Modifies the register in MIPS16OP_*_RX.  */
1390 #define MIPS16_INSN_WRITE_X                 0x00000001
1391 /* Modifies the register in MIPS16OP_*_RY.  */
1392 #define MIPS16_INSN_WRITE_Y                 0x00000002
1393 /* Modifies the register in MIPS16OP_*_RZ.  */
1394 #define MIPS16_INSN_WRITE_Z                 0x00000004
1395 /* Modifies the T ($24) register.  */
1396 #define MIPS16_INSN_WRITE_T                 0x00000008
1397 /* Modifies the SP ($29) register.  */
1398 #define MIPS16_INSN_WRITE_SP                0x00000010
1399 /* Modifies the RA ($31) register.  */
1400 #define MIPS16_INSN_WRITE_31                0x00000020
1401 /* Modifies the general purpose register in MIPS16OP_*_REG32R.  */
1402 #define MIPS16_INSN_WRITE_GPR_Y             0x00000040
1403 /* Reads the register in MIPS16OP_*_RX.  */
1404 #define MIPS16_INSN_READ_X                  0x00000080
1405 /* Reads the register in MIPS16OP_*_RY.  */
1406 #define MIPS16_INSN_READ_Y                  0x00000100
1407 /* Reads the register in MIPS16OP_*_MOVE32Z.  */
1408 #define MIPS16_INSN_READ_Z                  0x00000200
1409 /* Reads the T ($24) register.  */
1410 #define MIPS16_INSN_READ_T                  0x00000400
1411 /* Reads the SP ($29) register.  */
1412 #define MIPS16_INSN_READ_SP                 0x00000800
1413 /* Reads the RA ($31) register.  */
1414 #define MIPS16_INSN_READ_31                 0x00001000
1415 /* Reads the program counter.  */
1416 #define MIPS16_INSN_READ_PC                 0x00002000
1417 /* Reads the general purpose register in MIPS16OP_*_REGR32.  */
1418 #define MIPS16_INSN_READ_GPR_X              0x00004000
1419 /* Is an unconditional branch insn. */
1420 #define MIPS16_INSN_UNCOND_BRANCH           0x00008000
1421 /* Is a conditional branch insn. */
1422 #define MIPS16_INSN_COND_BRANCH             0x00010000
1423
1424 /* The following flags have the same value for the mips16 opcode
1425    table:
1426
1427    INSN_ISA3
1428
1429    INSN_UNCOND_BRANCH_DELAY
1430    INSN_COND_BRANCH_DELAY
1431    INSN_COND_BRANCH_LIKELY (never used)
1432    INSN_READ_HI
1433    INSN_READ_LO
1434    INSN_WRITE_HI
1435    INSN_WRITE_LO
1436    INSN_TRAP
1437    FP_D (never used)
1438    */
1439
1440 extern const struct mips_opcode mips16_opcodes[];
1441 extern const int bfd_mips16_num_opcodes;
1442
1443 /* These are the bit masks and shift counts used for the different fields
1444    in the microMIPS instruction formats.  No masks are provided for the
1445    fixed portions of an instruction, since they are not needed.  */
1446
1447 #define MICROMIPSOP_MASK_IMMEDIATE      0xffff
1448 #define MICROMIPSOP_SH_IMMEDIATE        0
1449 #define MICROMIPSOP_MASK_DELTA          0xffff
1450 #define MICROMIPSOP_SH_DELTA            0
1451 #define MICROMIPSOP_MASK_CODE10         0x3ff
1452 #define MICROMIPSOP_SH_CODE10           16      /* 10-bit wait code.  */
1453 #define MICROMIPSOP_MASK_TRAP           0xf
1454 #define MICROMIPSOP_SH_TRAP             12      /* 4-bit trap code.  */
1455 #define MICROMIPSOP_MASK_SHAMT          0x1f
1456 #define MICROMIPSOP_SH_SHAMT            11
1457 #define MICROMIPSOP_MASK_TARGET         0x3ffffff
1458 #define MICROMIPSOP_SH_TARGET           0
1459 #define MICROMIPSOP_MASK_EXTLSB         0x1f    /* "ext" LSB.  */
1460 #define MICROMIPSOP_SH_EXTLSB           6
1461 #define MICROMIPSOP_MASK_EXTMSBD        0x1f    /* "ext" MSBD.  */
1462 #define MICROMIPSOP_SH_EXTMSBD          11
1463 #define MICROMIPSOP_MASK_INSMSB         0x1f    /* "ins" MSB.  */
1464 #define MICROMIPSOP_SH_INSMSB           11
1465 #define MICROMIPSOP_MASK_CODE           0x3ff
1466 #define MICROMIPSOP_SH_CODE             16      /* 10-bit higher break code. */
1467 #define MICROMIPSOP_MASK_CODE2          0x3ff
1468 #define MICROMIPSOP_SH_CODE2            6       /* 10-bit lower break code.  */
1469 #define MICROMIPSOP_MASK_CACHE          0x1f
1470 #define MICROMIPSOP_SH_CACHE            21      /* 5-bit cache op.  */
1471 #define MICROMIPSOP_MASK_SEL            0x7
1472 #define MICROMIPSOP_SH_SEL              11
1473 #define MICROMIPSOP_MASK_OFFSET12       0xfff
1474 #define MICROMIPSOP_SH_OFFSET12         0
1475 #define MICROMIPSOP_MASK_3BITPOS        0x7
1476 #define MICROMIPSOP_SH_3BITPOS          21
1477 #define MICROMIPSOP_MASK_STYPE          0x1f
1478 #define MICROMIPSOP_SH_STYPE            16
1479 #define MICROMIPSOP_MASK_OFFSET10       0x3ff
1480 #define MICROMIPSOP_SH_OFFSET10         6
1481 #define MICROMIPSOP_MASK_RS             0x1f
1482 #define MICROMIPSOP_SH_RS               16
1483 #define MICROMIPSOP_MASK_RT             0x1f
1484 #define MICROMIPSOP_SH_RT               21
1485 #define MICROMIPSOP_MASK_RD             0x1f
1486 #define MICROMIPSOP_SH_RD               11
1487 #define MICROMIPSOP_MASK_FS             0x1f
1488 #define MICROMIPSOP_SH_FS               16
1489 #define MICROMIPSOP_MASK_FT             0x1f
1490 #define MICROMIPSOP_SH_FT               21
1491 #define MICROMIPSOP_MASK_FD             0x1f
1492 #define MICROMIPSOP_SH_FD               11
1493 #define MICROMIPSOP_MASK_FR             0x1f
1494 #define MICROMIPSOP_SH_FR               6
1495 #define MICROMIPSOP_MASK_RS3            0x1f
1496 #define MICROMIPSOP_SH_RS3              6
1497 #define MICROMIPSOP_MASK_PREFX          0x1f
1498 #define MICROMIPSOP_SH_PREFX            11
1499 #define MICROMIPSOP_MASK_BCC            0x7
1500 #define MICROMIPSOP_SH_BCC              18
1501 #define MICROMIPSOP_MASK_CCC            0x7
1502 #define MICROMIPSOP_SH_CCC              13
1503 #define MICROMIPSOP_MASK_COPZ           0x7fffff
1504 #define MICROMIPSOP_SH_COPZ             3
1505
1506 #define MICROMIPSOP_MASK_MB             0x7
1507 #define MICROMIPSOP_SH_MB               23
1508 #define MICROMIPSOP_MASK_MC             0x7
1509 #define MICROMIPSOP_SH_MC               4
1510 #define MICROMIPSOP_MASK_MD             0x7
1511 #define MICROMIPSOP_SH_MD               7
1512 #define MICROMIPSOP_MASK_ME             0x7
1513 #define MICROMIPSOP_SH_ME               1
1514 #define MICROMIPSOP_MASK_MF             0x7
1515 #define MICROMIPSOP_SH_MF               3
1516 #define MICROMIPSOP_MASK_MG             0x7
1517 #define MICROMIPSOP_SH_MG               0
1518 #define MICROMIPSOP_MASK_MH             0x7
1519 #define MICROMIPSOP_SH_MH               7
1520 #define MICROMIPSOP_MASK_MI             0x7
1521 #define MICROMIPSOP_SH_MI               7
1522 #define MICROMIPSOP_MASK_MJ             0x1f
1523 #define MICROMIPSOP_SH_MJ               0
1524 #define MICROMIPSOP_MASK_ML             0x7
1525 #define MICROMIPSOP_SH_ML               4
1526 #define MICROMIPSOP_MASK_MM             0x7
1527 #define MICROMIPSOP_SH_MM               1
1528 #define MICROMIPSOP_MASK_MN             0x7
1529 #define MICROMIPSOP_SH_MN               4
1530 #define MICROMIPSOP_MASK_MP             0x1f
1531 #define MICROMIPSOP_SH_MP               5
1532 #define MICROMIPSOP_MASK_MQ             0x7
1533 #define MICROMIPSOP_SH_MQ               7
1534
1535 #define MICROMIPSOP_MASK_IMMA           0x7f
1536 #define MICROMIPSOP_SH_IMMA             0
1537 #define MICROMIPSOP_MASK_IMMB           0x7
1538 #define MICROMIPSOP_SH_IMMB             1
1539 #define MICROMIPSOP_MASK_IMMC           0xf
1540 #define MICROMIPSOP_SH_IMMC             0
1541 #define MICROMIPSOP_MASK_IMMD           0x3ff
1542 #define MICROMIPSOP_SH_IMMD             0
1543 #define MICROMIPSOP_MASK_IMME           0x7f
1544 #define MICROMIPSOP_SH_IMME             0
1545 #define MICROMIPSOP_MASK_IMMF           0xf
1546 #define MICROMIPSOP_SH_IMMF             0
1547 #define MICROMIPSOP_MASK_IMMG           0xf
1548 #define MICROMIPSOP_SH_IMMG             0
1549 #define MICROMIPSOP_MASK_IMMH           0xf
1550 #define MICROMIPSOP_SH_IMMH             0
1551 #define MICROMIPSOP_MASK_IMMI           0x7f
1552 #define MICROMIPSOP_SH_IMMI             0
1553 #define MICROMIPSOP_MASK_IMMJ           0xf
1554 #define MICROMIPSOP_SH_IMMJ             0
1555 #define MICROMIPSOP_MASK_IMML           0xf
1556 #define MICROMIPSOP_SH_IMML             0
1557 #define MICROMIPSOP_MASK_IMMM           0x7
1558 #define MICROMIPSOP_SH_IMMM             1
1559 #define MICROMIPSOP_MASK_IMMN           0x3
1560 #define MICROMIPSOP_SH_IMMN             4
1561 #define MICROMIPSOP_MASK_IMMO           0xf
1562 #define MICROMIPSOP_SH_IMMO             0
1563 #define MICROMIPSOP_MASK_IMMP           0x1f
1564 #define MICROMIPSOP_SH_IMMP             0
1565 #define MICROMIPSOP_MASK_IMMQ           0x7fffff
1566 #define MICROMIPSOP_SH_IMMQ             0
1567 #define MICROMIPSOP_MASK_IMMU           0x1f
1568 #define MICROMIPSOP_SH_IMMU             0
1569 #define MICROMIPSOP_MASK_IMMW           0x3f
1570 #define MICROMIPSOP_SH_IMMW             1
1571 #define MICROMIPSOP_MASK_IMMX           0xf
1572 #define MICROMIPSOP_SH_IMMX             1
1573 #define MICROMIPSOP_MASK_IMMY           0x1ff
1574 #define MICROMIPSOP_SH_IMMY             1
1575
1576 /* MIPS DSP ASE */
1577 #define MICROMIPSOP_MASK_DSPACC         0x3
1578 #define MICROMIPSOP_SH_DSPACC           14
1579 #define MICROMIPSOP_MASK_DSPSFT         0x3f
1580 #define MICROMIPSOP_SH_DSPSFT           16
1581 #define MICROMIPSOP_MASK_SA3            0x7
1582 #define MICROMIPSOP_SH_SA3              13
1583 #define MICROMIPSOP_MASK_SA4            0xf
1584 #define MICROMIPSOP_SH_SA4              12
1585 #define MICROMIPSOP_MASK_IMM8           0xff
1586 #define MICROMIPSOP_SH_IMM8             13
1587 #define MICROMIPSOP_MASK_IMM10          0x3ff
1588 #define MICROMIPSOP_SH_IMM10            16
1589 #define MICROMIPSOP_MASK_WRDSP          0x3f
1590 #define MICROMIPSOP_SH_WRDSP            14
1591 #define MICROMIPSOP_MASK_BP             0x3
1592 #define MICROMIPSOP_SH_BP               14
1593
1594 /* Placeholders for fields that only exist in the traditional 32-bit
1595    instruction encoding; see the comment above for details.  */
1596 #define MICROMIPSOP_MASK_CODE20         0
1597 #define MICROMIPSOP_SH_CODE20           0
1598 #define MICROMIPSOP_MASK_PERFREG        0
1599 #define MICROMIPSOP_SH_PERFREG          0
1600 #define MICROMIPSOP_MASK_CODE19         0
1601 #define MICROMIPSOP_SH_CODE19           0
1602 #define MICROMIPSOP_MASK_ALN            0
1603 #define MICROMIPSOP_SH_ALN              0
1604 #define MICROMIPSOP_MASK_VECBYTE        0
1605 #define MICROMIPSOP_SH_VECBYTE          0
1606 #define MICROMIPSOP_MASK_VECALIGN       0
1607 #define MICROMIPSOP_SH_VECALIGN         0
1608 #define MICROMIPSOP_MASK_DSPACC_S       0
1609 #define MICROMIPSOP_SH_DSPACC_S         0
1610 #define MICROMIPSOP_MASK_DSPSFT_7       0
1611 #define MICROMIPSOP_SH_DSPSFT_7         0
1612 #define MICROMIPSOP_MASK_RDDSP          0
1613 #define MICROMIPSOP_SH_RDDSP            0
1614 #define MICROMIPSOP_MASK_MT_U           0
1615 #define MICROMIPSOP_SH_MT_U             0
1616 #define MICROMIPSOP_MASK_MT_H           0
1617 #define MICROMIPSOP_SH_MT_H             0
1618 #define MICROMIPSOP_MASK_MTACC_T        0
1619 #define MICROMIPSOP_SH_MTACC_T          0
1620 #define MICROMIPSOP_MASK_MTACC_D        0
1621 #define MICROMIPSOP_SH_MTACC_D          0
1622 #define MICROMIPSOP_MASK_BBITIND        0
1623 #define MICROMIPSOP_SH_BBITIND          0
1624 #define MICROMIPSOP_MASK_CINSPOS        0
1625 #define MICROMIPSOP_SH_CINSPOS          0
1626 #define MICROMIPSOP_MASK_CINSLM1        0
1627 #define MICROMIPSOP_SH_CINSLM1          0
1628 #define MICROMIPSOP_MASK_SEQI           0
1629 #define MICROMIPSOP_SH_SEQI             0
1630 #define MICROMIPSOP_SH_OFFSET_A         0
1631 #define MICROMIPSOP_MASK_OFFSET_A       0
1632 #define MICROMIPSOP_SH_OFFSET_B         0
1633 #define MICROMIPSOP_MASK_OFFSET_B       0
1634 #define MICROMIPSOP_SH_OFFSET_C         0
1635 #define MICROMIPSOP_MASK_OFFSET_C       0
1636 #define MICROMIPSOP_SH_RZ               0
1637 #define MICROMIPSOP_MASK_RZ             0
1638 #define MICROMIPSOP_SH_FZ               0
1639 #define MICROMIPSOP_MASK_FZ             0
1640
1641 /* These are the characters which may appears in the args field of a microMIPS
1642    instruction.  They appear in the order in which the fields appear
1643    when the instruction is used.  Commas and parentheses in the args
1644    string are ignored when assembling, and written into the output
1645    when disassembling.
1646
1647    The followings are for 16-bit microMIPS instructions.
1648
1649    "ma" must be $28
1650    "mc" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MC) at bit 4
1651         The same register used as both source and target.
1652    "md" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MD) at bit 7
1653    "me" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ME) at bit 1
1654         The same register used as both source and target.
1655    "mf" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MF) at bit 3
1656    "mg" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MG) at bit 0
1657    "mh" MIPS registers 4, 5, 6 (MICROMIPSOP_*_MH) at bit 7
1658    "mi" MIPS registers 5, 6, 7, 21, 22 (MICROMIPSOP_*_MI) at bit 7
1659         ("mh" and "mi" form a valid 3-bit register pair)
1660    "mj" 5-bit MIPS registers (MICROMIPSOP_*_MJ) at bit 0
1661    "ml" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ML) at bit 4
1662    "mm" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MM) at bit 1
1663    "mn" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MN) at bit 4
1664    "mp" 5-bit MIPS registers (MICROMIPSOP_*_MP) at bit 5
1665    "mq" 3-bit MIPS registers 0, 2-7, 17 (MICROMIPSOP_*_MQ) at bit 7
1666    "mr" must be program counter
1667    "ms" must be $29
1668    "mt" must be the same as the previous register
1669    "mx" must be the same as the destination register
1670    "my" must be $31
1671    "mz" must be $0
1672
1673    "mA" 7-bit immediate (-64 .. 63) << 2 (MICROMIPSOP_*_IMMA)
1674    "mB" 3-bit immediate (-1, 1, 4, 8, 12, 16, 20, 24) (MICROMIPSOP_*_IMMB)
1675    "mC" 4-bit immediate (1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 128, 255,
1676         32768, 65535) (MICROMIPSOP_*_IMMC)
1677    "mD" 10-bit branch address (-512 .. 511) << 1 (MICROMIPSOP_*_IMMD)
1678    "mE" 7-bit branch address (-64 .. 63) << 1 (MICROMIPSOP_*_IMME)
1679    "mF" 4-bit immediate (0 .. 15)  (MICROMIPSOP_*_IMMF)
1680    "mG" 4-bit immediate (-1 .. 14) (MICROMIPSOP_*_IMMG)
1681    "mH" 4-bit immediate (0 .. 15) << 1 (MICROMIPSOP_*_IMMH)
1682    "mI" 7-bit immediate (-1 .. 126) (MICROMIPSOP_*_IMMI)
1683    "mJ" 4-bit immediate (0 .. 15) << 2 (MICROMIPSOP_*_IMMJ)
1684    "mL" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML)
1685    "mM" 3-bit immediate (1 .. 8) (MICROMIPSOP_*_IMMM)
1686    "mN" 2-bit immediate (0 .. 3) for register list (MICROMIPSOP_*_IMMN)
1687    "mO" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML)
1688    "mP" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMP)
1689    "mU" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMU)
1690    "mW" 6-bit immediate (0 .. 63) << 2 (MICROMIPSOP_*_IMMW)
1691    "mX" 4-bit immediate (-8 .. 7) (MICROMIPSOP_*_IMMX)
1692    "mY" 9-bit immediate (-258 .. -3, 2 .. 257) << 2 (MICROMIPSOP_*_IMMY)
1693    "mZ" must be zero
1694
1695    In most cases 32-bit microMIPS instructions use the same characters
1696    as MIPS (with ADDIUPC being a notable exception, but there are some
1697    others too).
1698
1699    "." 10-bit signed offset/number (MICROMIPSOP_*_OFFSET10)
1700    "1" 5-bit sync type (MICROMIPSOP_*_SHAMT)
1701    "<" 5-bit shift amount (MICROMIPSOP_*_SHAMT)
1702    ">" shift amount between 32 and 63, stored after subtracting 32
1703        (MICROMIPSOP_*_SHAMT)
1704    "\" 3-bit position for ASET and ACLR (MICROMIPSOP_*_3BITPOS)
1705    "|" 4-bit trap code (MICROMIPSOP_*_TRAP)
1706    "~" 12-bit signed offset (MICROMIPSOP_*_OFFSET12)
1707    "a" 26-bit target address (MICROMIPSOP_*_TARGET)
1708    "b" 5-bit base register (MICROMIPSOP_*_RS)
1709    "c" 10-bit higher breakpoint code (MICROMIPSOP_*_CODE)
1710    "d" 5-bit destination register specifier (MICROMIPSOP_*_RD)
1711    "h" 5-bit PREFX hint (MICROMIPSOP_*_PREFX)
1712    "i" 16-bit unsigned immediate (MICROMIPSOP_*_IMMEDIATE)
1713    "j" 16-bit signed immediate (MICROMIPSOP_*_DELTA)
1714    "k" 5-bit cache opcode in target register position (MICROMIPSOP_*_CACHE)
1715    "n" register list for 32-bit LWM/SWM instruction (MICROMIPSOP_*_RT)
1716    "o" 16-bit signed offset (MICROMIPSOP_*_DELTA)
1717    "p" 16-bit PC-relative branch target address (MICROMIPSOP_*_DELTA)
1718    "q" 10-bit lower breakpoint code (MICROMIPSOP_*_CODE2)
1719    "r" 5-bit same register used as both source and target (MICROMIPSOP_*_RS)
1720    "s" 5-bit source register specifier (MICROMIPSOP_*_RS)
1721    "t" 5-bit target register (MICROMIPSOP_*_RT)
1722    "u" 16-bit upper 16 bits of address (MICROMIPSOP_*_IMMEDIATE)
1723    "v" 5-bit same register used as both source and destination
1724        (MICROMIPSOP_*_RS)
1725    "w" 5-bit same register used as both target and destination
1726        (MICROMIPSOP_*_RT)
1727    "y" 5-bit source 3 register for ALNV.PS (MICROMIPSOP_*_RS3)
1728    "z" must be zero register
1729    "C" 23-bit coprocessor function code (MICROMIPSOP_*_COPZ)
1730    "B" 10-bit syscall/wait function code (MICROMIPSOP_*_CODE10)
1731    "K" 5-bit Hardware Register (RDHWR instruction) (MICROMIPSOP_*_RS)
1732
1733    "+A" 5-bit INS/EXT/DINS/DEXT/DINSM/DEXTM position, which becomes
1734         LSB (MICROMIPSOP_*_EXTLSB).
1735         Enforces: 0 <= pos < 32.
1736    "+B" 5-bit INS/DINS size, which becomes MSB (MICROMIPSOP_*_INSMSB).
1737         Requires that "+A" or "+E" occur first to set position.
1738         Enforces: 0 < (pos+size) <= 32.
1739    "+C" 5-bit EXT/DEXT size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD).
1740         Requires that "+A" or "+E" occur first to set position.
1741         Enforces: 0 < (pos+size) <= 32.
1742         (Also used by DEXT w/ different limits, but limits for
1743         that are checked by the M_DEXT macro.)
1744    "+E" 5-bit DINSU/DEXTU position, which becomes LSB-32 (MICROMIPSOP_*_EXTLSB).
1745         Enforces: 32 <= pos < 64.
1746    "+F" 5-bit DINSM/DINSU size, which becomes MSB-32 (MICROMIPSOP_*_INSMSB).
1747         Requires that "+A" or "+E" occur first to set position.
1748         Enforces: 32 < (pos+size) <= 64.
1749    "+G" 5-bit DEXTM size, which becomes MSBD-32 (MICROMIPSOP_*_EXTMSBD).
1750         Requires that "+A" or "+E" occur first to set position.
1751         Enforces: 32 < (pos+size) <= 64.
1752    "+H" 5-bit DEXTU size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD).
1753         Requires that "+A" or "+E" occur first to set position.
1754         Enforces: 32 < (pos+size) <= 64.
1755
1756    PC-relative addition (ADDIUPC) instruction:
1757    "mQ" 23-bit offset (-4194304 .. 4194303) << 2 (MICROMIPSOP_*_IMMQ)
1758    "mb" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MB) at bit 23
1759
1760    Floating point instructions:
1761    "D" 5-bit destination register (MICROMIPSOP_*_FD)
1762    "M" 3-bit compare condition code (MICROMIPSOP_*_CCC)
1763    "N" 3-bit branch condition code (MICROMIPSOP_*_BCC)
1764    "R" 5-bit fr source 3 register (MICROMIPSOP_*_FR)
1765    "S" 5-bit fs source 1 register (MICROMIPSOP_*_FS)
1766    "T" 5-bit ft source 2 register (MICROMIPSOP_*_FT)
1767    "V" 5-bit same register used as floating source and destination or target
1768        (MICROMIPSOP_*_FS)
1769
1770    Coprocessor instructions:
1771    "E" 5-bit target register (MICROMIPSOP_*_RT)
1772    "G" 5-bit destination register (MICROMIPSOP_*_RD)
1773    "H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL)
1774    "+D" combined destination register ("G") and sel ("H") for CP0 ops,
1775         for pretty-printing in disassembly only
1776
1777    Macro instructions:
1778    "A" general 32 bit expression
1779    "I" 32-bit immediate (value placed in imm_expr).
1780    "+I" 32-bit immediate (value placed in imm2_expr).
1781    "F" 64-bit floating point constant in .rdata
1782    "L" 64-bit floating point constant in .lit8
1783    "f" 32-bit floating point constant
1784    "l" 32-bit floating point constant in .lit4
1785
1786    DSP ASE usage:
1787    "2" 2-bit unsigned immediate for byte align (MICROMIPSOP_*_BP)
1788    "3" 3-bit unsigned immediate (MICROMIPSOP_*_SA3)
1789    "4" 4-bit unsigned immediate (MICROMIPSOP_*_SA4)
1790    "5" 8-bit unsigned immediate (MICROMIPSOP_*_IMM8)
1791    "6" 5-bit unsigned immediate (MICROMIPSOP_*_RS)
1792    "7" 2-bit DSP accumulator register (MICROMIPSOP_*_DSPACC)
1793    "8" 6-bit unsigned immediate (MICROMIPSOP_*_WRDSP)
1794    "0" 6-bit signed immediate (MICROMIPSOP_*_DSPSFT)
1795    "@" 10-bit signed immediate (MICROMIPSOP_*_IMM10)
1796    "^" 5-bit unsigned immediate (MICROMIPSOP_*_RD)
1797
1798    Other:
1799    "()" parens surrounding optional value
1800    ","  separates operands
1801    "+"  start of extension sequence
1802    "m"  start of microMIPS extension sequence
1803
1804    Characters used so far, for quick reference when adding more:
1805    "12345678 0"
1806    "<>(),+.@\^|~"
1807    "ABCDEFGHI KLMN   RST V    "
1808    "abcd f hijklmnopqrstuvw yz"
1809
1810    Extension character sequences used so far ("+" followed by the
1811    following), for quick reference when adding more:
1812    ""
1813    ""
1814    "ABCDEFGHI"
1815    ""
1816
1817    Extension character sequences used so far ("m" followed by the
1818    following), for quick reference when adding more:
1819    ""
1820    ""
1821    " BCDEFGHIJ LMNOPQ   U WXYZ"
1822    " bcdefghij lmn pq st   xyz"
1823 */
1824
1825 extern const struct mips_opcode micromips_opcodes[];
1826 extern const int bfd_micromips_num_opcodes;
1827
1828 /* A NOP insn impemented as "or at,at,zero".
1829    Used to implement -mfix-loongson2f.  */
1830 #define LOONGSON2F_NOP_INSN     0x00200825
1831
1832 #endif /* _MIPS_H_ */