include/opcode/ppc.h

   1 /* ppc.h -- Header file for PowerPC opcode table
   2    Copyright (C) 1994-2016 Free Software Foundation, Inc.
   3    Written by Ian Lance Taylor, Cygnus Support
   4
   5    This file is part of GDB, GAS, and the GNU binutils.
   6
   7    GDB, GAS, and the GNU binutils are free software; you can redistribute
   8    them and/or modify them under the terms of the GNU General Public
   9    License as published by the Free Software Foundation; either version 3,
  10    or (at your option) any later version.
  11
  12    GDB, GAS, and the GNU binutils are distributed in the hope that they
  13    will be useful, but WITHOUT ANY WARRANTY; without even the implied
  14    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  15    the GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this file; see the file COPYING3.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  20    MA 02110-1301, USA.  */
  21
  22 #ifndef PPC_H
  23 #define PPC_H
  24
  25 #include "bfd_stdint.h"
  26
  27 #ifdef __cplusplus
  28 extern "C" {
  29 #endif
  30
  31 typedef uint64_t ppc_cpu_t;
  32
  33 /* The opcode table is an array of struct powerpc_opcode.  */
  34
  35 struct powerpc_opcode
  36 {
  37   /* The opcode name.  */
  38   const char *name;
  39
  40   /* The opcode itself.  Those bits which will be filled in with
  41      operands are zeroes.  */
  42   unsigned long opcode;
  43
  44   /* The opcode mask.  This is used by the disassembler.  This is a
  45      mask containing ones indicating those bits which must match the
  46      opcode field, and zeroes indicating those bits which need not
  47      match (and are presumably filled in by operands).  */
  48   unsigned long mask;
  49
  50   /* One bit flags for the opcode.  These are used to indicate which
  51      specific processors support the instructions.  The defined values
  52      are listed below.  */
  53   ppc_cpu_t flags;
  54
  55   /* One bit flags for the opcode.  These are used to indicate which
  56      specific processors no longer support the instructions.  The defined
  57      values are listed below.  */
  58   ppc_cpu_t deprecated;
  59
  60   /* An array of operand codes.  Each code is an index into the
  61      operand table.  They appear in the order which the operands must
  62      appear in assembly code, and are terminated by a zero.  */
  63   unsigned char operands[8];
  64 };
  65
  66 /* The table itself is sorted by major opcode number, and is otherwise
  67    in the order in which the disassembler should consider
  68    instructions.  */
  69 extern const struct powerpc_opcode powerpc_opcodes[];
  70 extern const int powerpc_num_opcodes;
  71 extern const struct powerpc_opcode vle_opcodes[];
  72 extern const int vle_num_opcodes;
  73
  74 /* Values defined for the flags field of a struct powerpc_opcode.  */
  75
  76 /* Opcode is defined for the PowerPC architecture.  */
  77 #define PPC_OPCODE_PPC                   1
  78
  79 /* Opcode is defined for the POWER (RS/6000) architecture.  */
  80 #define PPC_OPCODE_POWER                 2
  81
  82 /* Opcode is defined for the POWER2 (Rios 2) architecture.  */
  83 #define PPC_OPCODE_POWER2                4
  84
  85 /* Opcode is supported by the Motorola PowerPC 601 processor.  The 601
  86    is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
  87    but it also supports many additional POWER instructions.  */
  88 #define PPC_OPCODE_601                   8
  89
  90 /* Opcode is supported in both the Power and PowerPC architectures
  91    (ie, compiler's -mcpu=common or assembler's -mcom).  More than just
  92    the intersection of PPC_OPCODE_PPC with the union of PPC_OPCODE_POWER
  93    and PPC_OPCODE_POWER2 because many instructions changed mnemonics
  94    between POWER and POWERPC.  */
  95 #define PPC_OPCODE_COMMON             0x10
  96
  97 /* Opcode is supported for any Power or PowerPC platform (this is
  98    for the assembler's -many option, and it eliminates duplicates).  */
  99 #define PPC_OPCODE_ANY                0x20
 100
 101 /* Opcode is only defined on 64 bit architectures.  */
 102 #define PPC_OPCODE_64                 0x40
 103
 104 /* Opcode is supported as part of the 64-bit bridge.  */
 105 #define PPC_OPCODE_64_BRIDGE          0x80
 106
 107 /* Opcode is supported by Altivec Vector Unit */
 108 #define PPC_OPCODE_ALTIVEC           0x100
 109
 110 /* Opcode is supported by PowerPC 403 processor.  */
 111 #define PPC_OPCODE_403               0x200
 112
 113 /* Opcode is supported by PowerPC BookE processor.  */
 114 #define PPC_OPCODE_BOOKE             0x400
 115
 116 /* Opcode is supported by PowerPC 440 processor.  */
 117 #define PPC_OPCODE_440               0x800
 118
 119 /* Opcode is only supported by Power4 architecture.  */
 120 #define PPC_OPCODE_POWER4           0x1000
 121
 122 /* Opcode is only supported by Power7 architecture.  */
 123 #define PPC_OPCODE_POWER7           0x2000
 124
 125 /* Opcode is only supported by e500x2 Core.  */
 126 #define PPC_OPCODE_SPE              0x4000
 127
 128 /* Opcode is supported by e500x2 Integer select APU.  */
 129 #define PPC_OPCODE_ISEL             0x8000
 130
 131 /* Opcode is an e500 SPE floating point instruction.  */
 132 #define PPC_OPCODE_EFS             0x10000
 133
 134 /* Opcode is supported by branch locking APU.  */
 135 #define PPC_OPCODE_BRLOCK          0x20000
 136
 137 /* Opcode is supported by performance monitor APU.  */
 138 #define PPC_OPCODE_PMR             0x40000
 139
 140 /* Opcode is supported by cache locking APU.  */
 141 #define PPC_OPCODE_CACHELCK        0x80000
 142
 143 /* Opcode is supported by machine check APU.  */
 144 #define PPC_OPCODE_RFMCI          0x100000
 145
 146 /* Opcode is only supported by Power5 architecture.  */
 147 #define PPC_OPCODE_POWER5         0x200000
 148
 149 /* Opcode is supported by PowerPC e300 family.  */
 150 #define PPC_OPCODE_E300           0x400000
 151
 152 /* Opcode is only supported by Power6 architecture.  */
 153 #define PPC_OPCODE_POWER6         0x800000
 154
 155 /* Opcode is only supported by PowerPC Cell family.  */
 156 #define PPC_OPCODE_CELL          0x1000000
 157
 158 /* Opcode is supported by CPUs with paired singles support.  */
 159 #define PPC_OPCODE_PPCPS         0x2000000
 160
 161 /* Opcode is supported by Power E500MC */
 162 #define PPC_OPCODE_E500MC        0x4000000
 163
 164 /* Opcode is supported by PowerPC 405 processor.  */
 165 #define PPC_OPCODE_405           0x8000000
 166
 167 /* Opcode is supported by Vector-Scalar (VSX) Unit */
 168 #define PPC_OPCODE_VSX          0x10000000
 169
 170 /* Opcode is supported by A2.  */
 171 #define PPC_OPCODE_A2           0x20000000
 172
 173 /* Opcode is supported by PowerPC 476 processor.  */
 174 #define PPC_OPCODE_476          0x40000000
 175
 176 /* Opcode is supported by AppliedMicro Titan core */
 177 #define PPC_OPCODE_TITAN        0x80000000
 178
 179 /* Opcode which is supported by the e500 family */
 180 #define PPC_OPCODE_E500        0x100000000ull
 181
 182 /* Opcode is supported by Extended Altivec Vector Unit */
 183 #define PPC_OPCODE_ALTIVEC2    0x200000000ull
 184
 185 /* Opcode is supported by Power E6500 */
 186 #define PPC_OPCODE_E6500       0x400000000ull
 187
 188 /* Opcode is supported by Thread management APU */
 189 #define PPC_OPCODE_TMR         0x800000000ull
 190
 191 /* Opcode which is supported by the VLE extension.  */
 192 #define PPC_OPCODE_VLE        0x1000000000ull
 193
 194 /* Opcode is only supported by Power8 architecture.  */
 195 #define PPC_OPCODE_POWER8     0x2000000000ull
 196
 197 /* Opcode which is supported by the Hardware Transactional Memory extension.  */
 198 /* Currently, this is the same as the POWER8 mask.  If another cpu comes out
 199    that isn't a superset of POWER8, we can define this to its own mask.  */
 200 #define PPC_OPCODE_HTM        PPC_OPCODE_POWER8
 201
 202 /* Opcode is supported by ppc750cl.  */
 203 #define PPC_OPCODE_750        0x4000000000ull
 204
 205 /* Opcode is supported by ppc7450.  */
 206 #define PPC_OPCODE_7450       0x8000000000ull
 207
 208 /* Opcode is supported by ppc821/850/860.  */
 209 #define PPC_OPCODE_860        0x10000000000ull
 210
 211 /* Opcode is only supported by Power9 architecture.  */
 212 #define PPC_OPCODE_POWER9     0x20000000000ull
 213
 214 /* Opcode is supported by Vector-Scalar (VSX) Unit from ISA 2.08.  */
 215 #define PPC_OPCODE_VSX3       0x40000000000ull
 216
 217   /* Opcode is supported by e200z4.  */
 218 #define PPC_OPCODE_E200Z4     0x80000000000ull
 219
 220 /* A macro to extract the major opcode from an instruction.  */
 221 #define PPC_OP(i) (((i) >> 26) & 0x3f)
 222
 223 /* A macro to determine if the instruction is a 2-byte VLE insn.  */
 224 #define PPC_OP_SE_VLE(m) ((m) <= 0xffff)
 225
 226 /* A macro to extract the major opcode from a VLE instruction.  */
 227 #define VLE_OP(i,m) (((i) >> ((m) <= 0xffff ? 10 : 26)) & 0x3f)
 228
 229 /* A macro to convert a VLE opcode to a VLE opcode segment.  */
 230 #define VLE_OP_TO_SEG(i) ((i) >> 1)
 231 \f
 232 /* The operands table is an array of struct powerpc_operand.  */
 233
 234 struct powerpc_operand
 235 {
 236   /* A bitmask of bits in the operand.  */
 237   unsigned int bitm;
 238
 239   /* The shift operation to be applied to the operand.  No shift
 240      is made if this is zero.  For positive values, the operand
 241      is shifted left by SHIFT.  For negative values, the operand
 242      is shifted right by -SHIFT.  Use PPC_OPSHIFT_INV to indicate
 243      that BITM and SHIFT cannot be used to determine where the
 244      operand goes in the insn.  */
 245   int shift;
 246
 247   /* Insertion function.  This is used by the assembler.  To insert an
 248      operand value into an instruction, check this field.
 249
 250      If it is NULL, execute
 251          if (o->shift >= 0)
 252            i |= (op & o->bitm) << o->shift;
 253          else
 254            i |= (op & o->bitm) >> -o->shift;
 255      (i is the instruction which we are filling in, o is a pointer to
 256      this structure, and op is the operand value).
 257
 258      If this field is not NULL, then simply call it with the
 259      instruction and the operand value.  It will return the new value
 260      of the instruction.  If the ERRMSG argument is not NULL, then if
 261      the operand value is illegal, *ERRMSG will be set to a warning
 262      string (the operand will be inserted in any case).  If the
 263      operand value is legal, *ERRMSG will be unchanged (most operands
 264      can accept any value).  */
 265   unsigned long (*insert)
 266     (unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg);
 267
 268   /* Extraction function.  This is used by the disassembler.  To
 269      extract this operand type from an instruction, check this field.
 270
 271      If it is NULL, compute
 272          if (o->shift >= 0)
 273            op = (i >> o->shift) & o->bitm;
 274          else
 275            op = (i << -o->shift) & o->bitm;
 276          if ((o->flags & PPC_OPERAND_SIGNED) != 0)
 277            sign_extend (op);
 278      (i is the instruction, o is a pointer to this structure, and op
 279      is the result).
 280
 281      If this field is not NULL, then simply call it with the
 282      instruction value.  It will return the value of the operand.  If
 283      the INVALID argument is not NULL, *INVALID will be set to
 284      non-zero if this operand type can not actually be extracted from
 285      this operand (i.e., the instruction does not match).  If the
 286      operand is valid, *INVALID will not be changed.  */
 287   long (*extract) (unsigned long instruction, ppc_cpu_t dialect, int *invalid);
 288
 289   /* One bit syntax flags.  */
 290   unsigned long flags;
 291 };
 292
 293 /* Elements in the table are retrieved by indexing with values from
 294    the operands field of the powerpc_opcodes table.  */
 295
 296 extern const struct powerpc_operand powerpc_operands[];
 297 extern const unsigned int num_powerpc_operands;
 298
 299 /* Use with the shift field of a struct powerpc_operand to indicate
 300      that BITM and SHIFT cannot be used to determine where the operand
 301      goes in the insn.  */
 302 #define PPC_OPSHIFT_INV (-1U << 31)
 303
 304 /* Values defined for the flags field of a struct powerpc_operand.  */
 305
 306 /* This operand takes signed values.  */
 307 #define PPC_OPERAND_SIGNED (0x1)
 308
 309 /* This operand takes signed values, but also accepts a full positive
 310    range of values when running in 32 bit mode.  That is, if bits is
 311    16, it takes any value from -0x8000 to 0xffff.  In 64 bit mode,
 312    this flag is ignored.  */
 313 #define PPC_OPERAND_SIGNOPT (0x2)
 314
 315 /* This operand does not actually exist in the assembler input.  This
 316    is used to support extended mnemonics such as mr, for which two
 317    operands fields are identical.  The assembler should call the
 318    insert function with any op value.  The disassembler should call
 319    the extract function, ignore the return value, and check the value
 320    placed in the valid argument.  */
 321 #define PPC_OPERAND_FAKE (0x4)
 322
 323 /* The next operand should be wrapped in parentheses rather than
 324    separated from this one by a comma.  This is used for the load and
 325    store instructions which want their operands to look like
 326        reg,displacement(reg)
 327    */
 328 #define PPC_OPERAND_PARENS (0x8)
 329
 330 /* This operand may use the symbolic names for the CR fields, which
 331    are
 332        lt  0    gt  1   eq  2   so  3   un  3
 333        cr0 0    cr1 1   cr2 2   cr3 3
 334        cr4 4    cr5 5   cr6 6   cr7 7
 335    These may be combined arithmetically, as in cr2*4+gt.  These are
 336    only supported on the PowerPC, not the POWER.  */
 337 #define PPC_OPERAND_CR_BIT (0x10)
 338
 339 /* This operand names a register.  The disassembler uses this to print
 340    register names with a leading 'r'.  */
 341 #define PPC_OPERAND_GPR (0x20)
 342
 343 /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0.  */
 344 #define PPC_OPERAND_GPR_0 (0x40)
 345
 346 /* This operand names a floating point register.  The disassembler
 347    prints these with a leading 'f'.  */
 348 #define PPC_OPERAND_FPR (0x80)
 349
 350 /* This operand is a relative branch displacement.  The disassembler
 351    prints these symbolically if possible.  */
 352 #define PPC_OPERAND_RELATIVE (0x100)
 353
 354 /* This operand is an absolute branch address.  The disassembler
 355    prints these symbolically if possible.  */
 356 #define PPC_OPERAND_ABSOLUTE (0x200)
 357
 358 /* This operand is optional, and is zero if omitted.  This is used for
 359    example, in the optional BF field in the comparison instructions.  The
 360    assembler must count the number of operands remaining on the line,
 361    and the number of operands remaining for the opcode, and decide
 362    whether this operand is present or not.  The disassembler should
 363    print this operand out only if it is not zero.  */
 364 #define PPC_OPERAND_OPTIONAL (0x400)
 365
 366 /* This flag is only used with PPC_OPERAND_OPTIONAL.  If this operand
 367    is omitted, then for the next operand use this operand value plus
 368    1, ignoring the next operand field for the opcode.  This wretched
 369    hack is needed because the Power rotate instructions can take
 370    either 4 or 5 operands.  The disassembler should print this operand
 371    out regardless of the PPC_OPERAND_OPTIONAL field.  */
 372 #define PPC_OPERAND_NEXT (0x800)
 373
 374 /* This operand should be regarded as a negative number for the
 375    purposes of overflow checking (i.e., the normal most negative
 376    number is disallowed and one more than the normal most positive
 377    number is allowed).  This flag will only be set for a signed
 378    operand.  */
 379 #define PPC_OPERAND_NEGATIVE (0x1000)
 380
 381 /* This operand names a vector unit register.  The disassembler
 382    prints these with a leading 'v'.  */
 383 #define PPC_OPERAND_VR (0x2000)
 384
 385 /* This operand is for the DS field in a DS form instruction.  */
 386 #define PPC_OPERAND_DS (0x4000)
 387
 388 /* This operand is for the DQ field in a DQ form instruction.  */
 389 #define PPC_OPERAND_DQ (0x8000)
 390
 391 /* Valid range of operand is 0..n rather than 0..n-1.  */
 392 #define PPC_OPERAND_PLUS1 (0x10000)
 393
 394 /* Xilinx APU and FSL related operands */
 395 #define PPC_OPERAND_FSL (0x20000)
 396 #define PPC_OPERAND_FCR (0x40000)
 397 #define PPC_OPERAND_UDI (0x80000)
 398
 399 /* This operand names a vector-scalar unit register.  The disassembler
 400    prints these with a leading 'vs'.  */
 401 #define PPC_OPERAND_VSR (0x100000)
 402
 403 /* This is a CR FIELD that does not use symbolic names.  */
 404 #define PPC_OPERAND_CR_REG (0x200000)
 405
 406 /* This flag is only used with PPC_OPERAND_OPTIONAL.  If this operand
 407    is omitted, then the value it should use for the operand is stored
 408    in the SHIFT field of the immediatly following operand field.  */
 409 #define PPC_OPERAND_OPTIONAL_VALUE (0x400000)
 410
 411 /* This flag is only used with PPC_OPERAND_OPTIONAL.  The operand is
 412    only optional when generating 32-bit code.  */
 413 #define PPC_OPERAND_OPTIONAL32 (0x800000)
 414 \f
 415 /* The POWER and PowerPC assemblers use a few macros.  We keep them
 416    with the operands table for simplicity.  The macro table is an
 417    array of struct powerpc_macro.  */
 418
 419 struct powerpc_macro
 420 {
 421   /* The macro name.  */
 422   const char *name;
 423
 424   /* The number of operands the macro takes.  */
 425   unsigned int operands;
 426
 427   /* One bit flags for the opcode.  These are used to indicate which
 428      specific processors support the instructions.  The values are the
 429      same as those for the struct powerpc_opcode flags field.  */
 430   ppc_cpu_t flags;
 431
 432   /* A format string to turn the macro into a normal instruction.
 433      Each %N in the string is replaced with operand number N (zero
 434      based).  */
 435   const char *format;
 436 };
 437
 438 extern const struct powerpc_macro powerpc_macros[];
 439 extern const int powerpc_num_macros;
 440
 441 extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *);
 442
 443 static inline long
 444 ppc_optional_operand_value (const struct powerpc_operand *operand)
 445 {
 446   if ((operand->flags & PPC_OPERAND_OPTIONAL_VALUE) != 0)
 447     return (operand+1)->shift;
 448   return 0;
 449 }
 450
 451 /* PowerPC VLE insns.  */
 452 /* Form I16L, uses 16A relocs.  */
 453 #define E_OR2I_INSN             0x7000C000
 454 #define E_AND2I_DOT_INSN        0x7000C800
 455 #define E_OR2IS_INSN            0x7000D000
 456 #define E_LIS_INSN              0x7000E000
 457 #define E_AND2IS_DOT_INSN       0x7000E800
 458
 459 /* Form I16A, uses 16D relocs.  */
 460 #define E_ADD2I_DOT_INSN        0x70008800
 461 #define E_ADD2IS_INSN           0x70009000
 462 #define E_CMP16I_INSN           0x70009800
 463 #define E_MULL2I_INSN           0x7000A000
 464 #define E_CMPL16I_INSN          0x7000A800
 465 #define E_CMPH16I_INSN          0x7000B000
 466 #define E_CMPHL16I_INSN         0x7000B800
 467
 468 #ifdef __cplusplus
 469 }
 470 #endif
 471
 472 #endif /* PPC_H */