include/opcode/ppc.h

   1 /* ppc.h -- Header file for PowerPC opcode table
   2    Copyright 1994, 1995, 1999, 2000, 2001, 2002
   3    Free Software Foundation, Inc.
   4    Written by Ian Lance Taylor, Cygnus Support
   5
   6 This file is part of GDB, GAS, and the GNU binutils.
   7
   8 GDB, GAS, and the GNU binutils are free software; you can redistribute
   9 them and/or modify them under the terms of the GNU General Public
  10 License as published by the Free Software Foundation; either version
  11 1, or (at your option) any later version.
  12
  13 GDB, GAS, and the GNU binutils are distributed in the hope that they
  14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  16 the GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with this file; see the file COPYING.  If not, write to the Free
  20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  21
  22 #ifndef PPC_H
  23 #define PPC_H
  24
  25 /* The opcode table is an array of struct powerpc_opcode.  */
  26
  27 struct powerpc_opcode
  28 {
  29   /* The opcode name.  */
  30   const char *name;
  31
  32   /* The opcode itself.  Those bits which will be filled in with
  33      operands are zeroes.  */
  34   unsigned long opcode;
  35
  36   /* The opcode mask.  This is used by the disassembler.  This is a
  37      mask containing ones indicating those bits which must match the
  38      opcode field, and zeroes indicating those bits which need not
  39      match (and are presumably filled in by operands).  */
  40   unsigned long mask;
  41
  42   /* One bit flags for the opcode.  These are used to indicate which
  43      specific processors support the instructions.  The defined values
  44      are listed below.  */
  45   unsigned long flags;
  46
  47   /* An array of operand codes.  Each code is an index into the
  48      operand table.  They appear in the order which the operands must
  49      appear in assembly code, and are terminated by a zero.  */
  50   unsigned char operands[8];
  51 };
  52
  53 /* The table itself is sorted by major opcode number, and is otherwise
  54    in the order in which the disassembler should consider
  55    instructions.  */
  56 extern const struct powerpc_opcode powerpc_opcodes[];
  57 extern const int powerpc_num_opcodes;
  58
  59 /* Values defined for the flags field of a struct powerpc_opcode.  */
  60
  61 /* Opcode is defined for the PowerPC architecture.  */
  62 #define PPC_OPCODE_PPC (01)
  63
  64 /* Opcode is defined for the POWER (RS/6000) architecture.  */
  65 #define PPC_OPCODE_POWER (02)
  66
  67 /* Opcode is defined for the POWER2 (Rios 2) architecture.  */
  68 #define PPC_OPCODE_POWER2 (04)
  69
  70 /* Opcode is only defined on 32 bit architectures.  */
  71 #define PPC_OPCODE_32 (010)
  72
  73 /* Opcode is only defined on 64 bit architectures.  */
  74 #define PPC_OPCODE_64 (020)
  75
  76 /* Opcode is supported by the Motorola PowerPC 601 processor.  The 601
  77    is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
  78    but it also supports many additional POWER instructions.  */
  79 #define PPC_OPCODE_601 (040)
  80
  81 /* Opcode is supported in both the Power and PowerPC architectures
  82    (ie, compiler's -mcpu=common or assembler's -mcom).  */
  83 #define PPC_OPCODE_COMMON (0100)
  84
  85 /* Opcode is supported for any Power or PowerPC platform (this is
  86    for the assembler's -many option, and it eliminates duplicates).  */
  87 #define PPC_OPCODE_ANY (0200)
  88
  89 /* Opcode is supported as part of the 64-bit bridge.  */
  90 #define PPC_OPCODE_64_BRIDGE (0400)
  91
  92 /* Opcode is supported by Altivec Vector Unit */
  93 #define PPC_OPCODE_ALTIVEC (01000)
  94
  95 /* Opcode is supported by PowerPC 403 processor.  */
  96 #define PPC_OPCODE_403 (02000)
  97
  98 /* Opcode is supported by PowerPC BookE processor.  */
  99 #define PPC_OPCODE_BOOKE (04000)
 100
 101 /* Opcode is only supported by 64-bit PowerPC BookE processor.  */
 102 #define PPC_OPCODE_BOOKE64 (010000)
 103
 104 /* Opcode is only supported by Power4 architecture.  */
 105 #define PPC_OPCODE_POWER4 (020000)
 106
 107 /* Opcode isn't supported by Power4 architecture.  */
 108 #define PPC_OPCODE_NOPOWER4 (040000)
 109
 110 /* Opcode is only supported by POWERPC Classic architecture.  */
 111 #define PPC_OPCODE_CLASSIC (0100000)
 112
 113 /* Opcode is only supported by e500x2 Core.  */
 114 #define PPC_OPCODE_SPE     (0200000)
 115
 116 /* Opcode is supported by e500x2 Integer select APU.  */
 117 #define PPC_OPCODE_ISEL     (0400000)
 118
 119 /* Opcode is an e500 SPE floating point instruction.  */
 120 #define PPC_OPCODE_EFS      (01000000)
 121
 122 /* Opcode is supported by branch locking APU.  */
 123 #define PPC_OPCODE_BRLOCK   (02000000)
 124
 125 /* Opcode is supported by performance monitor APU.  */
 126 #define PPC_OPCODE_PMR      (04000000)
 127
 128 /* Opcode is supported by cache locking APU.  */
 129 #define PPC_OPCODE_CACHELCK (010000000)
 130
 131 /* Opcode is supported by machine check APU.  */
 132 #define PPC_OPCODE_RFMCI    (020000000)
 133
 134 /* A macro to extract the major opcode from an instruction.  */
 135 #define PPC_OP(i) (((i) >> 26) & 0x3f)
 136 \f
 137 /* The operands table is an array of struct powerpc_operand.  */
 138
 139 struct powerpc_operand
 140 {
 141   /* The number of bits in the operand.  */
 142   int bits;
 143
 144   /* How far the operand is left shifted in the instruction.  */
 145   int shift;
 146
 147   /* Insertion function.  This is used by the assembler.  To insert an
 148      operand value into an instruction, check this field.
 149
 150      If it is NULL, execute
 151          i |= (op & ((1 << o->bits) - 1)) << o->shift;
 152      (i is the instruction which we are filling in, o is a pointer to
 153      this structure, and op is the opcode value; this assumes twos
 154      complement arithmetic).
 155
 156      If this field is not NULL, then simply call it with the
 157      instruction and the operand value.  It will return the new value
 158      of the instruction.  If the ERRMSG argument is not NULL, then if
 159      the operand value is illegal, *ERRMSG will be set to a warning
 160      string (the operand will be inserted in any case).  If the
 161      operand value is legal, *ERRMSG will be unchanged (most operands
 162      can accept any value).  */
 163   unsigned long (*insert) PARAMS ((unsigned long instruction, long op,
 164                                    int dialect,
 165                                    const char **errmsg));
 166
 167   /* Extraction function.  This is used by the disassembler.  To
 168      extract this operand type from an instruction, check this field.
 169
 170      If it is NULL, compute
 171          op = ((i) >> o->shift) & ((1 << o->bits) - 1);
 172          if ((o->flags & PPC_OPERAND_SIGNED) != 0
 173              && (op & (1 << (o->bits - 1))) != 0)
 174            op -= 1 << o->bits;
 175      (i is the instruction, o is a pointer to this structure, and op
 176      is the result; this assumes twos complement arithmetic).
 177
 178      If this field is not NULL, then simply call it with the
 179      instruction value.  It will return the value of the operand.  If
 180      the INVALID argument is not NULL, *INVALID will be set to
 181      non-zero if this operand type can not actually be extracted from
 182      this operand (i.e., the instruction does not match).  If the
 183      operand is valid, *INVALID will not be changed.  */
 184   long (*extract) PARAMS ((unsigned long instruction, int dialect,
 185                            int *invalid));
 186
 187   /* One bit syntax flags.  */
 188   unsigned long flags;
 189 };
 190
 191 /* Elements in the table are retrieved by indexing with values from
 192    the operands field of the powerpc_opcodes table.  */
 193
 194 extern const struct powerpc_operand powerpc_operands[];
 195
 196 /* Values defined for the flags field of a struct powerpc_operand.  */
 197
 198 /* This operand takes signed values.  */
 199 #define PPC_OPERAND_SIGNED (01)
 200
 201 /* This operand takes signed values, but also accepts a full positive
 202    range of values when running in 32 bit mode.  That is, if bits is
 203    16, it takes any value from -0x8000 to 0xffff.  In 64 bit mode,
 204    this flag is ignored.  */
 205 #define PPC_OPERAND_SIGNOPT (02)
 206
 207 /* This operand does not actually exist in the assembler input.  This
 208    is used to support extended mnemonics such as mr, for which two
 209    operands fields are identical.  The assembler should call the
 210    insert function with any op value.  The disassembler should call
 211    the extract function, ignore the return value, and check the value
 212    placed in the valid argument.  */
 213 #define PPC_OPERAND_FAKE (04)
 214
 215 /* The next operand should be wrapped in parentheses rather than
 216    separated from this one by a comma.  This is used for the load and
 217    store instructions which want their operands to look like
 218        reg,displacement(reg)
 219    */
 220 #define PPC_OPERAND_PARENS (010)
 221
 222 /* This operand may use the symbolic names for the CR fields, which
 223    are
 224        lt  0    gt  1   eq  2   so  3   un  3
 225        cr0 0    cr1 1   cr2 2   cr3 3
 226        cr4 4    cr5 5   cr6 6   cr7 7
 227    These may be combined arithmetically, as in cr2*4+gt.  These are
 228    only supported on the PowerPC, not the POWER.  */
 229 #define PPC_OPERAND_CR (020)
 230
 231 /* This operand names a register.  The disassembler uses this to print
 232    register names with a leading 'r'.  */
 233 #define PPC_OPERAND_GPR (040)
 234
 235 /* This operand names a floating point register.  The disassembler
 236    prints these with a leading 'f'.  */
 237 #define PPC_OPERAND_FPR (0100)
 238
 239 /* This operand is a relative branch displacement.  The disassembler
 240    prints these symbolically if possible.  */
 241 #define PPC_OPERAND_RELATIVE (0200)
 242
 243 /* This operand is an absolute branch address.  The disassembler
 244    prints these symbolically if possible.  */
 245 #define PPC_OPERAND_ABSOLUTE (0400)
 246
 247 /* This operand is optional, and is zero if omitted.  This is used for
 248    the optional BF and L fields in the comparison instructions.  The
 249    assembler must count the number of operands remaining on the line,
 250    and the number of operands remaining for the opcode, and decide
 251    whether this operand is present or not.  The disassembler should
 252    print this operand out only if it is not zero.  */
 253 #define PPC_OPERAND_OPTIONAL (01000)
 254
 255 /* This flag is only used with PPC_OPERAND_OPTIONAL.  If this operand
 256    is omitted, then for the next operand use this operand value plus
 257    1, ignoring the next operand field for the opcode.  This wretched
 258    hack is needed because the Power rotate instructions can take
 259    either 4 or 5 operands.  The disassembler should print this operand
 260    out regardless of the PPC_OPERAND_OPTIONAL field.  */
 261 #define PPC_OPERAND_NEXT (02000)
 262
 263 /* This operand should be regarded as a negative number for the
 264    purposes of overflow checking (i.e., the normal most negative
 265    number is disallowed and one more than the normal most positive
 266    number is allowed).  This flag will only be set for a signed
 267    operand.  */
 268 #define PPC_OPERAND_NEGATIVE (04000)
 269
 270 /* This operand names a vector unit register.  The disassembler
 271    prints these with a leading 'v'.  */
 272 #define PPC_OPERAND_VR (010000)
 273
 274 /* This operand is for the DS field in a DS form instruction.  */
 275 #define PPC_OPERAND_DS (020000)
 276 \f
 277 /* The POWER and PowerPC assemblers use a few macros.  We keep them
 278    with the operands table for simplicity.  The macro table is an
 279    array of struct powerpc_macro.  */
 280
 281 struct powerpc_macro
 282 {
 283   /* The macro name.  */
 284   const char *name;
 285
 286   /* The number of operands the macro takes.  */
 287   unsigned int operands;
 288
 289   /* One bit flags for the opcode.  These are used to indicate which
 290      specific processors support the instructions.  The values are the
 291      same as those for the struct powerpc_opcode flags field.  */
 292   unsigned long flags;
 293
 294   /* A format string to turn the macro into a normal instruction.
 295      Each %N in the string is replaced with operand number N (zero
 296      based).  */
 297   const char *format;
 298 };
 299
 300 extern const struct powerpc_macro powerpc_macros[];
 301 extern const int powerpc_num_macros;
 302
 303 #endif /* PPC_H */